TW201532386A - Output buffer capable of rapidly switching gate potential and electrostatic protection circuit - Google Patents

Abstract

The present invention relates to an output buffer capable of rapidly switching gate potential, and its electrostatic protection circuit, wherein the output buffer comprises an abnormal potential detection unit, a gate potential switching unit and an output buffer unit, wherein the output buffer unit is connected to a corresponding signal end of an integrated circuit internal circuit via the abnormal potential detection unit and the gate potential switching unit, and shares the same DC power set therewith. When the DC power potential sharply rises abnormally, such as when the static charges enters the output pad, the abnormal potential detection unit will first detect the event and activates the gate potential switching unit for rapidly switching the gate potential of the PMOS transistor element and NMOS transistor element of the output buffer unit to the high potential terminal and low potential terminal corresponding to the DC power, thereby avoiding abnormal sudden change of the potential from breaking the MOS transistor element of output buffer unit with unknown gate floating potential state.

Description

Output buffer and static protection circuit for quickly switching gate potential

The present invention relates to an integrated circuit output buffer, and more particularly to an output buffer capable of quickly switching a gate potential and an electrostatic protection circuit thereof.

Referring to FIG. 4, an integrated circuit 50 having a digital input/output interface generally has an output buffer 52 interposed between each signal output end of the internal circuit 51 and the corresponding output pad 53 to ensure the output signal potential thereof. It is high or low. In the integrated circuit 50 of a common 5V or 3.3V operating DC voltage, the output pad 53 or the power terminals V _DD , V _{SS are} prone to static electricity V _ESD , and therefore, the PMOS transistor element or NMOS device that passes through the output buffer 52 The parasitic forward diode D1 and the parasitic reverse diode D2 of the crystal element introduce positive or negative static voltage V _ESD into the high potential terminal V _DD or the low potential terminal V _{SS of the} DC power source, and the static electricity is directly penetrated due to the high voltage. Internal circuit 51. In this regard, the output buffer 52 is usually connected to a static electricity protection circuit (not shown) to form a pair of ground discharge paths when the static electricity V _{ESD is} generated, so that the electrostatic current I _{ESD is} quickly discharged to the ground. The semiconductor electronic components of the internal circuit 51 are prevented from being damaged.

In fact, although the addition of the ESD protection circuit ensures that the internal circuit 51 of the integrated circuit is not damaged by the electrostatic current, the output buffer 52 between the internal circuit 51 and the output pad 53 is susceptible to electrostatic damage due to: When the internal circuit 51 is in normal operation, its output signal determines the gate potential of the output buffer 52, and controls the PMOS or NMOS transistor elements PM1, PN1 to be turned on, and the voltage level is measured from the output pad 53; When the operation interval or sleep is 51, the internal circuit 51 does not output a signal to the output buffer 52. At this time, the gate potential of the output buffer 52 is unknown, which is generally called gate floating connection, and may be high potential. May be low. For this reason, when static electricity is generated, if any of the PMOS or NMOS transistors MP1 and MN1 of the output buffer are turned on, the electrostatic protection circuit does not have time to trigger the start discharge mechanism, and the turned-on MOS transistor has been provided for the electrostatic V _ESD . An optimal discharge path, which causes large electrostatic currents to flow instantaneously and be damaged.

Therefore, it is necessary to further improve the output buffer of the integrated circuit to prevent damage due to the occurrence of static electricity.

The main object of the present invention is to provide an output buffer and an electrostatic protection circuit capable of rapidly switching the gate potential, thereby ensuring that the gate potential of the output buffer can be quickly switched when the static electricity is generated, so that the MOS transistor element is turned off and not turned on.

The main technical means used to achieve the above purpose is that the output buffer capable of rapidly switching the gate potential includes: an abnormal potential detecting unit serially connected to the DC power source to detect when the DC power potential is abnormal. a trigger signal; a gate potential switching unit is connected in series with the DC power source and connected to the abnormal potential detecting unit, and receives the trigger signal to trigger to output a two-gate potential switching signal; and an output buffer unit Connected to the DC power supply, and includes a PMOS transistor component and an NMOS transistor component, wherein the PMOS transistor component and the second gate of the NMOS transistor component are respectively connected to the gate potential switching unit, The gate potential switching unit determines its gate potential.

In the above invention, the output buffer unit is connected to the corresponding signal terminal of the internal circuit of an integrated circuit through the abnormal potential detecting unit and the gate potential switching unit, and uses the same group DC power source as the DC power supply potential. If it is abnormally steeped by static electricity, it is first detected by the abnormal potential detecting unit, and the gate potential switching unit is triggered and activated to quickly switch the gate potential of the PMOS transistor component and the NMOS transistor component of the output buffer unit. To the high-potential and low-potential terminals of the corresponding DC power supply, the PMOS and NMOS transistor components are turned off and non-conducting to avoid abnormally rising or steeply dropping the potential to damage the PMOS or NMOS transistor component due to the floating gate.

The main technical means used to achieve the above purpose is that the static protection circuit includes: an abnormal potential detecting unit connected in series with the DC power source to detect a trigger signal when the DC power source is abnormal; a gate potential The switching unit is connected in series with the DC power source and connected to the abnormal potential detecting unit, and is triggered by the trigger signal to output a two-gate potential switching signal; an output buffer unit is serially connected to the DC power source And comprising a PMOS transistor component, an NMOS transistor component, and an output pad connected to the PMOS and NMOS transistor component, wherein the PMOS transistor component and the NMOS transistor component have two gates connected to the gate respectively a potential switching unit, wherein the gate potential is determined by the gate potential switching unit; and an electrostatic protection unit is connected to the output pad of the output buffer unit to detect an abnormal potential generated by static electricity, and detecting an abnormality The potential constitutes a discharge path to a low potential of the DC power source; wherein the electrostatic protection circuit detects that the abnormal potential system is higher than the abnormal potential detection unit The abnormal potential.

The electrostatic protection circuit of the present invention adds an electrostatic protection unit to the output buffer unit to quickly form a discharge path when detecting an abnormal potential caused by static electricity, and quickly introduces the electrostatic current into the low potential of the DC power source to avoid recirculation to the product. The internal circuit of the body circuit causes damage.

The present invention is directed to the output stage circuit of the integrated circuit which is susceptible to damage due to the abnormal potential due to the floating gate, so the following solution is proposed.

Referring to FIG. 1 , it is a detailed circuit diagram of a preferred embodiment of the output buffer 10 of the present invention. The output buffer 10 includes an abnormal potential detecting unit 11 , a gate potential switching unit 12 , and a first The buffer unit 13 is output. The output buffer unit 13 includes a first PMOS transistor element MP1, a first NMOS transistor element MN1, and an output pad 22, wherein the first PMOS transistor element MP1 and the first NMOS transistor element MN1 are two The gate G is connected to the gate potential switching unit 12, and the gate potential switching unit 12 determines the potential of the gate G. Further, a drain-to-source diode D1 is connected to the drain D to the source S of the first PMOS transistor device MP1, and a parasitic reverse diode is connected to the drain D to the source S of the second NMOS transistor device MN1. Body D2. The output pad 22 is connected to the serial connection node of the first PMOS transistor element MP1 and the first NMOS transistor element MN1.

The abnormal potential detecting unit 11 is connected in series between the high and low potential terminals V _DD and V _{SS of the} DC power source to detect that the static electricity enters the input pad 22, causing the potential of the DC power source to be abnormal and generating an abnormal potential. Provide a trigger signal. In this embodiment, the abnormal potential detecting unit 11 includes: a register diode Z1 whose cathode is connected to the high potential terminal V _{DD of} the DC power source, and the breakdown voltage of the Zener diode Z1. More than the normal operating potential of the DC power supply, the 5V integrated circuit of the DC power supply voltage is taken as an example, and the Zener diode Z1 with a breakdown voltage of 7V or more can be used to ensure that the DC power supply does not enter a collapse state when the DC power supply is at a normal potential. The arrester diode Z1 with a breakdown voltage of 7V represents that the abnormal potential detecting unit presets an abnormal potential of 7V or more; and a resistor R1 is connected in series with the anode of the Zener diode Z1 and the DC power source. Low potential between V _SS .

Referring to FIG. 2A again, it is assumed that the current I _{ESD of the} positive static voltage V _ESD is injected from an output pad 22 of the integrated circuit, and is transmitted through the parasitic forward diode D1 of the first PMOS transistor element MP1 of the output buffer unit 13 . The high-potential terminal V _DD flowing into the DC power supply causes its potential to rise abnormally. When the breakdown voltage of the Zener diode Z1 is exceeded, the Zener diode Z1 collapses and simultaneously generates a breakdown current Iz, which flows through the The resistor R1 forms a voltage drop V _R on the resistor R1. Conversely, if the DC power source is maintained at the normal operating potential, the Zener diode Z1 does not enter a collapse state, and there is no voltage drop generated on the resistor. , as shown in Figure 2B.

The gate potential switching unit 12 of the present embodiment includes a second PMOS transistor element MP2 and a second NMOS transistor element MN2. The source S of the second PMOS transistor element MP2 is connected to the high potential terminal V _{DD of} the DC power source, and the drain D is connected to the gate G of the first PMOS transistor element MP1 of the output buffer unit 13 The source S of the second NMOS transistor element MN2 is connected to the low potential terminal V _{SS of} the DC power source, and the drain D is connected to the gate G of the first NMOS transistor element MN1 of the output buffer unit 13 . In addition, the gate G of the second NMOS transistor element MN2 is further connected to the gate G of the second PMOS transistor element MP2 through an inverter INV, and is connected to the abnormal potential detection unit 11 The diode Z1 and the resistor R1 are connected in series with the node N1.

Thus, when the resistor R1 is subjected to the voltage drop V _R generated by the mined breakdown current I _Z , the forward bias between the gate and the source G, S of the second NMOS transistor element MN2 can be provided. V _GS , the second NMOS transistor element MN2 is turned on, since the input terminal of the inverter INV is connected to the gate G of the second PMOS transistor element MP2, the second NMOS transistor is provided at the resistor R1 While the gate G of the component NM2 is forward biased +V _GS , the inverter INV outputs a relatively low potential to the gate G of the second PMOS transistor element MP2; and because of the second PMOS transistor The source S of the component MP2 is connected to the high potential terminal V _{DD of} the DC power source, so that the second PMOS transistor component MP2 obtains a reverse voltage -V when the inverter INV outputs a relatively low potential. _GS is turned on.

It can be seen from the above description that when the DC power source exhibits an abnormal potential higher than the breakdown voltage of the Zener diode Z1, the second PMOS and NMOS transistor components are turned on; at this time, the second PMOS and NMOS transistors are turned on. The diodes D of the elements MP2 and MN2 are respectively connected to the second gates G of the first PMOS and NMOS transistor elements MP1 and MN1 of the output buffer unit 13, so that the gate G of the first PMOS transistor element MP1 is turned on. The second PMOS transistor element MP2 is connected to the high potential terminal V _{DD of} the DC power source, and the gate G of the first NMOS transistor element MN1 is connected to the DC power source through the turned-on second NMOS transistor element MN2. Low potential terminal V _SS to ensure that the first PMOS and NMOS transistors MP1, MN1 are not turned on, so that the first PMOS of the output buffer unit 13 and the two gates G of the NMOS transistor elements MP1, MN1 are no longer floating The potential is unknown and may be susceptible to damage due to the abnormal potential generated by static electricity.

Referring to FIG. 2B, the abnormal potential detecting unit 11 and the gate potential switching unit 12 of the present invention do not affect the normal output of the PMOS and NMOS transistors MP1 and MP2 of the output circuit unit 13 by the internal circuit 21 of the integrated circuit. Switch actions. Since the DC power supply is in normal operation, the generator diode Z1 of the abnormal potential detecting unit 11 does not collapse and generates a large current, so that the resistor R1 does not have a voltage drop, which is insufficient for the gate potential switching unit 12 to be generated. The second PMOS and NMOS transistor elements MP2, MN2 are turned on to change the two-gate potential of the output buffer unit 13. Furthermore, since the second PMOS of the gate potential switching unit 12 and the two gates G of the NMOS transistor elements MP2 and MN2 are commonly connected to the abnormal potential detecting unit 11, and only the two drains D are respectively connected to the The two gates G of the output buffer unit 13 are outputted. Therefore, when the internal circuit 21 outputs the high and low potential signals to the two gates G of the output buffer unit 13, the second PMOS and NMOS transistor elements MP2 and MN2 are not turned on. The potential of the two gates G of the output buffer unit 13 is changed.

The above is the circuit improvement and circuit operation description of the output buffer of the general integrated circuit of the present invention. The following is a further description of the present invention, which is disposed between the high and low potential ends of the DC power supply of the internal circuit of the integrated circuit, or internal. Electrostatic protection circuit between the circuit and the output pad.

A preferred embodiment of the ESD protection circuit of the present invention is shown in FIG. 3. The ESD protection circuit 30 includes the output buffer 10 and an ESD protection unit 31. The ESD protection unit 31 can detect an abnormality caused by static electricity. a potential, and a discharge path of a low potential V _SS to the DC power source when the abnormal potential is detected; wherein the electrostatic protection circuit 31 detects that the abnormal potential is higher than the abnormal potential detected by the abnormal potential detecting unit 11 For example, a pilot rectifier with a low trigger voltage of less than 30V, that is, a Jensor diode Z1 with a breakdown voltage greater than 7V is used. The static electricity protection circuit of the invention is a low-trigger voltage controlled rectifier and its functionally identical components, so it is not limited to the controlled rectifier.

In this embodiment, when the static electricity generation V _{ESD is} generated, the controlled rectifier will trigger the conduction when the electrostatic voltage is greater than 30V, that is, the gates of the first PMOS and NMOS transistor elements MP1 and MN1 of the output buffer unit 13 are first controlled. G potential, so that it does not turn off, when the electrostatic voltage rises above 30V, the 矽-controlled rectifier is activated, and the electrostatic current I _SED is quickly bypassed, and the potential of the high-potential terminal V _DD of the DC power supply drops less than 7V, the gate potential switching unit 12 of the output buffer 10 no longer controls the gate G potential of the first PMOS and NMOS transistor elements MP1, MN1 of the output buffer unit 13.

It can be seen from the above description that the abnormal potential detecting unit and the gate potential switching unit added to the output buffer unit of the present invention can surely close the transistor element of the output buffer unit before the static protection circuit has been triggered to ensure that it is not The electrostatic protection circuit of the present invention does have two relatively high and low abnormal potential protections, and increases the electrostatic protection effect of the integrated circuit semiconductor components.

The integrated circuit using the 5V DC power supply is exemplified as a low-voltage integrated circuit, and the present invention is also applicable to a high-voltage integrated circuit, but the abnormal diode of the abnormal potential detecting unit, the resistor, and the gate The PMOS and NMOS transistor elements of the potential switching unit are selected according to the high voltage range used by the integrated circuit; therefore, the PMOS and NMOS transistor elements of the gate potential switching unit of the present invention may be low voltage or high voltage semiconductor elements.

The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way. Although the present invention has been disclosed above in the preferred embodiments, it is not intended to limit the present invention. A person skilled in the art can make some modifications or modifications to the equivalent embodiment by using the technical content disclosed above, without departing from the technical solution of the present invention, without departing from the technical solution of the present invention. Any simple modifications, equivalent changes and modifications made to the above embodiments in accordance with the technical spirit of the present invention are still within the scope of the technical solutions of the present invention.

10‧‧‧Output buffer
11‧‧‧Abnormal potential detection unit
12‧‧‧ Gate potential switching unit
13‧‧‧Output buffer unit
21‧‧‧Internal circuits
22‧‧‧Output pad
30‧‧‧Electrostatic protection circuit
31‧‧‧Electrostatic protection unit
50‧‧‧Integrated circuit
51‧‧‧Internal circuits
52‧‧‧Output buffer
53‧‧‧ Output埠

Figure 1 is a detailed circuit diagram of an ESD protection circuit of the output buffer of the present invention.

Fig. 2A is a circuit operation diagram of Fig. 1 in an abnormal potential state.

Fig. 2B is a circuit operation diagram of Fig. 1 in a normal potential state.

Figure 3 is a detailed circuit diagram of the electrostatic protection circuit of the present invention.

Figure 4: Schematic diagram of the output stage circuit with both integrated circuits.

10‧‧‧Output buffer

11‧‧‧Abnormal potential detection unit

12‧‧‧ Gate potential switching unit

13‧‧‧Output buffer unit

21‧‧‧Internal circuits

22‧‧‧Output pad

Claims (10)

An output buffer capable of rapidly switching a gate potential, comprising: an abnormal potential detecting unit connected in series with a DC power source to detect a trigger signal when a DC power source potential is abnormal; a gate potential switching unit, a string Connected to the DC power source and connected to the abnormal potential detecting unit and triggered by the trigger signal to output a two-gate potential switching signal; and an output buffer unit serially connected to the DC power source and including a a first PMOS transistor component and a first NMOS transistor component, wherein the gates of the PMOS transistor component and the NMOS transistor component are respectively connected to a gate potential switching unit, and the gate potential switching unit determines the gate thereof Potential. The output buffer of claim 1, wherein the abnormal potential detecting unit comprises: a register diode, the cathode of which is connected to the high potential end of the DC power source, and the breakdown voltage of the arrester diode is greater than a normal operating potential of the DC power source; and a resistor connected in series between the anode of the Zener diode and the low potential end of the DC power source. The output buffer of claim 2, wherein the gate potential switching unit comprises: a second PMOS transistor element, the source of which is connected to the high potential end of the DC power source, and the drain is connected to the output a gate of the first PMOS transistor element of the buffer unit; and a second NMOS transistor element, the source of which is connected to the low potential end of the DC power supply, and the drain of which is connected to the first NMOS transistor of the output buffer unit a gate of the second NMOS transistor; the gate of the second NMOS transistor is coupled to the gate of the first PMOS transistor through an inverter, and is coupled to the gate of the abnormal potential detection unit A tandem node of resistors. The output buffer of any one of claims 1 to 3, wherein the drain-to-source of the first PMOS transistor of the output buffer unit is connected to a parasitic forward diode, the first NMOS transistor component The drain to the source are respectively connected to a parasitic reverse diode. The output FIFO of claim 4, wherein the second PMOS transistor component and the second NMOS transistor component of the gate potential switching unit are low voltage or high voltage semiconductor components. An electrostatic protection circuit includes: an abnormal potential detecting unit connected in series with a DC power source to detect a trigger signal when a DC power source potential is abnormal; a gate potential switching unit is serially connected to the DC power source and coupled Connected to the abnormal potential detecting unit and triggered by the trigger signal to output a two-gate potential switching signal; an output buffer unit is serially connected to the DC power supply and includes a first PMOS transistor component, a first NMOS transistor component and an output pad connected to the first PMOS transistor component and the first NMOS transistor component, wherein the gates of the PMOS transistor component and the NMOS transistor component are respectively switched to a gate potential a unit connection, the gate potential switching unit determines a gate potential thereof; and an electrostatic protection unit is connected to the output buffer unit to detect an abnormal potential generated by static electricity, and detects a pair of abnormal potentials a low-potential discharge path of the DC power source; wherein the ESD protection circuit detects that the abnormal potential system is higher than the abnormal potential detected by the abnormal potential detecting unit. The electrostatic protection circuit of claim 6, wherein the abnormal potential detecting unit comprises: a register diode, the cathode of which is connected to the high potential end of the DC power source, and the breakdown voltage of the Zener diode is greater than a normal operating potential of the DC power source; and a resistor connected in series between the anode of the Zener diode and the low potential end of the DC power source. The static electricity protection circuit of claim 7, wherein the gate potential switching unit comprises: a second PMOS transistor element, the source of which is connected to the high potential end of the DC power source, and the drain is connected to the output a gate of the first PMOS transistor element of the buffer unit; and a second NMOS transistor element, the source of which is connected to the low potential end of the DC power supply, and the drain of which is connected to the first NMOS transistor of the output buffer unit a gate of the second NMOS transistor; the gate of the second NMOS transistor is coupled to the gate of the first PMOS transistor through an inverter, and is coupled to the gate of the abnormal potential detection unit A tandem node of resistors. The electrostatic protection circuit according to any one of claims 6 to 8, wherein a drain-to-source diode of the first PMOS transistor of the output buffer unit is connected to a parasitic forward diode, the first NMOS transistor component The drain to the source are respectively connected to a parasitic reverse diode. The static protection circuit of claim 9, wherein the second PMOS transistor component and the second NMOS transistor component of the gate potential switching unit are low voltage or high voltage semiconductor components.