CN203054822U - Controllable watchdog circuit - Google Patents
Controllable watchdog circuit Download PDFInfo
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- CN203054822U CN203054822U CN 201320025347 CN201320025347U CN203054822U CN 203054822 U CN203054822 U CN 203054822U CN 201320025347 CN201320025347 CN 201320025347 CN 201320025347 U CN201320025347 U CN 201320025347U CN 203054822 U CN203054822 U CN 203054822U
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- watchdog
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Abstract
A controllable watchdog circuit comprises a watchdog chip, a trigger and a switch. The watchdog chip comprises a manual reset signal input end and a watchdog output end. The input end of the trigger is connected with a microcontroller, the output end of the trigger is connected with the switch, the switch is connected with the manual reset signal input end, and the watchdog output end is connected with the switch and the input end of the trigger respectively. According to the controllable watchdog circuit, the trigger caches a last enable signal, does not carry out signal replacement until next entering of a normal enable signal, the controllable watchdog circuit solves the problems that the state of the enable signal is uncertain when the microcontroller is abnormal, and achieves the operation of operating and stopping the watchdog chip at any time through the switch.
Description
Technical field
The utility model relates to electronic device field, particularly relates to the controllable watch dog circuit.
Background technology
Along with popularizing of development of science and technology and application of electronic technology, more and more electrical equipment, equipment use microcontroller.Because the work of microcontroller can be subjected to the interference of factors such as external electromagnetic field, causes program fleet, and system can't normally be moved.
Be to adopt a kind of circuit of house dog that cries that the running status of microcontroller is monitored in real time in the classic method, its principle of work is to link to each other with the feeding-dog signal of watchdog chip with a microcontrolled I/O, by this I/O pin of software control by in official hour, sending high level (or low level), in case microcontroller is because interference causes program fleet, the program of writing the house dog pin just is not performed, watchdog circuit is then exported reset signal, system is resetted, program brings into operation from initial address, has just realized automatically reseting of system.
This watchdog circuit does not have the control signal of enabling, and can not realize the effective control to watchdog circuit.The circuit increase of another kind of house dog enables control signal, if but after the microcontroller program exception, the state of enable signal is uncertain, makes watchdog circuit be in invalid state, causes system not restart.
The utility model content
Based on this, be necessary that the enable signal state is uncertain at after the microcontroller program exception, cause system can not restart problem, a kind of controllable watch dog circuit is provided.
A kind of controllable watch dog circuit, it is characterized in that, comprise: watchdog chip, trigger, switch, described watchdog chip comprises hand-reset signal input part, house dog output terminal, the input end of described trigger is connected with microcontroller, the output terminal of described trigger is connected with described switch, and described switch is connected with described hand-reset signal input part, and described house dog output terminal is connected with the input end of described switch and described trigger respectively.
Above-mentioned controllable watch dog circuit, the last enable signal of trigger buffer memory, enter up to normal enable signal next time and just to carry out the signal replacement, solving microcontroller is in when unusual, the uncertain problem of enable signal state has realized carrying out at any time, stopping at any time the running of watchdog chip by switch.
Among embodiment, described trigger is d type flip flop therein, and the input end of described d type flip flop is connected with clock signal terminal with the enable signal end of described microcontroller respectively.
Above-mentioned controllable watch dog circuit, the last enable signal of d type flip flop buffer memory, enter up to normal enable signal next time and just to carry out the signal replacement, solving microcontroller is in when unusual, the uncertain problem of enable signal state has realized carrying out at any time, stopping at any time the running of watchdog chip by switch.
Among embodiment, described trigger is latch therein, and the input end of described latch is connected with output enable control signal end with the enable signal end of described microcontroller respectively.
Above-mentioned controllable watch dog circuit, the last enable signal of latch buffer memory, enter up to normal enable signal next time and just to carry out the signal replacement, solving microcontroller is in when unusual, the uncertain problem of enable signal state has realized carrying out at any time, stopping at any time the running of watchdog chip by switch.
Among embodiment, also comprise described microcontroller therein, described microcontroller is by enable signal end output watchdog circuit invalid signals.
Above-mentioned controllable watch dog circuit is realized control to control signal by second switch, just powers on or dormant state or when having mass data to handle when system is in, and can close watchdog circuit.
Among embodiment, described trigger is connected with described switch by delayer therein.
Above-mentioned controllable watch dog circuit by the delay of delayer to control signal, makes hand-reset signal input part normal response.
Description of drawings
Fig. 1 is the structural representation of the utility model controllable watch dog circuit;
Fig. 2 is the structural representation of the utility model controllable watch dog circuit embodiments one;
Fig. 3 is the realization circuit diagram of the utility model controllable watch dog circuit;
Fig. 4 is the structural representation of the utility model controllable watch dog circuit embodiments two.
Embodiment
Based on this, be necessary that at problem propose a kind of controllable watch dog circuit, after the microcontroller program exception, resolution system can not restart problem, no matter whether by external interference or operate as normal, open at any time in the time of can need accomplishing, close at any time.
In order to achieve the above object, the utility model is by the following technical solutions:
Referring to Fig. 1, structural representation for the utility model controllable watch dog circuit, comprise: watchdog chip 11, be used for trigger 12, the switch (S) 13 of the enable signal that the buffer memory microcontroller sends, watchdog chip comprises hand-reset signal input part MR(Manual Reset), house dog output terminal WDO(Watchdog Onput, WDO), the input end of trigger is connected with microcontroller, the output terminal of trigger is connected with switch, switch is connected with the hand-reset signal input part, and the house dog output terminal is connected with the input end of switch and trigger respectively.Wherein, the conducting of the output terminal gauge tap of trigger with close and then the RESET input conducting of control hand-reset signal and watchdog chip.In one embodiment, in order to guarantee hand-reset signal input part normal response, can also be provided with delayer between trigger 12 and the switch 13.
In an embodiment, referring to Fig. 2, be the structural representation of the utility model controllable watch dog circuit embodiments one.Trigger is d type flip flop 22, and the input end of d type flip flop 22 is connected with clock signal terminal CLK with the enable signal end EN of microcontroller 25 respectively.Be provided with delayer 24 between d type flip flop 22 and the switch 13, the house dog input end WDI(Watchdog Input of micro controller I/O pin and watchdog chip WDI) connects.
When needs open or close watchdog circuit, the EN end output enable signal of microcontroller 25, the CLK end clock signal of microcontroller 25, by the rising edge clock signal state of enable signal is input to d type flip flop, the instruction that the d type flip flop gauge tap is opened or closed, and the state of this enable signal remained in the d type flip flop, up to receiving next normal enable signal.When if next enable signal is abnormal signal, the on off state of d type flip flop control is being kept current situation and is not being made change, has guaranteed that then watchdog chip still can operate as normal.The conducting of the output terminal gauge tap of described trigger with close and then the reset output terminal conducting of control hand-reset signal and watchdog chip.When microcontroller 25 because various factors when unusual, can not be exported normal feeding-dog signal.At this moment, the WDO of watchdog chip end output WDO signal, when switch when opening, this signal is held by MR, is input to watchdog chip, and system is resetted.Simultaneously, this WDO signal enters d type flip flop, removes the state of the current control signal of d type flip flop preservation, makes d type flip flop revert to original state, even switch is closed condition.D type flip flop sends out code to delayer, carries out the regular hour delay.At least be set at the time that house dog output WDO signal can be input to the hand-reset input end MR of house dog time delay, after watchdog chip produces reset signal, out code be sent to switch, switch cuts out, forbid watchdog circuit.
Also comprise described microcontroller 25, described microcontroller is by enable signal end output watchdog circuit invalid signals.When system has just powered on or has been in dormant state, close watchdog circuit, after system powers on stable or wakes up from dormant state, open watchdog circuit again.When lot of data need be handled, microcontroller 25 also can cut out watchdog circuit by the watchdog circuit invalid signals.
In a physical circuit, referring to shown in Figure 3, be the realization circuit diagram of the utility model controllable watch dog circuit.Wherein, U1 is microcontroller, adopts the microcontroller of AT91SAM9G45-CU model in the present embodiment.U2, R1, R2, R3, R4, D1, C6 constitute d type flip flop circuit of the present utility model, and present embodiment adopts the U2 of 74LVC74AD type.U4C, R13, R15 constitute switch S of the present utility model, and R8, C5 constitute delayer of the present utility model, and U3 and D2, R6, C4, C1, C2, C3, U4D constitute watchdog chip and the peripheral circuit of this programme; System is by the control system.
In an embodiment, referring to Fig. 4, be the structural representation of utility model controllable watch dog circuit embodiments two.Watchdog chip 11, be used for latch 32, the switch (S) 33 of the enable signal that the buffer memory microcontroller sends, watchdog chip comprises hand-reset signal input part MR, house dog output terminal WDO, and the input end of latch is connected with output enable control signal end OE with the enable signal end EN of microcontroller respectively.The output terminal of latch is connected with switch, switch is connected with delayer, and delayer is connected with the hand-reset signal input part, and the house dog output terminal is connected with the input end of switch and latch respectively.Concrete enforcement is similar with embodiment one, does not repeat them here.Trigger can also be for rest-set flip-flop etc., and is concrete and embodiment is similar, do not repeat them here.
The above embodiment has only expressed several embodiment of the present utility model, and it describes comparatively concrete and detailed, but can not therefore be interpreted as the restriction to the utility model claim.Should be pointed out that for the person of ordinary skill of the art under the prerequisite that does not break away from the utility model design, can also make some distortion and improvement, these all belong to protection domain of the present utility model.Therefore, the protection domain of the utility model patent should be as the criterion with claims.
Claims (6)
1. controllable watch dog circuit, it is characterized in that, comprise: watchdog chip, trigger, switch, described watchdog chip comprises hand-reset signal input part, house dog output terminal, the input end of described trigger is connected with microcontroller, the output terminal of described trigger is connected with described switch, and described switch is connected with described hand-reset signal input part, and described house dog output terminal is connected with the input end of described switch and described trigger respectively.
2. controllable watch dog circuit according to claim 1 is characterized in that, described trigger is d type flip flop, and the input end of described d type flip flop is connected with clock signal terminal with the enable signal end of described microcontroller respectively.
3. controllable watch dog circuit according to claim 1 is characterized in that, described trigger is latch, and the input end of described latch is connected with output enable control signal end with the enable signal end of described microcontroller respectively.
4. controllable watch dog circuit according to claim 2 is characterized in that, also comprises described microcontroller, and described microcontroller is by enable signal end output watchdog circuit invalid signals.
5. controllable watch dog circuit according to claim 3 is characterized in that, also comprises described microcontroller, and described microcontroller is by enable signal end output watchdog circuit invalid signals.
6. according to any described controllable watch dog circuit of claim 1 to 5, it is characterized in that described trigger is connected with described switch by delayer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320025347 CN203054822U (en) | 2013-01-17 | 2013-01-17 | Controllable watchdog circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320025347 CN203054822U (en) | 2013-01-17 | 2013-01-17 | Controllable watchdog circuit |
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| Publication Number | Publication Date |
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| CN203054822U true CN203054822U (en) | 2013-07-10 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 201320025347 Expired - Fee Related CN203054822U (en) | 2013-01-17 | 2013-01-17 | Controllable watchdog circuit |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105676981A (en) * | 2014-11-19 | 2016-06-15 | 湖南南车时代电动汽车股份有限公司 | Reset circuit, working method and reset method |
| CN105897618A (en) * | 2016-04-01 | 2016-08-24 | 上海斐讯数据通信技术有限公司 | Reset circuit device of switch |
| CN106776101A (en) * | 2017-02-28 | 2017-05-31 | 四川九洲电器集团有限责任公司 | A kind of watchdog circuit and signal processing circuit |
| CN110750374A (en) * | 2018-07-23 | 2020-02-04 | 迈普通信技术股份有限公司 | Watchdog circuit and control method thereof |
| CN110794942A (en) * | 2018-08-03 | 2020-02-14 | 圣邦微电子（北京）股份有限公司 | Reset chip circuit |
-
2013
- 2013-01-17 CN CN 201320025347 patent/CN203054822U/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105676981A (en) * | 2014-11-19 | 2016-06-15 | 湖南南车时代电动汽车股份有限公司 | Reset circuit, working method and reset method |
| CN105897618A (en) * | 2016-04-01 | 2016-08-24 | 上海斐讯数据通信技术有限公司 | Reset circuit device of switch |
| CN106776101A (en) * | 2017-02-28 | 2017-05-31 | 四川九洲电器集团有限责任公司 | A kind of watchdog circuit and signal processing circuit |
| CN106776101B (en) * | 2017-02-28 | 2023-07-21 | 四川九洲电器集团有限责任公司 | Watchdog circuit and signal processing circuit |
| CN110750374A (en) * | 2018-07-23 | 2020-02-04 | 迈普通信技术股份有限公司 | Watchdog circuit and control method thereof |
| CN110794942A (en) * | 2018-08-03 | 2020-02-14 | 圣邦微电子（北京）股份有限公司 | Reset chip circuit |
| CN110794942B (en) * | 2018-08-03 | 2021-07-09 | 圣邦微电子（北京）股份有限公司 | Reset chip circuit |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130710 Termination date: 20200117 |
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| CF01 | Termination of patent right due to non-payment of annual fee |