CN102323914A - Controller interface capable of automatically detecting WGIN input and control method - Google Patents

Abstract

The invention relates to a controller interface capable of automatically detecting WGIN input and a control method. A WGIN module is attached to a bus bridge and is in signal connection with a kernel CPU (Central Processing Unit) through the bus bridge, the kernel CPU transfers a clock module to the WGIN module through the bus bridge, and a reference clock which can be supplied to the WGIN for work is formed through a WGIN prescaler in a frequency division way; two external GPIO (General Purpose Input/Output) ports are used for carrying out data sampling by a sampling clock, acquiring data with the length consistent with preset data length and storing the data in a register WGINH_RESULT and a register WGINL_RESULT, an interrupt is generated at the time, and whether the interrupt is delivered to the kernel CPU is judged under the control of interrupt enable. The controller interface and the control method disclosed by the invention have the beneficial effects that: a WGIN level signal is automatically received by the hardware without the need of polling the level states of the GPIO ports by a main program, therefore the phenomenon of data loss can be avoided, and the defects in an inquiring manner are overcome; and according to the configuration of users, the hardware can be subjected to once interrupt after receiving all data, therefore the progress cannot be influenced by frequency interrupt, and the defects of an interrupt manner are overcome.

Description

A kind of control unit interface and control method of automatic detection Wei root input

Technical field

The present invention relates to access control system, especially a kind of control unit interface and control method of automatic detection Wei root input.

Background technology

The Wiegand agreement is unified in the world standard, is a kind of communications protocol of being formulated by Motorola Inc..It is applicable to the card reader that relates to access control system and the numerous characteristics of card.It has a lot of forms, and the 26-bit of standard should be the most frequently used form.In addition, also have forms such as 34-bit, 37-bit.And standard 26-bit form is a widely used industrial standard, and open to the user of all HID (Human Interface Device human interface device).Nearly all access control system is all accepted the 26-Bit form of standard.

The output of Wei single data is made up of two lines, is respectively DATA0 and DATA1; Two lines respectively will ' 0 ' or ' 1 ' output.When exporting ' 0 ': appearance of negative pulse on the DATA0 line; When exporting ' 1 ': appearance of negative pulse on the DATA1 line; A burst length TL is between 20us to 100us, and the bound-time TW of pulse is between 200us to 20ms, and is as shown in Figure 2.

Existing Wei root signal reception mode has two kinds: inquiry mode and external interrupt mode.All exist drawback separately.1, the reception of Wei root requires than higher the real-time of time; If the phenomenon of frame losing can occur with the method reception of inquiry: supposing to inquire DATA0 is that 0 o'clock master routine is pointing to other tasks; DATA0 has become 1 when executing this task Deng master routine; Just caused losing of a 0bit so like this, the card number of reading like this parity checking certainly can't pass, and therefore shows CPU and does not receive the card number that the ID module is sent.Though 2, the phenomenon of data can not appear losing in the mode of employing external interrupt, interruption times is too frequent, and for example Wei root 26 will interrupt 26 times, and Wei root 34 will interrupt 34 times, and this can cause user's process often to be interrupted, and influences the continuity of program process.

Summary of the invention

The object of the invention will solve the deficiency that above-mentioned technology exists just, and a kind of control unit interface and control method of automatic detection Wei root input are provided.

The present invention solves the technical scheme that its technical matters adopts: the control unit interface of this automatic detection Wei root input; The Wei root module is articulated on the bus bridge; Be connected with the kernel cpu signal through bus bridge; Kernel CPU transmits a clock module through bus bridge and gives the Wei root module, and occuring frequently through WGIN pre-divider branch to supply the reference clock of Wei root module work; Be used to receive two external GPIO mouths of external signal; Be WGIN_DATA0, WGIN_DATA1, carry out data sampling, collect the data consistent with preset data length through sampling clock; It is the WGIN data length; It is stored among register WGINH_RESULT and the WGINL_RESULT, produces an interruption this moment, this interrupts whether passing to kernel CPU by interrupting enabling control.

Control method of the present invention, it is following that the client receives the Wiegand signal step through control unit interface:

Step 1: Wei root (WGIN) initialization:

1. dispose the work clock of WGIN, write register WGIN_CLKDIV;

2. Data Receiving length is set, writes register WGIN_CTRL [7:1];

3. remove WGIN interrupt inquiry sign, write register WGIN_INTFLAG=1;

4. if configuration WGIN interrupts enabling, write register WGIN_CTRL [0]=1, if interruption does not enable then writes 0;

Step 2: Wei root (WGIN) receives break in service:

1., produce among the WGIN and have no progeny, remove the WGIN interrupt identification, prepare next WGIN and interrupt, write register WGIN-INTFLAG=1;

2., read WGIN result register WGINH_RESULT, WGINL_RESULT; Depositing in this register from read head and passing the complete Wiegand signal of coming.

The effect that the present invention is useful is: the characteristic that the present invention is directed to Wei root acknowledge(ment) signal has well solved above two drawbacks: hardware automatic reception Wei root level signal of the present invention; No longer need master routine to remove the level state of poll GPIO mouth; Thereby the phenomenon of data can not occur losing, solve the drawback of inquiry mode.Right hardware only produces once after having accepted all data and interrupts, thereby can not interrupt frequently influencing the course according to user's configuration, has solved the drawback that adopts interrupt mode.

Description of drawings

Fig. 1 is the data transmission synoptic diagram of gate inhibition and read head;

Fig. 2 is the WGIN sequential chart;

Fig. 3 receives the semiotic function block diagram for Wei root among the present invention;

Fig. 4 is the synoptic diagram that articulates of WGIN module among the present invention;

Fig. 5 is WGIN initialization flowchart among the present invention;

Fig. 6 receives the interrupt service subroutine synoptic diagram for WGIN among the present invention.

Embodiment

Below in conjunction with accompanying drawing and embodiment the present invention is described further:

Please join shown in Figure 4ly, the Wei root module is articulated on the bus bridge, thereby carries out the signal transmission with kernel CPU.Kernel CPU transmits a clock module and gives the Wei root module through bus bridge, divides to occur frequently through Wei root frequency divider (WGIN pre-divider) to supply the reference clock of Wei root module work.Two external GPIO mouth (WGIN_DATA0; WGIN_DATA1) receive external signal; Carry out data sampling through sampling clock, collect the data consistent (WGIN data length), it is stored among register WGINH_RESULT (high 32 bit registers of WGIN result) and the WGINL_RESULT (WGIN result hangs down 32 bit registers) with preset data length; Produce an interruption this moment, this interrupts whether passing to kernel CPU by interrupting enabling control.

The user can realize the reception of Wiegand signal through some simple registers of configuration.Register description is following:

Table 1 has been listed these register names, offset address, access mode and initial value etc.

Table 1WGIN register

Register name	Offset address	R/W	Reset values	Describe
					WGIN_CLKDIV	0x00	r/w	0x0a	Clock sampling frequency division register
WGIN_CTRL	0X04	r/w	0x00	Control register
					WGIN_INTFLAG	0x08	r/w	0x00	Interrupt identification/zero clearing register
WGINH_RESULT	0x0c	r/w	0x00	The high bit register of transformation result
					WGINL_RESULT	0x10	r/w	0x00	Transformation result is hanged down bit register

WGIN clock sampling frequency division register (WGIN_CLKDIV):

WGIN clock sampling frequency division register (WGIN_CLKDIV) is confirmed SF, and table 2 is seen in its definition.

Table 2WGIN_CLKDIV

Domain name	The position	R/W	Reset values	Describe
					--	31:16	--	--	Keep
ClkDiv	15:0	r/w	0x0a	WGIN clock division number, divider ratio are (WGINClkDiv+1) * 2

WGIN control register (WGIN_CTRL):

WGIN_CTRL is used for disposing the control signal of WGIN, describes and sees table 3.

Table 3WGIN_RSTDT

Domain name	The position	R/W	Reset values	Describe
					--	31:9	--	--	Keep
Start	8	r/w	0x00	Write 1 and start the reception data,
					Len	7:1	r/w	0x00	Receive the data total length
IntEn	0	r/w	0x00	Interrupt enable bit is write 1 and is enabled to interrupt

WGIN_INTFLAG sees table 4, is used for reading the interrupt identification of WGIN, and removes WGIN interrupt identification, this register write 1 zero clearing.

Table 4WGIN_INTFLAG

Domain name	The position	R/W	Reset values	Describe
					--	31:1	--	--	Keep
IntFlag	0	r/w	0x00	Wiegand interrupt identification/zero clearing register

WGIN transformation result register high 32 (WGINH_RESULT)

WGINH_RESULT sees table 5, is WGIN transformation result register.In case the user detects or inquires interruption, the user just can read the transformation result (high 32) that this register obtains Wiegand.

Table 5WGIN_RESULT

Name	Bits	R/W	Reset	Description
					--	31:10	--	--	Reserved
ResultH	9:0	r	0x00	WGIN?conversion?result

WGIN transformation result register hangs down 32 (WGINL_RESULT)

WGINH_RESULT sees table 6, if data length surpasses 32, remaining result exists in this register, is WGIN transformation result register.In case the user detects or inquire interruption, the user just can read the transformation result (low 32) that this register obtains Wiegand.

Table 6WGIN_RESULT

Name	Bits	R/W	Reset	Description
					--	31:10	--	--	Reserved
ResultL	9:0	r	0x00	WGIN?conversion?result

Like Fig. 5, shown in Figure 6, it is following that the client receives the Wiegand signal step through this interface:

Step 1: Wei root (WGIN) initialization:

1. dispose the work clock of WGIN, write register WGIN_CLKDIV

2. Data Receiving length is set, writes register WGIN_CTRL [7:1]

3. remove WGIN interrupt inquiry sign, write register WGIN_INTFLAG=1

4. if configuration WGIN interrupts enabling, write register WGIN_CTRL [0]=1, if interruption does not enable then writes 0

Step 2: Wei root (WGIN) receives break in service

1., produce among the WGIN and have no progeny, remove the WGIN interrupt identification, prepare next WGIN and interrupt, write register WGIN-INTFLAG=1;

2., read WGIN result register WGINH_RESULT, WGINL_RESULT; Depositing in this register from read head and passing the complete Wiegand signal of coming.

Characteristics of the present invention are following:

1. the input of Wei root can be passed through register configuration, to save the MEMORY space, reduces system resource;

2. hardware mode guarantees to receive the accuracy of data;

3. greatly reduce interruption frequency, liberated MCU (Micro Control Unit micro-control unit resource) resource;

4.IP logic is simple, area is less, and cost is lower;

5. can pass through IP, compatible existing existing multiple Wei root input mode.

Terminological interpretation:

Gate control system:

Weigh up again into management control system (ACCESS CONTROL SYSTEM).It is a kind of intellectualized management system of managerial personnel's turnover.Summarize and be exactly: whom is managed when can pass in and out those doors; And inquiry form afterwards or the like is provided; Common gate control system has: password gate control system, non-contact card gate control system, the general name of fingerprint iris palm type bio-identification gate control system etc.; Gate control system developed very fast in recent years, was widely used in the management control system.

Read head:

Read head is exactly a card reader, and (read goes out device, scanner, reader, communicator, read write line again) is the module for reading and writing in the control system.The read head Chip Packaging is got up, mainly communicate through modes such as Wei Gen or serial ports, IIC and controller, this has just formed simple control system.At present the kind of read head is a lot, mainly comprises three kinds of keyboard-type, induction type and bio-identification.

Door controller:

Door controller is the unidirectional turnover of door or the two-way turnover of door, according to high-performance gate inhibition's controller of technical grade technical requirement design.

MCU：

MCU (Micro Control Unit) Chinese is a micro-control unit; Claim one chip microcomputer (Single Chip Microcomputer) or single-chip microcomputer again; Be meant appearance and development thereof along with large scale integrated circuit; CPU, RAM, ROM, timer conter and the multiple I/O interface of computing machine are integrated on a slice chip, form the computing machine of chip-scale, for doing various combination control in different application scenarios.

The GPIO mouth:

This paper refers to the pin of MCU.

The external interrupt mode:

External interrupt mode among this paper is meant that the GPIO mouth of the MCU in the door controller receives the terminal that level signal produced of sending from read head, and the MCU of controller reads the level of this interruption then.

The external inquiry mode:

External inquiry mode among this paper is meant that the continuous poll of MCU in the door controller self is connected to the GPIO mouth signal of read head, and is as shown in Figure 1.

Except that the foregoing description, the present invention can also have other embodiments.All employings are equal to the technical scheme of replacement or equivalent transformation formation, all drop on the protection domain of requirement of the present invention.

Claims (2)

1. one kind is detected the control unit interface that the Wei root is imported automatically; It is characterized in that: the Wei root module is articulated on the bus bridge; Be connected with the kernel cpu signal through bus bridge; Kernel CPU transmits a clock module through bus bridge and gives the Wei root module, and occuring frequently through WGIN pre-divider branch to supply the reference clock of Wei root module work; Be used to receive two external GPIO mouths of external signal; Be WGIN_DATA0, WGIN_DATA1, carry out data sampling, collect the data consistent with preset data length through sampling clock; It is the WGIN data length; It is stored among register WGINH_RESULT and the WGINL_RESULT, produces an interruption this moment, this interrupts whether passing to kernel CPU by interrupting enabling control.

2. control method that adopts the control unit interface of automatic detection Wei root input as claimed in claim 1, it is characterized in that: it is following that the client receives the Wiegand signal step through control unit interface:

Step 1: Wei root (WGIN) initialization:

1. dispose the work clock of WGIN, write register WGIN_CLKDIV;

2. Data Receiving length is set, writes register WGIN_CTRL [7:1];

3. remove WGIN interrupt inquiry sign, write register WGIN_INTFLAG=1;

4. if configuration WGIN interrupts enabling, write register WGIN_CTRL [0]=1, if interruption does not enable then writes 0;

Step 2: Wei root (WGIN) receives break in service:

1., produce among the WGIN and have no progeny, remove the WGIN interrupt identification, prepare next WGIN and interrupt, write register WGIN-INTFLAG=1;

2., read WGIN result register WGINH_RESULT, WGINL_RESULT; Depositing in this register from read head and passing the complete Wiegand signal of coming.

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