CN109992959A - Direct fault location resists method and device, chip and computer readable storage medium - Google Patents
Direct fault location resists method and device, chip and computer readable storage medium Download PDFInfo
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- CN109992959A CN109992959A CN201810049993.XA CN201810049993A CN109992959A CN 109992959 A CN109992959 A CN 109992959A CN 201810049993 A CN201810049993 A CN 201810049993A CN 109992959 A CN109992959 A CN 109992959A
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- 238000000034 method Methods 0.000 title claims abstract description 33
- 238000001514 detection method Methods 0.000 claims abstract description 41
- 230000002159 abnormal effect Effects 0.000 claims abstract description 38
- 230000001960 triggered effect Effects 0.000 claims abstract description 6
- 238000012545 processing Methods 0.000 claims description 4
- 238000007689 inspection Methods 0.000 claims 3
- 238000002347 injection Methods 0.000 abstract description 15
- 239000007924 injection Substances 0.000 abstract description 15
- 230000000694 effects Effects 0.000 abstract description 7
- 230000007123 defense Effects 0.000 abstract description 5
- 238000012360 testing method Methods 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 5
- 230000006870 function Effects 0.000 description 5
- 230000008901 benefit Effects 0.000 description 3
- 238000004891 communication Methods 0.000 description 3
- 108010001267 Protein Subunits Proteins 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000008358 core component Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
- G06F21/55—Detecting local intrusion or implementing counter-measures
- G06F21/554—Detecting local intrusion or implementing counter-measures involving event detection and direct action
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
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- Theoretical Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Software Systems (AREA)
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- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
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Abstract
The present invention provides a kind of direct fault locations to resist method and device, chip and computer readable storage medium; the abnormal signal that this method passes through the power port of detection module to be protected; when detecting abnormal signal; send alarm signal; when being triggered by alarm signal; instruction is resisted according to security strategy generation, execution is resisted instruction progress direct fault location and resisted；The detection of the abnormal signal to the local function module of chip is realized, and carries out direct fault location according to testing result and resists, solves the problems, such as that existing direct fault location defense technique is bad for local fault injection protection effect.
Description
Technical field
The present invention relates to chip secure fields more particularly to a kind of direct fault location to resist method and device, chip and calculating
Machine readable storage medium storing program for executing.
Background technique
Direct fault location analysis is interfered by certain means it in chip operational process, occurs it pre-
Phase perhaps unexpected operating status according to introduce mistake after chip working condition or output as a result, obtain analysis object
Effective information or sensitive data.
Electromagnetism direct fault location due to not having to destroy chip surface, and is attacked only as a kind of novel direct fault location mode
For topically effective, controllability is strong, so electromagnetism fault injection attacks have great advantage in Accurate Analysis, by more next
The concern of more same industries.
In SOC (System on Chip, system level chip), (Flash EEPROM Memory stores core to FLASH
Piece) it is mainly used for program storage, FLASH controller is always the emphasis of direct fault location；When FLASH controller breaks down
When, write-in data are read it is possible that various exceptions, lead to sequential operation and corrupt data, to chip secure operation generation
Greatly harm.
The defence method of existing hardware fault injection considers global voltage glitch and clock bur attack mostly, and
For local electromagnetism direct fault location, protection effect is bad.
Summary of the invention
The present invention provides a kind of direct fault location and resists method and device, chip and computer readable storage medium, to solve
The existing direct fault location defense technique problem bad for local fault injection protection effect.
In order to solve the above technical problems, the invention adopts the following technical scheme:
A kind of direct fault location resists method, be used for include multiple functional modules chip, direct fault location resists method packet
It includes:
Detect the abnormal signal of the power port of module to be protected；
When detecting abnormal signal, alarm signal is sent；
When being triggered by alarm signal, instruction is resisted according to security strategy generation；
Execution is resisted instruction progress direct fault location and is resisted.
Further, the abnormal signal for detecting the power port of module to be protected includes:
The voltage glitch of power port is detected, and when detecting voltage glitch, judgement detects abnormal signal；
And/or the clock bur of power port being detected, and when detecting clock bur, judgement detects abnormal signal.
Further, it executes to resist instruction progress direct fault location and resist and includes:
Module to be protected is resetted according to instruction is resisted；
And/or module to be protected is removed according to instruction is resisted.
A kind of direct fault location resists device, be used for include processor and multiple functional modules chip, direct fault location supports
Imperial device includes:
Detection unit is connect with the power port of module to be protected in chip, for detecting abnormal signal, and is being detected
When abnormal signal, alarm signal is sent to processor；
Resist unit, for receive processor according to security strategy by alarm signal trigger it is generated resist instruction,
And it executes to resist and progress direct fault location is instructed to resist.
Further, detection unit includes voltage glitch detection unit, and voltage glitch detection unit is for detecting power end
The voltage glitch of mouth, and when detecting voltage glitch, judgement detects abnormal signal, sends alarm signal to processor.
Further, detection unit includes clock bur detection unit, and voltage glitch detection unit is for detecting power end
The clock bur of mouth, and when detecting clock bur, judgement detects abnormal signal, sends alarm signal to processor.
Further, chip includes processor, storage chip and storage control, and storage control includes multiple function moulds
Block, detection unit include multiple detection sub-units, and detection sub-unit is arranged in each functional module of storage control, and with it is right
The power port of functional module is answered to connect.
Further, resist unit for according to resist instruction reset storage control and/or removing storage chip.
A kind of chip comprising processor, multiple functional modules and direct fault location provided by the invention resist device.
A kind of computer readable storage medium, computer-readable recording medium storage have one or more program, and one
Or multiple programs can be executed by one or more processor, to realize that direct fault location provided by the invention resists the step of method
Suddenly.
Beneficial effect
The present invention provides a kind of direct fault locations to resist method and device, chip and computer readable storage medium, the party
Method sends alarm signal, in quilt when detecting abnormal signal by detecting the abnormal signal of the power port of module to be protected
When alarm signal triggers, instruction is resisted according to security strategy generation, execution is resisted instruction progress direct fault location and resisted；It realizes pair
The detection of the abnormal signal of the local function module of chip, and carry out direct fault location according to testing result and resist, it solves existing
The direct fault location defense technique problem bad for local fault injection protection effect.
Detailed description of the invention
Fig. 1 is the flow chart that the direct fault location that the embodiment of the present invention one provides resists method；
Fig. 2 is the structural schematic diagram that the direct fault location that the embodiment of the present invention one provides resists device；
Fig. 3 is the structural schematic diagram for the chip that the embodiment of the present invention one provides；
Fig. 4 is the structural schematic diagram of chip provided by Embodiment 2 of the present invention.
Specific embodiment
Below by specific embodiment combination attached drawing, invention is further described in detail.
Embodiment one:
Fig. 1 is the flow chart that the direct fault location that the embodiment of the present invention one provides resists method, referring to FIG. 1, the present embodiment
The direct fault location of offer resist method the following steps are included:
S101: the abnormal signal of the power port of module to be protected is detected.
According to the different modes of direct fault location, such as voltage glitch injection, clock bur injection, this step includes different
Implementation:
The voltage glitch of power port is detected, and when detecting voltage glitch, judgement detects abnormal signal；And/or
The clock bur of power port is detected, and when detecting clock bur, judgement detects abnormal signal.
S102: when detecting abnormal signal, alarm signal is sent.
The implementation of alarm signal can be interrupt signal, be also possible to low level signal or high level signal.
S103: when being triggered by alarm signal, instruction is resisted according to security strategy generation.
Security strategy can need to be arranged according to user, such as only reset storage chip controller can be set in user, also
The content for only removing storage chip can be set, or may be set to be while resetting storage chip controller, remove
Content of storage chip etc..These strategies all do not play the purpose for resisting direct fault location.
S104: execution is resisted instruction progress direct fault location and is resisted.
This step includes: that basis resists instruction reset module to be protected；And/or mould to be protected is removed according to instruction is resisted
Block, in this way when reset module to be protected, after resetting storage chip controller, shadow of the direct fault location to storage chip controller
Sound will disappear, and solve this direct fault location, when removing module to be protected, after resetting storage chip, in storage chip
Data be just emptied, direct fault location cannot obtain the data such as the program in storage chip.
Fig. 2 is the structural schematic diagram that the direct fault location that the embodiment of the present invention one provides resists device, referring to FIG. 2, this reality
The direct fault location for applying example offer is resisted device 2 and is comprised the following modules:
Detection unit 21 is connect with the power port of module to be protected in chip, for detecting abnormal signal, and is being detected
When to abnormal signal, alarm signal is sent to processor；
Unit 22 is resisted, finger generated is resisted being triggered by alarm signal according to security strategy for receiving processor
It enables, and executes to resist and progress direct fault location is instructed to resist.
In some embodiments, detection unit 21 includes voltage glitch detection unit, and voltage glitch detection unit is for examining
The voltage glitch of power port is surveyed, and when detecting voltage glitch, judgement detects abnormal signal, sends and alarms to processor
Signal.
In some embodiments, detection unit 21 includes clock bur detection unit, and voltage glitch detection unit is for examining
The clock bur of power port is surveyed, and when detecting clock bur, judgement detects abnormal signal, sends and alarms to processor
Signal.
In some embodiments, chip includes processor, storage chip and storage control, and storage control includes multiple
Functional module, detection unit 21 include multiple detection sub-units, and each functional module of storage control is arranged in detection sub-unit
In, and connect with the power port of corresponding function module.
In some embodiments, resist unit 22 for according to resist instruction reset storage control and/or remove store
Chip.
Fig. 3 is the structural schematic diagram for the chip that the embodiment of the present invention one provides, referring to FIG. 3, core provided in this embodiment
Piece includes: that processor 31, storage chip 32, communication bus 33, multiple functional modules 34 and direct fault location resist device 2,
In,
Communication bus 33 resists dress for realizing processor 31, storage chip 32, multiple functional modules 34 and direct fault location
Set the connection communication between 2；
Direct fault location resists the step of method that device 2 provides for realizing any of the above embodiment.
It present embodiments provides a kind of direct fault location and resists method and device, chip, this method is by detecting mould to be protected
The abnormal signal of the power port of block sends alarm signal, when being triggered by alarm signal, root when detecting abnormal signal
Instruction is resisted according to security strategy generation, execution is resisted instruction progress direct fault location and resisted；Realize the local function mould to chip
The detection of the abnormal signal of block, and carry out direct fault location according to testing result and resist, solve existing direct fault location defense technique
For the bad problem of local fault injection protection effect.
Embodiment two:
The present embodiment is illustrated so that chip is SOC as an example.
In SOC, FLASH is mainly used for program storage, and the controller IP of FLASH is always the emphasis of direct fault location,
When FLASH controller breaks down, write-in data are read it is possible that various exceptions, cause sequential operation and data to go out
Mistake generates greatly harm to chip secure operation.The present embodiment proposes a kind of high safety of anti-electromagnetism direct fault location analysis
Property SOC FLASH controller, the analysis of local electromagnetism direct fault location, and cost performance with higher can be resisted.
For current FLASH controller IP the case where being very easy to by electromagnetism fault injection attacks, the present embodiment exists
In the case that circuit basic structure is constant, according to electric power network feature, part electricity is added in each sub-function module power port
Dabbing pierces unit, forms voltage glitch and detects network, which effectively detects the office generated when electromagnetism fault injection attacks
Portion's electric voltage exception significantly improves the ability that FLASH controller resists the analysis of electromagnetism direct fault location.
Specifically, the variation of FLASH controller circuit structure mechanism less under the premise of, the characteristics of according to electric power network,
Since each submodule has power end, voltage glitch detection unit is added in the power end of each submodule, forms a voltage
Burr detects network, covers entire control circuit.When a certain submodule of control circuit is by electromagnetism fault injection attacks,
The voltage glitch detection unit of port can detect the burr of generation in time, and export alarm condition position to CPU (processor).
After CPU receives alarm condition position, according to user configuration situation, the safety such as instruction execution reset or removing FLASH content is issued
Operation, so that it is guaranteed that chip secure.
As shown in figure 4, the high security SOC FLASH controller 4 of anti-electromagnetism direct fault location analysis provided in this embodiment
It mainly include that interface module 41, main control module 42 and voltage glitch detect network.
Interface module 41 is made of 412 two submodules of bit width conversion logic sub-modules 411 and control logic submodule, is born
Duty handles the signal that other equipment in bus issue and control signal, is converted into format that main control module can identify simultaneously
It is sent to main control module, while the data-signal conveyed to main control module 42 is handled, and is converted thereof into and bus standard phase
Other main equipments being sent to after the form met in system.FLASH controller 4 is the slave equipment based on AHB (high-speed bus)
Module, interface module 41 facilitate the other equipment in bus and access to FLASH controller 4.
Main control module 42 is the processing core of FLASH controller 4, and FLASH controller 4 is all logical to the various operations of FLASH
Cross the realization of main control module 42.Main control module includes data buffer submodule 421, register file submodule 422 and control logic
423 3 submodules of submodule, wherein data buffer submodule 421 is used to cache control logic and bit width conversion logic generates
Data, register file submodule 422 between interface module 41 and main control module 42 address command configuration signal transition,
Signals, the control logic submodules 423 such as deposit address, order and configuration are read out out to data in each register,
To generate output to the control signal of FLASH；Main control module 42 realizes in bus other main equipments and accesses behaviour to FLASH
Make.
Voltage glitch detection network is made of the burr detection unit 43i (431-435) of each submodule, is to resist electromagnetism
The core component of direct fault location, voltage glitch detect network and rely on electric power network, add at the power port of each submodule
Burr detection unit is added, has formed a reticular structure, cover entire control circuit, when a certain submodule of FLASH control circuit
When block is by electromagnetism fault injection attacks, the voltage glitch detection unit of submodule can detect the burr of generation in time, and
Alarm signal is passed to CPU by bus, CPU according to user configuration situation, to secure processing module (i.e. above resist list
Member) it issues and executes instruction, FLASH control circuit is executed by secure processing module and the operation such as resets or remove FLASH, thus really
Protect chip secure.
The advantage that chip provided in this embodiment at least exists:
High security covers whole since the voltage glitch detection unit of each submodule has formed voltage glitch detection network
A FLASH controller can be detected when a submodule any one in electromagnetism fault injection attacks FLASH controller, be sent out in time
Alarm signal out, effect is obvious and susceptibility is high, can greatly promote the energy that FLASH controller resists electromagnetism fault injection attacks
Power.
High performance-price ratio, due to the present embodiment the variation of circuit basic structure less in the case where, according to electric power network feature,
Local voltage burr unit is added in each sub-function module power port, building voltage glitch detects network, and design is simple, real
It is now easy, is conducive to various system optimizations and upgrades.
The present invention also provides a kind of computer readable storage medium, computer-readable recording medium storage have one or
Multiple programs, one or more program are performed, the step of to realize method provided by all embodiments of the invention.
By the implementation of above embodiments it is found that the present invention have it is following the utility model has the advantages that
The present invention provides a kind of direct fault locations to resist method and device, chip and computer readable storage medium, the party
Method sends alarm signal, in quilt when detecting abnormal signal by detecting the abnormal signal of the power port of module to be protected
When alarm signal triggers, instruction is resisted according to security strategy generation, execution is resisted instruction progress direct fault location and resisted；It realizes pair
The detection of the abnormal signal of the local function module of chip, and carry out direct fault location according to testing result and resist, it solves existing
The direct fault location defense technique problem bad for local fault injection protection effect.
The above content is specific embodiment is combined, further detailed description of the invention, and it cannot be said that this hair
Bright specific implementation is only limited to these instructions.For those of ordinary skill in the art to which the present invention belongs, it is not taking off
Under the premise of from present inventive concept, a number of simple deductions or replacements can also be made, all shall be regarded as belonging to protection of the invention
Range.
Claims (10)
1. a kind of direct fault location resists method, which is characterized in that for the chip including multiple functional modules, the direct fault location
The method of resisting includes:
Detect the abnormal signal of the power port of module to be protected；
When detecting abnormal signal, alarm signal is sent；
When being triggered by the alarm signal, instruction is resisted according to security strategy generation；
Instruction progress direct fault location is resisted described in execution to resist.
2. direct fault location as described in claim 1 resists method, which is characterized in that the power end of the detection module to be protected
Mouthful abnormal signal include:
The voltage glitch of the power port is detected, and when detecting voltage glitch, judgement detects abnormal signal；
And/or the clock bur of the power port being detected, and when detecting clock bur, judgement detects abnormal signal.
3. direct fault location as claimed in claim 1 or 2 resists method, which is characterized in that resisted described in the execution instruct into
Row direct fault location, which is resisted, includes:
The instruction reset module to be protected is resisted according to described；
And/or the instruction removing module to be protected is resisted according to described.
4. a kind of direct fault location resists device, which is characterized in that described for the chip including processor and multiple functional modules
Direct fault location resists device
Detection unit connect with the power port of module to be protected in the chip, for detecting abnormal signal, and is detecting
When abnormal signal, Xiang Suoshu processor sends alarm signal；
Unit is resisted, finger generated is being resisted by alarm signal triggering according to security strategy for receiving the processor
It enables, and resists instruction progress direct fault location described in execution and resist.
5. direct fault location as claimed in claim 4 resists device, which is characterized in that the detection unit includes voltage glitch inspection
Unit is surveyed, the voltage glitch detection unit is used to detect the voltage glitch of the power port, and is detecting voltage glitch
When, judgement detects that abnormal signal, Xiang Suoshu processor send alarm signal.
6. direct fault location as claimed in claim 4 resists device, which is characterized in that the detection unit includes clock bur inspection
Unit is surveyed, the voltage glitch detection unit is used to detect the clock bur of the power port, and is detecting clock bur
When, judgement detects that abnormal signal, Xiang Suoshu processor send alarm signal.
7. as the described in any item direct fault locations of claim 4 to 6 resist device, which is characterized in that the chip includes processing
Device, storage chip and storage control, the storage control include multiple functional modules, and the detection unit includes multiple inspections
Subelement is surveyed, the detection sub-unit is arranged in each functional module of storage control, and the power supply with corresponding function module
Port connection.
8. direct fault location as claimed in claim 7 resists device, which is characterized in that the unit of resisting according to for supporting
Imperial instruction resets the storage control and/or removes the storage chip.
9. a kind of chip, which is characterized in that including processor, multiple functional modules and such as any one of claim 4 to 8 institute
The direct fault location stated resists device.
10. a kind of computer readable storage medium, which is characterized in that the computer-readable recording medium storage have one or
Multiple programs, one or more of programs can be executed by one or more processor, to realize such as claims 1 to 3
The step of described in any item direct fault locations resist method.
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| CN2017114809871 | 2017-12-29 | ||
| CN201711480987 | 2017-12-29 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111010267A (en) * | 2019-11-14 | 2020-04-14 | 上海华虹集成电路有限责任公司 | Method for encrypting internal security detection sensor signal of chip based on random number |
| CN112148103A (en) * | 2020-09-09 | 2020-12-29 | 北京中电华大电子设计有限责任公司 | Circuit for protecting power supply attack implemented from PAD |
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| CN1740980A (en) * | 2004-08-29 | 2006-03-01 | 华为技术有限公司 | Fault filling method and apparatus based on programmable logical device |
| CN105391542A (en) * | 2015-10-22 | 2016-03-09 | 天津大学 | Detection method and detector applied to integrated circuit for detecting electromagnetic fault injection attack |
| US20170344438A1 (en) * | 2016-05-24 | 2017-11-30 | Virginia Polytechnic Institute And State University | Microprocessor fault detection and response system |
-
2018
- 2018-01-18 CN CN201810049993.XA patent/CN109992959A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1740980A (en) * | 2004-08-29 | 2006-03-01 | 华为技术有限公司 | Fault filling method and apparatus based on programmable logical device |
| CN105391542A (en) * | 2015-10-22 | 2016-03-09 | 天津大学 | Detection method and detector applied to integrated circuit for detecting electromagnetic fault injection attack |
| US20170344438A1 (en) * | 2016-05-24 | 2017-11-30 | Virginia Polytechnic Institute And State University | Microprocessor fault detection and response system |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111010267A (en) * | 2019-11-14 | 2020-04-14 | 上海华虹集成电路有限责任公司 | Method for encrypting internal security detection sensor signal of chip based on random number |
| CN112148103A (en) * | 2020-09-09 | 2020-12-29 | 北京中电华大电子设计有限责任公司 | Circuit for protecting power supply attack implemented from PAD |
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