CN104268487A - Reset and self-destruction management system for security chip - Google Patents
Reset and self-destruction management system for security chip Download PDFInfo
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- CN104268487A CN104268487A CN201410488611.5A CN201410488611A CN104268487A CN 104268487 A CN104268487 A CN 104268487A CN 201410488611 A CN201410488611 A CN 201410488611A CN 104268487 A CN104268487 A CN 104268487A
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
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Abstract
The invention discloses a reset and self-destruction management system for a security chip. The reset and self-destruction management system comprises a security chip on which a central processing unit is encapsulated; a reset management unit, a self-destruction management unit, a power supply management unit, a debugging unit, an encryption and decryption unit, a storage and a bus unit are connected to the central processing unit, wherein the reset management unit and the self-destruction management unit are both connected to a plurality of abnormity detection units for detecting abnormal analog or digit of each unit in the detection system; when the abnormity detection units detect that the certain unit is abnormal, an abnormity signal is output to a central processing unit; after receiving the abnormity signal, the central processing unit emits a reset enable signal or a self-destruction enable signal of the corresponding unit to the reset management unit or the self-destruction management unit which consequently resets or selectively self-destructs the corresponding unit after receiving the corresponding enable signal.
Description
Technical field
The present invention relates to a kind of reset and self-destruction management system of safety chip.
Background technology
In information security application, the safety chip based on specific cryptosystem algorithm can provide confidentiality and integrity protection for sensitive information.Meanwhile, the vital role of safety chip in information safety protection makes it easily suffer various attack, is faced with more and more serious security challenge, has occurred the attack means of various different levels, varying level.These attack meanses sum up and mainly contain two kinds: Nondestructive attack and Subversive attack, the former comprises eavesdropping attack method (i.e. power consumption analysis method), software attacks method and fault attacks method (as high/low temperature, high-low pressure, speed clock, electromagnetic interference (EMI) etc.), and the latter is microcell detection method (as FIB or oppositely analysis).For above-mentioned Nondestructive attack method, the multiple effective countermeasure of current property cryptographic algorithm and development place of circuit design aspect, as mask technology, power-consumption balance technology, clock upset technology etc.In addition, for software attacks, fault attacks and microcell detection etc., devise various detecting unit, when chip is subjected to corresponding attack, detecting unit is abnormal to chip report, and chip pins responds to abnormal.Reset is able to widespread use as the effective response means easily of one, and the response means of higher security level is exactly self-destruction.So how to manage various exceptional reset at chip internal, how to realize self-destruction more important than the single exception of process, and the anti-attack ability of this reset and self-destruct circuit self is also of crucial importance.
Summary of the invention
The invention provides a kind of exception to chip to manage, reset and the self-destruction management system of the safety chip of exceptional reset and self-destruction can be realized.
The technical solution used in the present invention is:
A kind of reset of safety chip and self-destruction management system, it is characterized in that: comprise a safety chip, described safety chip is packaged with central processing unit, described central processing unit is connected with reset administrative unit, self-destruction administrative unit, Power Management Unit, debugging unit, encryption/decryption element, storer, bus unit, described reset administrative unit is all connected with abnormality detecting unit with self-destruction administrative unit, described abnormality detecting unit comprises the abnormality detecting unit of the analog or digital of multiple abnormal conditions for unit each in detection system, when described abnormality detecting unit detects certain unit exception, then export the abnormal signal of this unit to central processing unit, central processing unit sends the reset enable signal of corresponding units or self-destruction enable signal to reset administrative unit or self-destruction administrative unit after receiving abnormal signal, described reset administrative unit or self-destruction administrative unit reset or selectivity self-destruction to corresponding unit when receiving corresponding enable signal.
Further, described abnormality detecting unit comprises the SRAM detecting unit, ROM detecting unit, active shielding layer detecting unit, lower electro-detection unit, core voltage detecting unit, core external voltage detecting unit, temperature detecting unit, frequency detecting unit, outside self-destruction input detection unit, house dog detecting unit, MPU protection exception detecting unit, electromagnetic detecting unit, the optical detecting unit that detect corresponding units.These detecting units cover the detection of software attacks common at present, fault attacks and microcell, have carried out detecting protection to the various attack media that chip subjects to.
Further, described reset administrative unit adopts the method for leveled reset to manage the effective source of various exception and chip functions reset source, reset grade totally three grades, the first order resets and is jointly produced by chip internal electrification reset and external reset, is the Global reset source under normal functioning mode; The second level is reset to Global reset source and each exceptional reset produces jointly, is systematic reset signal; The third level is reset to systematic reset signal and warm reset produces jointly, is bus reset signal; Described bus reset signal is used for the abnormality detecting unit of reset bus unit, storer, encryption/decryption element and SRAM, ROM, MPU; Systematic reset signal is used for the assembly that reset power administrative unit, debugging unit and bus reset signal reset to; Global reset source is used for the assembly that arrives of resetting system reseting signal reset and active shielding layer detecting unit, lower electro-detection unit, core voltage detecting unit, core external voltage detecting unit, temperature detecting unit, frequency detecting unit, self-destruction input detect, electromagnetic detecting unit and house dog detecting unit.The Power Management Unit that systematic reset signal resets and debugging unit do not affect by bus reset, and the anomaly detection component that Global reset source resets or not by systematic reset signal and bus reset signal and affects.The method of this leveled reset is that each reset source is provided with different reset authorities, does not affect chip and use volume convenience while guarantee chip security.
Further, always in running order after abnormality detecting unit irrelevant with bus reset in the leveled reset of described reset administrative unit powers on, continue to detect extremely, not by the impact of each reset mode in chip; The abnormality detecting unit relevant to bus reset restarts detection by new configuration when relevant abnormality detecting unit above-mentioned after bus reset, until bus reset next time.
Further, described safety chip in the normal mode of operation each abnormality detecting unit should be " 1 " output entirely, now Global reset source switches to systematic reset signal, and after certain abnormality detecting unit detects abnormal output " 0 ", this abnormal signal will be added on systematic reset signal.For improving the application adaptability of chip, be each abnormality detection configuration enable signal, each exception only just can produce reset signal when the enable signal of correspondence is effective, arranges reset and protection targetedly at different application scenarioss.
Further, described self-destruction administrative unit is used for, when exception being detected, the key message of the storer of safety chip is carried out elimination, when abnormality detecting unit detects that core voltage, core external voltage, working temperature, self-destruction input, frequency of operation, electromagnetism, SRAM, ROM, MPU occur abnormal, central processing unit starts the self-destruction operation of self-destruction administrative unit: one closes the power switch of powering to SRAM, cuts off the power supply of SRAM; Two start FALSH self-destruction controller, and this self-destruction controller performs claimed FLASH content and inserts except operation, close the normal value to FLASH and peek path simultaneously.Electrification reset in the present invention, lower point reset, house dog is normal function assembly, and do not control self-destruction operation, the storer storing key message in chip has SRAM, FLASH, and the different qualities because of SRAM and FLASH adopts different self-destruction means respectively.FLASH is nonvolatile memory, and after power down, data exist, and therefore adopt full sheet to insert except operation self-destruction, SRAM is volatile memory, adopts power down self-destruction.For improving the application adaptability of safety chip, be each abnormality detecting unit configuration enable signal, each exception only just can produce self-destruction signal when the enable signal of correspondence is effective, arranges self-destruction protection targetedly at different application scenarioss.
Central processing unit in the present invention is the working centre of chip, for various application and development, attack resistance technology provide hardware platform and program.Described abnormality detecting unit is detecting that the corresponding abnormal signal of abnormal rear output is to central processing unit, and central processing unit sends corresponding enable signal to reset administrative unit and self-destruction administrative unit.Described reset administrative unit adopts the method for leveled reset to manage the effective source of various exception and chip functions reset source.Described self-destruction administrative unit is used for, when exception being detected, the key message of the storer of safety chip is carried out elimination.Power Management Unit is power management component, and under central processing unit can being made to be operated in various battery saving mode by this assembly, this unit does not affect by warm reset.Debugging unit is the debug component of chip; the resource such as register, storer of chip internal can be observed by this assembly debugging acid; this assembly does not affect by warm reset; after safety chip Program has been debugged; debug port understands locking usually, prevents Data within the chip from being peeped by debug port.Bus unit is the peripheral control unit that Standard bus interface and this interface connect, as SPI, I2C, UART, USB, symmetry algorithm accelerator, asymmetric arithmetic accelerator, FLASH controller, SRAM controller etc.Storer is the memory module of chip, usually has volatile memory and nonvolatile memory, and volatile memory is SRAM, and nonvolatile memory is FLASH.Encryption/decryption element is a unit that can realize one or more enciphering and deciphering algorithms, these algorithms have symmetry algorithm usually (as AES simultaneously, DES/3DES, the close SM1 of state etc.) and asymmetric arithmetic (as RSA, ECC, the close SM2 of state etc.), this unit can adopt pure hardware implementing, and soft or hard combination also can be adopted to realize.
Beneficial effect of the present invention: introduce reset administrative unit and self-destruction administrative unit, process reset (functional reduction and exceptional reset) and self-destruction respectively, reset is divided into Three Estate by reset authority difference by reset administrative unit: Global reset, system reset, bus reset, the method of this leveled reset is that each reset source is provided with different reset authorities, does not affect chip and use volume convenience while guarantee chip security.The object of self-destruction is SRAM and FLASH, and the former adopts the mode of power down to realize self-destruction, and latter detects that the abnormal FLASH full sheet that just starts is inserted except operation.In order to take into account the safety and stability of chip in different application field, for each abnormal output arranges reset enable and self-destruction is enable, only have as this exception enable effective, reset administrative unit and self-destruction administrative unit just can produce corresponding reset signal and self-destruction signal, start reset and the self-destruction operation of corresponding grade.In the present invention, in security chip design, the rational management of each anomaly source is orderly, along with the continuous lifting of attacking ability, the anomaly detector of attack protection will be on the increase, deviser be only required to be the anomaly detector that newly increases arrange with apply corresponding reset grade, enable and self-destruction is enable.
Accompanying drawing explanation
Fig. 1 is theory diagram of the present invention.
Fig. 2 is the leveled reset schematic diagram of reset administrative unit of the present invention.
Fig. 3 is the self-destruction schematic diagram of self-destruction administrative unit of the present invention.
Fig. 4 is a kind of embody rule schematic diagram of the present invention.
Embodiment
Below in conjunction with specific embodiment, the present invention is further described, but does not limit the invention to these embodiments.One skilled in the art would recognize that all alternativess, improvement project and the equivalents that present invention encompasses and may comprise in Claims scope.
With reference to Fig. 1-3, a kind of reset of safety chip and self-destruction management system, comprise a safety chip, described safety chip is packaged with central processing unit 1, described central processing unit 1 is connected with reset administrative unit 2, self-destruction administrative unit 3, Power Management Unit 4, debugging unit 5, encryption/decryption element 8, storer 7, bus unit 6, described reset administrative unit 2 is all connected with abnormality detecting unit 9 with self-destruction administrative unit 3, described abnormality detecting unit 9 comprises the abnormality detecting unit 9 of the analog or digital of multiple abnormal conditions for unit each in detection system, when described abnormality detecting unit 9 detects certain unit exception, then export the abnormal signal of this unit to central processing unit 1, central processing unit 1 sends the reset enable signal of corresponding units or self-destruction enable signal to reset administrative unit 2 or self-destruction administrative unit 3 after receiving abnormal signal, described reset administrative unit 2 or self-destruction administrative unit 3 reset or selectivity self-destruction to corresponding unit when receiving corresponding enable signal.
Abnormality detecting unit 9 of the present invention comprises the SRAM detecting unit, ROM detecting unit, active shielding layer detecting unit ActiveShield, lower electro-detection unit, core voltage detecting unit, core external voltage detecting unit, temperature detecting unit, frequency detecting unit, outside self-destruction input detection unit, house dog detecting unit, MPU protection exception detecting unit, electromagnetic detecting unit, the optical detecting unit that detect corresponding units.These detecting units cover the detection of software attacks common at present, fault attacks and microcell, have carried out detecting protection to the various attack media that chip subjects to.
Reset administrative unit 2 of the present invention adopts the method for leveled reset to manage the effective source of various exception and chip functions reset source, reset grade totally three grades, the first order resets and is jointly produced by chip internal electrification reset and external reset, is the Global reset source GLOBALREETn under normal functioning mode; The second level is reset to Global reset source GLOBALREETn and each exceptional reset produces jointly, is systematic reset signal MCURESETn; The third level is reset to systematic reset signal MCURESETn and warm reset produces jointly, is bus reset signal HRESETn; Described bus reset signal HRESETn is used for the abnormality detecting unit of reset bus unit 6, storer 7, encryption/decryption element 8 and SRAM, ROM, MPU; Systematic reset signal MCURESETn is used for the assembly that reset power administrative unit 4, debugging unit 5 and bus reset signal HRESETn reset to; Global reset source GLOBALREETn is used for the assembly that resets to of resetting system reset signal MCURESETn and active shielding layer detecting unit, lower electro-detection unit, core voltage detecting unit, core external voltage detecting unit, temperature detecting unit, frequency detecting unit, self-destruction input detect, electromagnetic detecting unit and house dog detecting unit.The Power Management Unit 4 that systematic reset signal MCURESETn resets and debugging unit 5 do not affect by bus reset, and the anomaly detection component that Global reset source GLOBALREETn resets or not by systematic reset signal MCURESETn and bus reset signal HRESETn and affects.The method of this leveled reset is that each reset source is provided with different reset authorities, does not affect chip and use volume convenience while guarantee chip security.
Always in running order after abnormality detecting unit 9 irrelevant with bus reset in the leveled reset of reset administrative unit 2 of the present invention powers on, continue to detect extremely, not by the impact of each reset mode in chip; The abnormality detecting unit 9 relevant to bus reset restarts detection by new configuration when relevant abnormality detecting unit 9 above-mentioned after bus reset, until bus reset next time.
Safety chip of the present invention in the normal mode of operation each abnormality detecting unit 9 should be " 1 " output entirely, now Global reset source GLOBALREETn switches to systematic reset signal MCURESETn, after certain abnormality detecting unit 9 detects abnormal output " 0 ", this abnormal signal will be added on systematic reset signal MCURESETn.For improving the application adaptability of chip, be each abnormality detection configuration enable signal, each exception only just can produce reset signal when the enable signal of correspondence is effective, arranges reset and protection targetedly at different application scenarioss.
Self-destruction administrative unit 3 of the present invention is for carrying out elimination when exception being detected by the key message of the storer 7 of safety chip, when abnormality detecting unit 9 detects that core voltage, core external voltage, working temperature, self-destruction input, frequency of operation, electromagnetism, SRAM, ROM, MPU occur abnormal, central processing unit 1 starts the self-destruction operation of self-destruction administrative unit 3: one closes the power switch of powering to SRAM, cuts off the power supply of SRAM; Two start FALSH self-destruction controller, and this self-destruction controller performs claimed FLASH content and inserts except operation, close the normal value to FLASH and peek path simultaneously.Electrification reset POR in the present invention, lower some reset BOD, house dog WDT are normal function assembly, self-destruction operation is not controlled, the storer storing key message in chip has SRAM, FLASH, and the different qualities because of SRAM and FLASH adopts different self-destruction means respectively.FLASH is nonvolatile memory, and after power down, data exist, and therefore adopt full sheet to insert except operation self-destruction, SRAM is volatile memory, adopts power down self-destruction.For improving the application adaptability of safety chip, be each abnormality detecting unit configuration enable signal, each exception only just can produce self-destruction signal when the enable signal of correspondence is effective, arranges self-destruction protection targetedly at different application scenarioss.
Central processing unit 1 in the present invention is the working centre of chip, for various application and development, attack resistance technology provide hardware platform and program.Described abnormality detecting unit 9 is detecting that the corresponding abnormal signal of abnormal rear output is to central processing unit, and central processing unit 1 sends corresponding enable signal to reset administrative unit 2 and self-destruction administrative unit 3.Described reset administrative unit 2 adopts the method for leveled reset to manage the effective source of various exception and chip functions reset source.Described self-destruction administrative unit 3 is for carrying out elimination when exception being detected by the key message of the storer 7 of safety chip.Power Management Unit 4 is power management component, and under central processing unit can being made to be operated in various battery saving mode by this assembly, this unit does not affect by warm reset.Debugging unit 5 is the debug component of chip; the resource such as register, storer of chip internal can be observed by this assembly debugging acid; this assembly does not affect by warm reset; after safety chip Program has been debugged; debug port understands locking usually, prevents Data within the chip from being peeped by debug port.Bus unit 6 is the peripheral control unit that Standard bus interface and this interface connect, as SPI, I2C, UART, USB, symmetry algorithm accelerator, asymmetric arithmetic accelerator, FLASH controller, SRAM controller etc.Storer 7 is the memory module of chip, usually has volatile memory and nonvolatile memory, and volatile memory is SRAM, and nonvolatile memory is FLASH.Encryption/decryption element 8 is the unit that can realize one or more enciphering and deciphering algorithms, these algorithms have symmetry algorithm usually (as AES simultaneously, DES/3DES, the close SM1 of state etc.) and asymmetric arithmetic (as RSA, ECC, the close SM2 of state etc.), this unit can adopt pure hardware implementing, and soft or hard combination also can be adopted to realize.
A kind of application specifically:
See Fig. 4, the present embodiment is the SOC safety chip based on ARM Cortex-M0, and storage resources has ROM, SRAM, FLASH, controls by MPU the access of storage resources.Memory access control (MPU) function realizes based on the memory access control strategy of safety, and this access control policy core is subregion and control of authority.ROM adopts address to upset and data encryption storage mode guarantees data security, and SRAM then adopts address to upset and data integrity verifying guarantees data security.
The present embodiment algorithm unit comprises symmetry algorithm and asymmetric arithmetic, and wherein symmetry algorithm has AES, DES/3DES, the close SM1 of state etc., and asymmetric arithmetic has RSA, ECC, the close SM2 of state etc.Peripheral unit is connected with cpu bus by ahb bus or APB bus, wherein ahb bus unit has USB, SD card to have random number generator TRNG, smart card master controller SCI, smart card from controller SCSI, voice PWM (VPWM), single-wire-protocol main interface SWPM, single-wire-protocol from interface SWPS, real-time clock RTC, general purpose I/O controller (GPIO), I2C, UART, SPI, SPI from interface (SSI) from controller SDSI, four-way serial FLASH (SQI FLASH), FLASH, APB bus unit.
The present embodiment carries out differentiated control by reset and self-destruction administrative unit (SCM) to chip reset, requires that higher application adopts self-destruction management to safe class.The exception of this reset and the process of self-destruction administrative unit has: upper electro-detection, lower electro-detection, voltage detecting (comprising core voltage to detect and the detection of core external voltage), light detection, electromagnetic detection, active shielding detection, temperature detection, frequency detecting, MPU are extremely, SRAM is abnormal, ROM is abnormal.
In the present embodiment, power supply is managed by power conversion unit, and upper electro-detection, lower electro-detection and voltage detecting are monitored Power Management Unit, respond to abnormal electrical power supply.
In the present embodiment, clock is produced by clock generating unit, and the clock input of frequency detecting to clock generating unit detects, and responds to clock input is abnormal.
Light detection in the present embodiment, electromagnetic detection, active shielding detection, temperature detection are all simulated assemblies, process the physical attacks means of photodetection, electromagnetic interference (EMI), FIB, temperature anomaly respectively, bootrom reset or self-destruction, once receive exceptions output signal of these simulation establishments, operate by reset and self-destruction administrative unit.
In the present embodiment, the abnormal of MPU, SRAM, ROM is realized by digital units, MPU unit is once occur that current restrict access region is accessed to and will produces access exception, SRAM, ROM make mistakes once the verification of sense data and just produce access exception, by reset and self-destruction administrative unit bootrom resets and self-destruction operates.
Claims (6)
1. the reset of a safety chip and self-destruction management system, it is characterized in that: comprise a safety chip, described safety chip is packaged with central processing unit, described central processing unit is connected with reset administrative unit, self-destruction administrative unit, Power Management Unit, debugging unit, encryption/decryption element, storer, bus unit, described reset administrative unit is all connected with abnormality detecting unit with self-destruction administrative unit, described abnormality detecting unit comprises the abnormality detecting unit of the analog or digital of multiple abnormal conditions for unit each in detection system, when described abnormality detecting unit detects certain unit exception, then export the abnormal signal of this unit to central processing unit, central processing unit sends the reset enable signal of corresponding units or self-destruction enable signal to reset administrative unit or self-destruction administrative unit after receiving abnormal signal, described reset administrative unit or self-destruction administrative unit reset or selectivity self-destruction to corresponding unit when receiving corresponding enable signal.
2. the reset of a kind of safety chip according to claim 1 and self-destruction management system, is characterized in that: described abnormality detecting unit comprises the SRAM detecting unit, ROM detecting unit, active shielding layer detecting unit, lower electro-detection unit, core voltage detecting unit, core external voltage detecting unit, temperature detecting unit, frequency detecting unit, outside self-destruction input detection unit, house dog detecting unit, MPU protection exception detecting unit, electromagnetic detecting unit, the optical detecting unit that detect corresponding units.
3. the reset of a kind of safety chip according to claim 2 and self-destruction management system, it is characterized in that: described reset administrative unit adopts the method for leveled reset to manage the effective source of various exception and chip functions reset source, reset grade totally three grades, the first order resets and is jointly produced by chip internal electrification reset and external reset, is the Global reset source under normal functioning mode; The second level is reset to Global reset source and each exceptional reset produces jointly, is systematic reset signal; The third level is reset to systematic reset signal and warm reset produces jointly, is bus reset signal; Described bus reset signal is used for the abnormality detecting unit of reset bus unit, storer, encryption/decryption element and SRAM, ROM, MPU; Systematic reset signal is used for the assembly that reset power administrative unit, debugging unit and bus reset signal reset to; Global reset source is used for the assembly that arrives of resetting system reseting signal reset and active shielding layer detecting unit, lower electro-detection unit, core voltage detecting unit, core external voltage detecting unit, temperature detecting unit, frequency detecting unit, self-destruction input detect, electromagnetic detecting unit and house dog detecting unit.
4. the reset of a kind of safety chip according to claim 3 and self-destruction management system, it is characterized in that: always in running order after abnormality detecting unit irrelevant with bus reset in the leveled reset of described reset administrative unit powers on, continue to detect extremely, not by the impact of each reset mode in chip; The abnormality detecting unit relevant to bus reset restarts detection by new configuration when relevant abnormality detecting unit above-mentioned after bus reset, until bus reset next time.
5. the reset of a kind of safety chip according to claim 3 and self-destruction management system, it is characterized in that: described safety chip in the normal mode of operation each abnormality detecting unit should be " 1 " output entirely, now Global reset source switches to systematic reset signal, after certain abnormality detecting unit detects abnormal output " 0 ", this abnormal signal will be added on systematic reset signal.
6. according to reset and the self-destruction management system of a kind of safety chip one of claim 1 ~ 5 Suo Shu, it is characterized in that: described self-destruction administrative unit is used for, when exception being detected, the key message of the storer of safety chip is carried out elimination, when abnormality detecting unit detects that core voltage, core external voltage, working temperature, self-destruction input, frequency of operation, electromagnetism, SRAM, ROM, MPU occur abnormal, central processing unit starts the self-destruction operation of self-destruction administrative unit: one closes the power switch of powering to SRAM, cuts off the power supply of SRAM; Two start FALSH self-destruction controller, and this self-destruction controller performs claimed FLASH content and inserts except operation, close the normal value to FLASH and peek path simultaneously.
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