CN106156827B - A kind of chip information protective device and method - Google Patents
A kind of chip information protective device and method Download PDFInfo
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- CN106156827B CN106156827B CN201610616397.6A CN201610616397A CN106156827B CN 106156827 B CN106156827 B CN 106156827B CN 201610616397 A CN201610616397 A CN 201610616397A CN 106156827 B CN106156827 B CN 106156827B
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- 238000000034 method Methods 0.000 title claims description 12
- 230000001681 protective effect Effects 0.000 title abstract 2
- 238000012790 confirmation Methods 0.000 claims abstract description 16
- 230000006378 damage Effects 0.000 claims description 16
- 239000002245 particle Substances 0.000 claims description 12
- 230000005540 biological transmission Effects 0.000 claims description 3
- 239000013078 crystal Substances 0.000 claims description 3
- 238000003491 array Methods 0.000 claims description 2
- 238000007664 blowing Methods 0.000 description 3
- 238000004891 communication Methods 0.000 description 3
- 230000000977 initiatory effect Effects 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/073—Special arrangements for circuits, e.g. for protecting identification code in memory
- G06K19/07309—Means for preventing undesired reading or writing from or onto record carriers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
- G06F21/79—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computer Security & Cryptography (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Software Systems (AREA)
- Storage Device Security (AREA)
Abstract
The present invention provides a kind of chip information protective device, including mobile receiving unit, local password confirmation module, password error counting judging unit, eFuse fusing control unit, efuse array, 4 efuse value judging units, cmos signal switch, MTCMOS power switch, Flash initialization control unit, storing initial unit and confidential information storage unit；Mobile receiving unit is separately connected remote control unit and eFuse fusing control unit；Local password confirmation module, password error count judging unit, eFuse fusing control unit and efuse array and are sequentially connected；Efuse array connects cmos signal switch, MTCMOS power switch, Flash initialization control unit, storing initial unit by one of efuse value judging unit respectively, and storing initial unit connects confidential information storage unit.The present invention can allow chip self-destroying in the case where confirmation is by Brute Force, or only completely eliminate private data without damaging chip.
Description
Technical Field
The invention relates to a chip information protection device and a chip information protection method.
Background
With the increasing development of mobile electronic devices, mobile electronic devices such as mobile phones and tablet computers have been widely applied to electronic payment and functions of receiving and sending important personal short messages and mails, and a large amount of personal privacy information and confidential information of users are stored in the mobile electronic devices, so that the security performance of the mobile electronic devices is increasingly emphasized. In the case of loss or theft of an electronic device, how to protect the secret data in the electronic device is a very important issue.
The prior art has the following defects:
1. a hacker can crack secret data of electronic equipment in a brute force cracking mode, the chip protection technology cannot actively destroy the data under the condition that the data are cracked violently at present, a machine can be locked on a software level generally, the secret data still exist in a hardware and chip level, the eMMC chip or other flash memory chips on a circuit board can be picked up when the hacker cracks violently, although the secret data in the memory chip usually has encryption protection, the hacker can crack and acquire the secret data through various means;
2. hackers may also obtain secure data by slicing through the storage array.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide a chip information protection apparatus and method, which can enable a chip to be self-destructed under the condition of confirming that the chip is cracked violently, so that a hacker cannot achieve the purpose of obtaining secret data.
The chip information protection device of the invention is realized as follows: a chip information protection device comprises a mobile receiving unit, a local password confirmation module, a password error counting judgment unit, an efuse fusing control unit, an efuse array, 4 efuse value judgment units, a CMOS (complementary metal oxide semiconductor) signal switch, a MTCMOS (multiple-terminal-programmable metal oxide semiconductor) power switch, a Flash initialization control unit, a storage initialization unit and a secret information storage unit;
the mobile receiving unit is respectively connected with a remote control unit and the efuse fusing control unit;
the local password confirmation module, the password error counting judgment unit, the efuse fusing control unit and the efuse array are sequentially connected;
the efuse array is respectively connected with the CMOS signal switch, the MTCMOS power switch, the Flash initialization control unit and the storage initialization unit through one of the efuse value judgment units;
the CMOS signal switch is also connected with a chip external crystal oscillator clock source; the MTCMOS power switch is also connected with a chip power supply outside the chip; the Flash initialization control unit is also connected with Flash storage particles outside the chip; the storage initialization unit is connected with the secret information storage unit.
Furthermore, the chip information protection device also comprises a security level setting storage unit which is respectively connected with the password error counting judgment unit and the efuse fusing control unit.
Furthermore, the mobile receiving unit, the local password confirmation module, the password error counting judgment unit, the security level setting storage unit, the efuse fusing control unit, the efuse array, the 4 efuse value judgment units, the CMOS signal switch, the MTCMOS power switch, the Flash initialization control unit, the storage initialization unit and the security information storage unit are all integrated in a chip.
The chip information protection method of the invention is realized as follows: a chip information protection method provides the chip information protection device of the invention, and comprises the following steps:
the mobile receiving unit receives a remote self-destruction command through a wireless channel and sends the self-destruction command to the efuse fusing control unit;
when the password error transmission times of the local user are larger than a preset password error tolerance threshold value, the password error counting and judging unit sends a self-destruction command to the efuse fusing control unit;
after receiving the remote self-destruction command or sending the self-destruction command by the password error counting judgment unit, the efuse fusing control unit writes a specific value into the efuse array to represent that different destruction operations are executed;
the 4 efuse value judging units carry out numerical value judgment according to the efuse arrays and execute corresponding destruction operation;
the destruction operation includes:
resetting and initializing Flash storage particles outside the chip through the Flash initialization control unit;
the memory initialization unit is used for resetting and initializing the memory content of the secret information memory unit in the chip;
turning off the power supply of the chip through the MTCMOS power switch;
and turning off a clock source of the chip through the CMOS signal switch.
Furthermore, when the device is used for the first time, a storage security level and the preset password error tolerance threshold value are set and stored in a security level setting storage unit, and the security level setting storage unit is respectively connected with the password error counting judgment unit and the efuse fusing control unit; the efuse fusing control unit writes a specific value into the efuse array according to the storage security level;
the security level represented by the specific value is that only the security data is destroyed, and then the destruction operation is:
resetting and initializing Flash storage particles outside the chip through the Flash initialization control unit; the memory initialization unit is used for resetting and initializing the memory content of the secret information memory unit in the chip;
if the security level represented by the specific value is a destruction chip, the destruction operation is:
resetting and initializing Flash storage particles outside the chip through the Flash initialization control unit; the memory initialization unit is used for resetting and initializing the memory content of the secret information memory unit in the chip; then, the power supply of the chip is turned off through the MTCMOS power switch; and turning off a clock source of the chip through the CMOS signal switch.
The invention has the following advantages:
1. the chip can be self-destroyed under the condition of confirming that the chip is cracked violently, so that a hacker can not achieve the purpose of obtaining the confidential data;
2. the self-destruction level during self-protection can be configured, so that the chip can be completely damaged, or the secret data can be completely eliminated without damaging the chip.
Drawings
The invention will be further described with reference to the following examples with reference to the accompanying drawings.
FIG. 1 is a flow chart of the method of the present invention.
Detailed Description
As shown in fig. 1, the chip information protection apparatus 100 of the present invention includes a mobile receiving unit 101, a local password confirmation module 102, a password error count determination unit 103, a security level setting storage unit 104, an efuse blowing control unit 105, an efuse array 106, 4 efuse value determination units 107, a CMOS signal switch 108, an MTCMOS power switch 109, a Flash initialization control unit 110, a storage initialization unit 111, and a security information storage unit 112.
The mobile receiving unit 101 is respectively connected with a remote control unit 200 and the efuse fusing control unit 105; the local password confirmation module 102, the password error count determination unit 103, the efuse fuse control unit 105 and the efuse array 106 are connected in sequence; the security level setting storage unit 104 is respectively connected with the password error count determination unit 103 and the efuse fusing control unit 105; the efuse array 106 is respectively connected with the CMOS signal switch 108, the MTCMOS power switch 109, the Flash initialization control unit 110, and the storage initialization unit 111 through one of the efuse value determination units 107; the storage initialization unit 111 is connected to the secret information storage unit 112.
The mobile receiving unit 101, the local password confirmation module 102, the password error counting determination unit 103, the security level setting storage unit 104, the efuse fusing control unit 105, the efuse array 106, the 4 efuse value determination units 107, the CMOS signal switch 108, the MTCMOS power switch 109, the Flash initialization control unit 110, the storage initialization unit 111, and the security information storage unit 112 are all integrated in a chip. The CMOS signal switch 108 is also connected with a chip external crystal oscillator clock source 301; the MTCMOS power switch 109 is also connected with a chip power supply 302 outside the chip; the Flash initialization control unit 110 also controls the Flash memory particles 303 outside the chip.
The remote control unit 200 is outside the chip and comprises an account authentication system 201, a remote control command initiating module 202 and a wireless communication channel 203 such as wifi or GPRS which are connected in sequence;
wherein,
the account authentication system 201 is used for a user to perform remote account authentication and login;
the remote control command initiating module 202 is responsible for receiving a command of an authorized user and sending a command of chip self-destruction operation to the mobile electronic device after the user logs in through the authentication of the account authentication system 201 remotely;
the mobile receiving unit 101 is configured to receive a self-destruction command through a wireless channel (a wireless communication channel such as wifi or GPRS) and send the self-destruction command to the efuse fusing control unit;
the local password confirmation module 102 is used for receiving a password input confirmation request operation of a local user, and judging whether the password is correct (the password here includes a numeric letter password, a gesture password, a fingerprint password and the like), if the password is judged to be correct, starting the device to enable the local user to normally use the device, and if the password is judged to be incorrect, requiring the user to input the password again, and meanwhile sending a password judgment error result to the password error counting judgment unit 103 for recording;
the password error counting and judging unit 103 is responsible for recording the password error transmission times of the local user, and comparing and judging the error times and the password error tolerance threshold stored in the security level setting and storing unit 104; if the user inputs the password for a plurality of times and the count value of the password error counter reaches the password error tolerance threshold stored in the security level setting storage unit 104, a self-destruction command is sent to the efuse fusing control unit 105;
the security level setting storage unit 104 is responsible for storing security level setting and password error tolerance times setting which are required when the device is used for the first time;
the efuse fusing control unit 105 is responsible for reading the security level from the security level setting storage unit 104 after receiving the destroy command, and writing a specific value to the efuse array 106 according to different levels to represent that different destroy operations are executed;
the efuse value determination unit 107 determines whether to execute a corresponding operation according to the value of the efuse array 106;
the CMOS signal switch 108 is responsible for turning off the clock source of the chip;
the MTCMOS power switch 109 is responsible for turning off the power supply of the chip;
the Flash initialization control unit 110 is responsible for zero clearing initialization of Flash storage particles outside the chip;
the storage initialization unit 111 is responsible for initializing the storage contents of the secret information storage unit 112 in the chip by clearing.
Based on the chip information protection apparatus 100 of the present invention, the chip information protection method of the present invention includes the following steps:
the initial setting of the mobile device requires a user to register an account, set a password, and then set the number of times that the password can be tolerated by error, and whether the processing level of the chip after receiving the destruction command is to thoroughly destroy the chip or to destroy only the confidential data, the set storage security level and the preset password error tolerance threshold value are stored in the security level setting storage unit 104, and the efuse fusing control unit 105 writes a specific value into the efuse array 106 according to the storage security level.
Conditions for remotely triggering efuse fuse control unit 105 to perform a fuse operation:
after a user remotely authenticates and logs in an account through the account authentication system 201, a remote control command initiating module 202 sends a chip self-destruction operation command, the remote self-destruction command reaches the mobile device through a wireless channel (wireless communication channels such as wifi or GPRS), and the mobile receiving unit 101 of the mobile device receives the remote self-destruction command through the wireless channel and sends the self-destruction command to the efuse fusing control unit 105.
The condition for the local operation to trigger the efuse blowing control unit 105 to perform the blowing operation:
when the local password confirmation module 102 receives a password input confirmation request of a local user, whether the password is correct (the password comprises password input modes such as a digital-letter password, a gesture password, a fingerprint password and the like) or not is judged, and if the password is correct, the local user starts the equipment to normally use the equipment; if the password is judged incorrectly, the user is required to input the password again, and meanwhile, the password judgment error result is sent to the password error counting judgment unit 103 for recording, if the user inputs the password for many times and the error input times are more than the preset password error tolerance threshold value, the password error counting judgment unit 103 sends a self-destruction command to the efuse fusing control unit 105;
destroying treatment:
after receiving the remote self-destruction command or the self-destruction command sent by the password error count determination unit 103, the efuse fuse control unit 105 reads the security level from the security level setting storage unit 104;
1. if the security level is to destroy only the security data, the following procedures are executed:
(1) writing a particular value to the efuse array 106 indicates performing a secure data destruction operation (such as 32' h5a5a5a5 a);
(2) the 4 efuse value determination units 107 always perform numerical value determination on the efuse array 106, and when the value is equal to the value of the destroyed secret data level, the Flash initialization control unit 110 and the storage initialization unit 111 start to operate, clear and initialize the storage content of the secret information storage unit 112 in the chip, and clear and initialize the Flash storage particles 303 outside the chip.
After the processing of destroying the confidential data, the chip can be used continuously, and only the confidential data inside the chip and outside the chip are cleared.
2. If the read security level in the security level setting storage unit is that the chip is completely destroyed, executing the following procedures:
(a) writing a particular value to the efuse array 106 indicates performing a secure data destruction operation (e.g., 32' hdeadded)
(b) The 4 efuse value judgment units 107 always perform numerical value judgment on the efuse array 106, and when the value is equal to the value at the chip destruction level, the Flash initialization control unit 110 and the storage initialization unit 111 start to work, clear and initialize the storage content of the secret information storage unit 112 in the chip, and clear and initialize the Flash storage particles 303 outside the chip;
(c) after the initialization and the zero clearing of the confidential data are finished, the MTCMOS power switch 109 turns off the power supply of the chip, and the CMOS signal switch 108 turns off the clock source of the chip, at this time, the chip does not work any more.
That is to say, after the chip is destroyed, the chip itself will cut off the power supply and the clock, and will not be used any more, and at the same time, the confidential data inside the chip and outside the chip will be cleared.
Although specific embodiments of the invention have been described above, it will be understood by those skilled in the art that the specific embodiments described are illustrative only and are not limiting upon the scope of the invention, and that equivalent modifications and variations can be made by those skilled in the art without departing from the spirit of the invention, which is to be limited only by the appended claims.
Claims (5)
1. A chip information protection device is characterized in that: the system comprises a mobile receiving unit, a local password confirmation module, a password error counting judgment unit, an efuse fusing control unit, an efuse array, 4 efuse value judgment units, a CMOS signal switch, an MTCMOS power switch, a Flash initialization control unit, a storage initialization unit and a secret information storage unit;
the mobile receiving unit is respectively connected with a remote control unit and the efuse fusing control unit;
the local password confirmation module, the password error counting judgment unit, the efuse fusing control unit and the efuse array are sequentially connected;
the efuse array is respectively connected with the CMOS signal switch, the MTCMOS power switch, the Flash initialization control unit and the storage initialization unit through one of the efuse value judgment units;
the CMOS signal switch is also connected with a chip external crystal oscillator clock source; the MTCMOS power switch is also connected with a chip power supply outside the chip; the Flash initialization control unit is also connected with Flash storage particles outside the chip; the storage initialization unit is connected with the secret information storage unit.
2. The chip information protection device of claim 1, wherein: the password protection device further comprises a security level setting storage unit which is respectively connected with the password error counting judgment unit and the efuse fusing control unit.
3. The chip information protection device of claim 2, wherein: the mobile receiving unit, the local password confirmation module, the password error counting judgment unit, the security level setting storage unit, the efuse fusing control unit, the efuse array, the 4 efuse value judgment units, the CMOS signal switch, the MTCMOS power switch, the Flash initialization control unit, the storage initialization unit and the security information storage unit are all integrated in a chip.
4. A chip information protection method is characterized in that: the chip information protection apparatus according to claim 1, and comprising the steps of:
the mobile receiving unit receives a remote self-destruction command through a wireless channel and sends the self-destruction command to the efuse fusing control unit;
when the password error transmission times of the local user are larger than a preset password error tolerance threshold value, the password error counting and judging unit sends a self-destruction command to the efuse fusing control unit;
after receiving the remote self-destruction command or sending the self-destruction command by the password error counting judgment unit, the efuse fusing control unit writes a specific value into the efuse array to represent that different destruction operations are executed;
the 4 efuse value judging units carry out numerical value judgment according to the efuse arrays and execute corresponding destruction operation;
the destruction operation includes:
resetting and initializing Flash storage particles outside the chip through the Flash initialization control unit;
the memory initialization unit is used for resetting and initializing the memory content of the secret information memory unit in the chip;
turning off the power supply of the chip through the MTCMOS power switch;
and turning off a clock source of the chip through the CMOS signal switch.
5. The chip information protection method according to claim 4, wherein:
when the device is used for the first time, the storage security level and the preset password error tolerance threshold value are set and stored in a security level setting storage unit, and the security level setting storage unit is respectively connected with the password error counting judgment unit and the efuse fusing control unit; the efuse fusing control unit writes a specific value into the efuse array according to the storage security level;
the security level represented by the specific value is that only the security data is destroyed, and then the destruction operation is:
resetting and initializing Flash storage particles outside the chip through the Flash initialization control unit; the memory initialization unit is used for resetting and initializing the memory content of the secret information memory unit in the chip;
if the security level represented by the specific value is a destruction chip, the destruction operation is:
resetting and initializing Flash storage particles outside the chip through the Flash initialization control unit; the memory initialization unit is used for resetting and initializing the memory content of the secret information memory unit in the chip; then, the power supply of the chip is turned off through the MTCMOS power switch; and turning off a clock source of the chip through the CMOS signal switch.
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| CN201610616397.6A CN106156827B (en) | 2016-07-29 | 2016-07-29 | A kind of chip information protective device and method |
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| CN201610616397.6A CN106156827B (en) | 2016-07-29 | 2016-07-29 | A kind of chip information protective device and method |
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| CN106156827A CN106156827A (en) | 2016-11-23 |
| CN106156827B true CN106156827B (en) | 2019-01-18 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US11776646B2 (en) | 2021-03-31 | 2023-10-03 | Microsoft Technology Licensing, Llc | Fuse based replay protection with dynamic fuse usage and countermeasures for fuse voltage cut attacks |
| US11860999B2 (en) | 2021-03-31 | 2024-01-02 | Microsoft Technology Licensing, Llc | Fuse based replay protection with aggressive fuse usage and countermeasures for fuse voltage cut attacks |
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| CN106778370B (en) * | 2016-12-23 | 2020-01-07 | 四川九洲电器集团有限责任公司 | Self-destruction method and device of device capable of moving autonomously |
| CN106650464A (en) * | 2016-12-29 | 2017-05-10 | 深圳市金立通信设备有限公司 | Security detection method and terminal |
| CN106960822B (en) * | 2017-03-30 | 2018-11-23 | 中国电子科技集团公司第二十四研究所 | A kind of integrated circuit self-destruction circuit and method trimming technology based on fuse |
| CN112270021B (en) * | 2020-09-23 | 2024-03-26 | 成都三零嘉微电子有限公司 | Wireless self-destruction control circuit and method for security chip |
| US11615187B2 (en) * | 2021-03-31 | 2023-03-28 | Microsoft Technology Licensing, Llc | Fuse based replay protection with conservative fuse usage |
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|---|---|
| CN106156827A (en) | 2016-11-23 |
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Address after: 350000 building, No. 89, software Avenue, Gulou District, Fujian, Fuzhou 18, China Patentee after: Ruixin Microelectronics Co., Ltd Address before: 350000 building, No. 89, software Avenue, Gulou District, Fujian, Fuzhou 18, China Patentee before: Fuzhou Rockchips Electronics Co.,Ltd. |