CN106776101B - Watchdog circuit and signal processing circuit - Google Patents
Watchdog circuit and signal processing circuit Download PDFInfo
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- CN106776101B CN106776101B CN201710113927.XA CN201710113927A CN106776101B CN 106776101 B CN106776101 B CN 106776101B CN 201710113927 A CN201710113927 A CN 201710113927A CN 106776101 B CN106776101 B CN 106776101B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
- G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
- G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Debugging And Monitoring (AREA)
Abstract
The application provides a watchdog circuit and a signal processing circuit, which are used for solving the problem that in the prior art, a program of a processor connected with the watchdog circuit is difficult to simulate or upgrade. The watchdog circuit comprises: the reset signal circuit is used for generating a reset signal, and the reset signal is used for resetting a processor connected with the watchdog circuit; the input end of the analog switch is connected to the output end of the reset signal circuit, the output end of the analog switch is connected to the reset signal input end of the processor, and the analog switch is used for switching on or switching off a passage between the output end of the reset signal circuit and the processor.
Description
Technical Field
The invention relates to the technical field of digital signal processing, in particular to a watchdog circuit and a signal processing circuit.
Background
In the field of digital signals, when an abnormality occurs in a processor program, a reset signal output by a watchdog circuit is generally used to passively reset and re-operate the processor, and in order to avoid interference of the watchdog circuit when the processor normally operates, the processor is generally made to perform a watchdog feeding operation on the watchdog at a time interval smaller than a period of the reset signal, so that the watchdog circuit turns off a period reset function, that is, does not output the reset signal.
However, when the program of the processor is simulated or upgraded, the simulation and upgrade time is generally longer than the period of the reset signal, so the processor cannot perform the watchdog feeding operation on the watchdog at a time interval smaller than the reset period, and the watchdog circuit still outputs the reset signal, and the reset signal interrupts the simulation or upgrade process of the program of the processor. The prior art has a problem in that it is difficult to simulate or upgrade a program of a processor to which a watchdog circuit is connected.
Disclosure of Invention
The application provides a watchdog circuit and a signal processing circuit, which are used for solving the problem that in the prior art, a program of a processor connected with the watchdog circuit is difficult to simulate or upgrade.
A first aspect of an embodiment of the present invention provides a watchdog circuit, including:
the reset signal circuit is used for generating a reset signal, and the reset signal is used for resetting a processor connected with the watchdog circuit;
the input end of the analog switch is connected to the output end of the reset signal circuit, the output end of the analog switch is connected to the reset signal input end of the processor, and the analog switch is used for switching on or switching off a passage between the output end of the reset signal circuit and the processor.
Optionally, the analog switch includes: a normally closed NC pin as the input end of the analog switch; a common COM pin as the output of the analog switch; a power VCC pin for connecting with a power supply; the electric wire grounding GND pin is used for grounding; a normally open NO pin suspended; a SEL pin is selected and used for controlling the connection or disconnection of a passage between the NC pin and the COM pin; when the SEL pin and the VCC pin are disconnected, the path between the NC pin and the COM pin is turned on, and the reset signal is sent to the reset signal input terminal of the processor via the NC pin and the COM pin; when the SEL pin and the VCC pin are shorted, the path between the NC pin and the COM pin is opened.
Optionally, the analog switch further includes: a first pin leading from the VCC pin; and a second pin leading from the SEL pin; when the first pin and the second pin are disconnected, a passage between the NC pin and the COM pin is conducted, and the reset signal is sent to the reset signal input end of the processor through the NC pin and the COM pin; and when the first pin and the second pin are short-circuited, the passage between the NC pin and the COM pin is disconnected.
Optionally, the watchdog circuit further includes: the first end of the checking socket is connected with the VCC pin, and the second end of the checking socket is connected with the SEL pin; when the first end and the second end are disconnected, a passage between the NC pin and the COM pin is conducted, and the reset signal is sent to a reset signal input end of the processor through the NC pin and the COM pin; and when the first end and the second end are short-circuited, a passage between the NC pin and the COM pin is disconnected.
Optionally, the inspection socket further includes: the third end and the fourth end are respectively connected with a VCC pin and a SEL pin of the second analog switch; the second analog switch is an analog switch of a second watchdog circuit and is used for switching on or switching off a passage between the output end of a reset signal circuit of the second watchdog circuit and the processor; when the third end and the fourth end are disconnected, a passage between the NC pin of the second analog switch and the COM pin of the second analog switch is conducted, and a reset signal generated by a reset signal circuit of the second watchdog circuit is sent to the processor through the NC pin of the second analog switch and the COM pin of the second analog switch; and when the third end and the fourth end are short-circuited, a path between the NC pin of the second watchdog circuit and the COM pin of the second watchdog circuit is disconnected.
Optionally, the inspection socket further includes: a first extension end and a second extension end; the first expansion end and the second expansion end are respectively connected with a first pin and a second pin of the processor and are used for switching on or switching off a passage between the first pin and the second pin.
Optionally, the watchdog circuit further includes: the chip selection CS pin is used for receiving the chip selection CS signal sent by the processor; a serial input SI pin for receiving a serial input SI signal sent by the processor; a serial output SO pin for outputting a serial output SO signal to the processor; the serial clock input SCK pin is used for receiving a serial clock SCK signal output by the processor; the CS pin, the SI pin, the SO pin and the SCK pin are serial peripheral interface SPI.
A second aspect of an embodiment of the present invention provides a signal processing circuit, including:
a processor for performing signal processing;
a clock circuit for providing an operating clock signal for the processor;
a memory for providing storage space for the processor;
and, a watchdog circuit according to the first aspect or any of the alternatives of the first aspect, for providing a reset signal for the processor;
leading out a first contact pin from a VCC pin of an analog switch of the watchdog circuit, and connecting the first contact pin to a first end of an extra-cavity checking socket by using a wire; a second pin is led out from the SEL pin of the analog switch and connected to the second end of the out-of-cavity inspection socket using a wire.
Optionally, the signal processing circuit further includes a jumper cap for: and shorting the first pin and the second pin when simulating or upgrading the program of the processor so as to disconnect the passage between the NC pin and the COM pin.
Optionally, the watchdog circuit further comprises a connection cable for: when the program of the processor is simulated or upgraded, the first pin is connected with the second pin, so that a passage between the NC pin and the COM pin is disconnected.
One or more technical solutions provided in the embodiments of the present application at least have the following technical effects or advantages:
in the technical scheme of the embodiment of the invention, the passage between the NC pin and the COM pin can be controlled to be disconnected or connected by switching on or switching off the passage between the SEL pin and the VCC pin, so that the passage between the NC pin and the COM pin is disconnected or connected. Therefore, when the processor program is simulated or upgraded, the SEL pin and the VCC pin are short-circuited, so that the input of a reset signal of the watchdog circuit to the processor can be stopped, the simulation or upgrade of the processor program is normally performed, the periodic reset function of closing the watchdog circuit when the processor program is simulated or upgraded is realized, and the problem that the program of the processor connected with the watchdog circuit is difficult to simulate or upgrade in the prior art is solved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a watchdog circuit according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of an analog switch 120 according to an embodiment of the present application;
FIG. 3 is a schematic diagram of another configuration of a watchdog circuit according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a signal processing circuit according to an embodiment of the present disclosure;
fig. 5 is another schematic structural diagram of a signal processing circuit in an embodiment of the present application.
Detailed Description
The following detailed description of the technical solutions of the present application will be made with reference to the accompanying drawings and specific embodiments, and it should be understood that the specific features of the embodiments and embodiments of the present application are detailed descriptions of the technical solutions of the present application, and not limiting the technical solutions of the present application, and the technical features of the embodiments and embodiments of the present application may be combined with each other without conflict.
Example 1
Referring to fig. 1, the watchdog circuit 10 includes a reset signal circuit 110 and an analog switch 120, and an input terminal of the analog switch 120 is connected to an output terminal of the reset signal circuit 110, and an output terminal of the analog switch 120 is connected to a reset signal input terminal of the processor 20. When the analog switch 120 is in the on state, the reset signal generated by the reset signal circuit 110 is transmitted to the processor 20 via the analog switch 120, and the reset signal resets the processor 20.
The analog switch 120 specifically includes: a Normally-closed (NC) pin, a Common (COM) pin, a power (Volt Current Condenser, VCC) pin, a Ground (GND) pin, a Normally-open (NO) pin, and a Select (SEL) pin. The NC pin is an input end of the analog switch 120, and is connected to an output end of the reset signal circuit 110; the COM pin is an output end of the analog switch 120 and is connected to a reset signal input end of the processor 20; the VCC pin is used for connecting electricity; the GND pin is used for grounding; the NO pin is suspended; the SEL pin is used to control the passage between the NC pin and the COM pin to be turned on or off.
The specific method for controlling the on or off of the passage between the NC pin and the COM pin by the SEL pin is as follows:
when the path between the SEL pin and the VCC pin is open, the SEL pin is low, and the path between the NC pin and the COM pin is on, i.e., the analog switch 120 is in an on state, and a reset signal is sent to the reset signal input terminal of the processor 20 via the NC pin and the COM pin; when the SEL pin is shorted to the VCC pin, the SEL pin is high and the path between the NC pin and the COM pin is open.
In the scheme, the channel between the NC pin and the COM pin can be controlled to be disconnected or connected by switching on or switching off the channel between the SEL pin and the VCC pin, so that the channel between the NC pin and the COM pin is disconnected or connected. Therefore, when the processor 20 program is simulated or upgraded, the input of the reset signal of the watchdog circuit 10 to the processor 20 can be stopped by shorting the SEL pin and the VCC pin, so that the simulation or upgrade of the processor 20 program is performed normally, the periodic reset function of closing the watchdog circuit 10 when the processor 20 program is simulated or upgraded is realized, and the problem that the program of the processor 20 connected with the watchdog circuit 10 is difficult to simulate or upgrade in the prior art is solved.
As an alternative, referring to fig. 2, the analog switch 120 further includes: a first pin 121 leading from the VCC pin and a second pin 122 leading from the SEL pin. The control of the on or off of the path between the NC pin and the COM pin can be controlled by opening or connecting the path between the first pin 121 and the second pin 122.
Specifically, when the path between the first pin 121 and the second pin 122 is open, the SEL pin is at low level, and the path between the NC pin and the COM pin is on, i.e. the analog switch 120 is in a conductive state, and the reset signal is sent to the reset signal input end of the processor 20 through the NC pin and the COM pin; when the path between the first pin 121 and the second pin 122 is short, the SEL pin is high, and the path between the NC pin and the COM pin is open.
In this manner, the path between the NC pin and the COM pin can be controlled to be turned off or on by turning on or off the path between the first pin 121 and the second pin 122, so that the path between the NC pin and the COM pin is turned off or on, and the periodic reset function of the watchdog circuit 10 is turned on or off more conveniently and rapidly.
As an alternative way, when the program of the processor 20 is simulated or upgraded, the jumper cap is adopted to short-circuit the first pin 121 and the second pin 122, so that the path between the NC pin and the COM pin is disconnected, and then the periodic reset function of the watchdog circuit 10 is closed, and the simulation or upgrade of the program of the processor 20 can be normally performed; when the emulation or upgrade of the program of the processor 20 is completed, the periodic reset function of the watchdog circuit 10 can be restored by removing the jumper cap. In this way, the start or stop of the periodic reset function of the watchdog circuit 10 can be controlled more conveniently.
As an alternative, referring to fig. 3, the watchdog circuit 10 further comprises an inspection socket 30, the inspection socket 30 being arranged outside the cavity of the device in which the watchdog circuit 10 is located. Wherein a first end 310 of the check socket 30 is connected to the VCC pin of the analog switch 120 and a second end 320 of the check socket 30 is connected to the SEL pin of the analog switch 120. The control of the on or off of the path between the NC pin and the COM pin may be controlled by opening or connecting the path between the first end 310 and the second end 320.
Specifically, when the path between the first end 310 and the second end 320 is open, the SEL pin is at low level, and the path between the NC pin and the COM pin is on, i.e. the analog switch 120 is in a conductive state, and the reset signal is sent to the reset signal input end of the processor 20 through the NC pin and the COM pin; when the path between the first terminal 310 and the second terminal 320 is short, the SEL pin is high, and the path between the NC pin and the COM pin is open.
When the program of the processor 20 is simulated or upgraded, the first end 310 and the second end 320 of the checking socket 30 are short-circuited through the cable, so that a passage between an NC pin and a COM pin is disconnected, and then the periodic reset function of the watchdog circuit 10 is closed, and the simulation or upgrading of the program of the processor 20 can be normally performed; when the emulation or upgrade of the program of the processor 20 is completed, the periodic reset function of the watchdog circuit 10 can be restored by removing the cable.
In the method, the vehicle detection socket 130 is arranged outside the cavity of the equipment where the watchdog circuit 10 is arranged, and the output of the analog switch 120 can be controlled to select or not select the reset signal through the external detection socket 130 in the cavity of the equipment, namely, the periodic reset function of the watchdog circuit 10 is controlled to be started or stopped, so that the operation of controlling the periodic reset function of the watchdog circuit 10 to be started or stopped is more convenient; meanwhile, unlike the mode that the control circuit is arranged in the cavity to control the on or off of the periodic reset function of the watchdog circuit 10, the inspection socket 30 in the mode is arranged outside the cavity of the equipment where the watchdog circuit 10 is arranged, so that the structure of the watchdog circuit 10 can be simplified, and the volume of the cavity of the equipment where the watchdog circuit 10 is arranged can be reduced.
As an alternative, the number of the ports of the inspection socket 30 may be two or more in the embodiment of the present invention, which is not particularly limited; the number of watchdog circuits connected to the inspection socket 30 in the embodiment of the present invention may be one or two or more, and the embodiment of the present invention is not particularly limited.
For example, referring to fig. 3, the inspection socket 30 further includes third and fourth terminals 330 and 340, respectively connected to the VCC pin of the second analog switch and the SEL pin of the second analog switch. The second analog switch is an analog switch of the second watchdog circuit and is used for switching on or switching off a passage between the output end of the reset signal circuit of the second watchdog circuit and the processor.
When the path between the SEL pin of the second analog switch and the VCC pin of the second analog switch is open, the SEL pin of the second analog switch is at a low level, the path between the NC pin of the second analog switch and the COM pin of the second analog switch is on, and a reset signal generated by the reset signal circuit of the second watchdog circuit is sent to the processor 20 via the NC pin of the second analog switch and the COM pin of the second analog switch; when the SEL pin of the second analog switch is short-circuited with the VCC pin of the second analog switch, the SEL pin of the second analog switch is high, and a path between the NC pin of the second analog switch and the COM pin of the second analog switch is disconnected.
By the mode, the inspection socket 30 can simultaneously control the on and off of the periodic reset functions of a plurality of watchdog circuits, and the universality of the inspection socket 30 is improved.
Alternatively, in an embodiment of the present invention, the inspection receptacle 30 further includes a first extension end 350 and a second extension end 360. The first extension terminal 350 and the second extension terminal 360 are respectively connected to a first pin and a second pin of the processor 20, and are used for switching on or switching off a path between the first pin and the second pin.
Specifically, when the path between the first expansion end 350 and the second expansion end 360 is open, the path between the first pin and the second pin is open; when the path between the first extension terminal 350 and the second extension terminal 360 is a short circuit, the path between the first pin and the second pin is a short circuit.
By the mode, the inspection socket 30 can also control the circuit state in the processor 20, enrich the functions of the inspection socket 30 and improve the universality of the inspection socket 30.
As an alternative, referring to fig. 4, the watchdog circuit 10 further comprises: a Chip Select (CS) pin for receiving a CS signal for Chip Select sent by the processor 20; a Serial Input (SI) pin for receiving a Serial Input SI signal transmitted from the processor 20; a Serial Output (SO) pin for outputting a Serial Output SO signal to the processor 20; a Serial Clock input (SCK) pin for receiving a Serial Clock SCK signal output from the processor 20. The CS pin, the SI pin, the SO pin, and the SCK pin are all serial peripheral interfaces (Serial Peripheral Interface, SPI).
Wherein the CS signal is a watchdog signal of the processor 20 to the watchdog circuit 10. When the CS signal is low, the processor 20 feeds the watchdog circuit 10, and after the feeding is completed, the CS signal is restored to high. During a reset period after the watchdog circuit 10 is fed by the processor 20, the watchdog circuit 10 no longer outputs a reset signal, i.e. the periodic reset function of the watchdog circuit 10 is turned off.
The periodic reset function of closing the watchdog circuit 10 is realized by the method, so that the simulation or upgrading of the program of the processor 20 is smoothly carried out.
Example two
A second embodiment of the present invention provides a signal processing circuit 40, referring to fig. 5, the circuit includes: processor 410, clock circuit 420, memory 430, and watchdog circuit 440 in accordance with one embodiment of the present invention.
Wherein the processor 410 is configured to perform signal processing; clock circuit 420 provides an operating clock signal to processor 410; a memory 430 for providing storage space for the processor 410; watchdog circuit 440 is operative to provide reset signals to processor 410.
A first pin 441 leads from the VCC pin of the watchdog circuit 440 and is connected to the first end 510 of the out-of-cavity inspection socket 50 using a wire; a second pin 442 from the SEL pin of the analog switch and is connected to the second end 520 of the extra-cavity inspection socket 50 using a wire.
When the program of the processor 410 is simulated or upgraded, the first pin 441 and the second pin 442 can be shorted by the jumper cap, so that the VCC pin and the SEL pin are shorted, and a path between the NC pin and the COM pin is disconnected, thereby closing the periodic reset function of the watchdog circuit 440. After the emulation or upgrade of the program of the processor 410 is completed, the periodic reset function of the watchdog circuit 10 may be restored by removing the jumper cap.
When conditions do not allow for direct operation of the signal processing circuit 40, a cable may be used to connect the first end 510 and the second end 520 of the extra-cavity inspection socket 50 such that the VCC pin and the SEL pin are shorted, thereby opening the path between the NC pin and the COM pin, i.e., closing the periodic reset function of the watchdog circuit 440. After the simulation or upgrade of the program of the processor 410 is completed, the periodic reset function of the watchdog circuit 440 may be restored by removing the cable.
In the above-mentioned scheme, two implementation methods for closing the periodic reset function of the watchdog circuit 440 are provided, which can not only realize the periodic reset function of the watchdog circuit 440 by changing the circuit connection relationship inside the signal processing circuit 40, but also realize the periodic reset function of the watchdog circuit 440 by the external checking socket 50, and the operation is simple. The periodic reset function of the watchdog circuit 440 can still be closed when the program of the processor 410 is simulated or upgraded, and the problem that the program of the processor connected with the watchdog circuit is difficult to simulate or upgrade in the prior art is solved.
The above specific implementation of the watchdog circuit 440 may refer to the implementation of the watchdog circuit 10 in the first embodiment of the present invention, and the detailed description of this embodiment is omitted.
One or more technical solutions provided in the embodiments of the present application at least have the following technical effects or advantages:
1. the opening or closing of the path between the NC pin and the COM pin can be controlled by opening or closing the path between the SEL pin and the VCC pin. Therefore, when the processor program is simulated or upgraded, the input of the reset signal of the watchdog circuit to the processor can be stopped by shorting the SEL pin and the VCC pin, so that the simulation or upgrade of the processor program is normally performed. The method solves the problem that the program of the processor connected with the watchdog circuit is difficult to simulate or upgrade in the prior art.
2. The jumper cap is adopted to short-circuit the first contact pin and the second contact pin, so that a passage between the NC pin and the COM pin is disconnected, namely, the periodic reset function of closing the watchdog circuit is realized, and further, the periodic reset function of controlling the watchdog circuit is more convenient to open or close.
3. The car checking socket is arranged outside the cavity of the equipment where the watchdog circuit is arranged, and can control the analog switch to select or not select the output of the reset signal through the outer checking seat of the cavity of the equipment, namely, the turning on or off of the periodic reset function of the watchdog circuit is controlled, so that the operation of controlling the turning on or off of the periodic reset function of the watchdog circuit is more convenient.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims and the equivalents thereof, the present application is intended to cover such modifications and variations.
Claims (8)
1. A watchdog circuit, comprising:
the reset signal circuit is used for generating a reset signal, and the reset signal is used for resetting a processor connected with the watchdog circuit;
the input end of the analog switch is connected to the output end of the reset signal circuit, the output end of the analog switch is connected to the reset signal input end of the processor, and the analog switch is used for switching on or switching off a passage between the output end of the reset signal circuit and the processor;
the analog switch includes:
a normally closed NC pin as the input end of the analog switch;
a common COM pin as the output of the analog switch;
a power VCC pin for connecting with a power supply;
the electric wire grounding GND pin is used for grounding;
a normally open NO pin suspended;
a SEL pin is selected and used for controlling the connection or disconnection of a passage between the NC pin and the COM pin;
when the SEL pin and the VCC pin are disconnected, the path between the NC pin and the COM pin is turned on, and the reset signal is sent to the reset signal input terminal of the processor via the NC pin and the COM pin; when the SEL pin and the VCC pin are short-circuited, a passage between the NC pin and the COM pin is disconnected;
the watchdog circuit further comprises an inspection socket;
the inspection socket includes: a first extension end and a second extension end;
the first expansion end and the second expansion end are respectively connected with a first pin and a second pin of the processor and are used for switching on or switching off a passage between the first pin and the second pin.
2. The watchdog circuit of claim 1, wherein the analog switch further comprises:
a first pin leading from the VCC pin;
and a second pin leading from the SEL pin;
when the first pin and the second pin are disconnected, a passage between the NC pin and the COM pin is conducted, and the reset signal is sent to the reset signal input end of the processor through the NC pin and the COM pin; and when the first pin and the second pin are short-circuited, the passage between the NC pin and the COM pin is disconnected.
3. The watchdog circuit of claim 1 or 2, wherein the inspection socket further comprises:
a first end of the checking socket is connected with the VCC pin, and a second end of the checking socket is connected with the SEL pin; when the first end and the second end are disconnected, a passage between the NC pin and the COM pin is conducted, and the reset signal is sent to a reset signal input end of the processor through the NC pin and the COM pin; and when the first end and the second end are short-circuited, a passage between the NC pin and the COM pin is disconnected.
4. A watchdog circuit according to claim 3, wherein the inspection socket further comprises:
the third end and the fourth end are respectively connected with a VCC pin and a SEL pin of the second analog switch; the second analog switch is an analog switch of a second watchdog circuit and is used for switching on or switching off a passage between the output end of a reset signal circuit of the second watchdog circuit and the processor;
when the third end and the fourth end are disconnected, a passage between the NC pin of the second analog switch and the COM pin of the second analog switch is conducted, and a reset signal generated by a reset signal circuit of the second watchdog circuit is sent to the processor through the NC pin of the second analog switch and the COM pin of the second analog switch; and when the third end and the fourth end are short-circuited, a path between the NC pin of the second watchdog circuit and the COM pin of the second watchdog circuit is disconnected.
5. A watchdog circuit according to claim 3, further comprising:
the chip selection CS pin is used for receiving the chip selection CS signal sent by the processor;
a serial input SI pin for receiving a serial input SI signal sent by the processor;
a serial output SO pin for outputting a serial output SO signal to the processor;
the serial clock input SCK pin is used for receiving a serial clock SCK signal output by the processor;
the CS pin, the SI pin, the SO pin and the SCK pin are serial peripheral interface SPI.
6. A signal processing circuit, comprising:
a processor for performing signal processing;
a clock circuit for providing an operating clock signal for the processor;
a memory for providing storage space for the processor;
and a watchdog circuit according to any of claims 1 to 5 for providing a reset signal for the processor;
leading out a first contact pin from a VCC pin of an analog switch of the watchdog circuit, and connecting the first contact pin to a first end of an extra-cavity checking socket by using a wire; a second pin is led out from the SEL pin of the analog switch and connected to the second end of the out-of-cavity inspection socket using a wire.
7. The signal processing circuit of claim 6, further comprising a jumper cap for: and when the program of the processor is simulated or upgraded, shorting the first pin and the second pin so as to disconnect a passage between the NC pin and the COM pin.
8. The signal processing circuit of claim 6, wherein the watchdog circuit further comprises a connection cable for: when the program of the processor is simulated or upgraded, the first pin is connected with the second pin, so that a passage between the NC pin and the COM pin is disconnected.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710113927.XA CN106776101B (en) | 2017-02-28 | 2017-02-28 | Watchdog circuit and signal processing circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710113927.XA CN106776101B (en) | 2017-02-28 | 2017-02-28 | Watchdog circuit and signal processing circuit |
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| CN106776101A CN106776101A (en) | 2017-05-31 |
| CN106776101B true CN106776101B (en) | 2023-07-21 |
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| CN109274608A (en) * | 2018-11-13 | 2019-01-25 | 浙江恒捷通信科技有限公司 | A kind of intelligent acess digital SPC exchange |
| CN111090323A (en) * | 2019-12-24 | 2020-05-01 | 上海移远通信科技有限公司 | Power-off protection circuit of control chip, software upgrading circuit and control system |
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| CN106776101A (en) | 2017-05-31 |
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