CN111090323A - Power-off protection circuit of control chip, software upgrading circuit and control system - Google Patents
Power-off protection circuit of control chip, software upgrading circuit and control system Download PDFInfo
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- CN111090323A CN111090323A CN201911347787.8A CN201911347787A CN111090323A CN 111090323 A CN111090323 A CN 111090323A CN 201911347787 A CN201911347787 A CN 201911347787A CN 111090323 A CN111090323 A CN 111090323A
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
- G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
- G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
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- G06—COMPUTING; CALCULATING OR COUNTING
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Abstract
The invention discloses a power-off protection circuit of a control chip, a software upgrading circuit and a control system, wherein the power-off protection circuit comprises a hardware watchdog chip, a first control circuit, a second control circuit and a first filter capacitor; when the hardware watchdog chip can receive the periodic signal, generating a continuous high-level signal; the first control circuit is used for supplying power to a power pin of the control chip, and the second control circuit does not work; when the hardware watchdog chip cannot receive the periodic signal output by the control chip, a low level signal is generated; the first control circuit does not work, and the control chip is in a power-off state; the second control circuit is used for discharging the electric energy in the first filter capacitor. The invention adopts a power-off reset mode to process the fault condition of the MCU, and can discharge the electric energy in the filter capacitor in time to ensure that the MCU is effectively reset and restarted; software upgrading can be carried out on the MCU at any time, maintenance cost is reduced, and operation efficiency and convenience are improved.
Description
Technical Field
The invention relates to the technical field of circuit design, in particular to a power-off protection circuit of a control chip, a software upgrading circuit and a control system.
Background
The hardware watchdog chip mainly plays a monitoring role in an MCU (microcontroller) circuit system, and is used for regularly checking the working condition of the MCU and sending a reset restart signal to the MCU once an error occurs.
As shown in fig. 1, the watchdog reset circuit U1 in the MCU circuit system is directly connected in communication with the MCU (i.e., U2), where C1 and C2 are the respective filter capacitors, and a is the power input. Under a normal working state, the hardware watchdog chip U1 needs the MCU to continuously input continuous square wave periodic signals (commonly called 'dog feeding' signals) to a WDI pin (square wave signal input pin) of the external watchdog reset circuit U1 through a GPIO (general purpose input/output) pin to ensure the normal operation of the hardware watchdog chip U1, so that the hardware watchdog chip U1 can default that the MCU is in a normal working state and can not output reset signals to the MCU. When the MCU crashes or otherwise fails, a continuous square wave periodic signal (i.e., an abnormal dog feeding signal) cannot be continuously and normally input to the hardware watchdog chip U1, at this time, the hardware watchdog chip U1 outputs a reset signal to the reset signal output pin M1_ RST of the MCU through the M _ RST pin, so as to reset the MCU circuit system, and the MCU is reset and then restarted to operate, so that the whole circuit system is restored to a normal operating state. However, the conventional circuit structure has the following disadvantages:
(1) the hardware watchdog chip U1 mainly generates a reset signal to reset the MCU circuit system, and the MCU does not consume electric energy in the reset process; however, the power stored in the filter capacitor is not consumed immediately and is consumed by parasitic impedance in the circuit for a long time, so that the reset signal generated in this case does not necessarily enable an effective reset restart of the MCU.
(2) In the normal operation process of the existing hardware watchdog chip U1, a maintainer cannot perform independent software upgrading operation on the MCU. Once the MCU is upgraded, the MCU stops inputting square wave periodic signals to the hardware watchdog chip U1, the hardware watchdog chip U1 judges that the MCU is in a dead halt state or other fault states, and the standing horse outputs a reset signal to the MCU reset pin to perform reset operation, so that the MCU of the ongoing software upgrade fails. The existing solution is as follows: the MCU is disassembled to carry out independent software upgrading operation, however, the disassembling and assembling process is complex, the upgrading efficiency is reduced, and the maintenance cost is increased. Moreover, many times, the MCU is permanently soldered in the whole circuit device, and the circuit device cannot be disassembled, so that if the MCU software must be upgraded, the whole system circuit must be upgraded, which may increase the cost of the device.
Disclosure of Invention
The invention aims to overcome the defects that the circuit structure in the prior art cannot ensure that the MCU is effectively reset and restarted, and software upgrading operation is difficult, and the like, and aims to provide a power-off protection circuit of a control chip, a software upgrading circuit and a control system.
The invention solves the technical problems through the following technical scheme:
the invention provides a power-off protection circuit of a control chip, which comprises a hardware watchdog chip, a first control circuit, a second control circuit and a first filter capacitor, wherein the hardware watchdog chip is connected with the first control circuit;
the first end of the first control circuit is electrically connected with a power supply input end, the second end of the first control circuit is electrically connected with a reset signal output pin of the hardware watchdog chip, and the third end of the first control circuit is electrically connected with a power supply pin of the control chip;
the first end of the second control circuit is electrically connected with the power input end, the second end of the second control circuit is respectively electrically connected with the power pin of the control chip and one end of the first filter capacitor, and the other end of the first filter capacitor is grounded;
the periodic signal input end of the hardware watchdog chip is electrically connected with the periodic signal output end of the control chip;
when the hardware watchdog chip can receive the periodic signal output by the control chip, a reset signal output pin of the hardware watchdog chip generates a high-level signal;
the first control circuit is used for supplying power to a power supply pin of the control chip according to the high level signal, the first filter capacitor is used for storing electric energy, and the second control circuit does not work;
when the hardware watchdog chip cannot receive the periodic signal output by the control chip, a reset signal output pin of the hardware watchdog chip generates a low-level signal;
the first control circuit does not work, and the control chip is in a power-off state;
the second control circuit is used for discharging the electric energy in the first filter capacitor.
Preferably, the first control circuit includes a first transistor and a second transistor;
the first transistor is electrically connected with the second transistor, the power supply input end and a power supply pin of the control chip respectively;
the second transistor is electrically connected with a reset signal output pin of the hardware watchdog chip.
Preferably, the first transistor is a PMOS transistor (P-channel MOS transistor), and the second transistor is an NPN-type transistor (a kind of transistor);
the first control circuit further comprises a first resistor and a second resistor;
the source electrode of the first transistor is electrically connected with the power supply input end, the drain electrode of the first transistor is electrically connected with the power supply pin of the control chip, and the grid electrode of the first transistor is electrically connected with the collector electrode of the second transistor;
one end of the first resistor is electrically connected with a reset signal output pin of the hardware watchdog chip, the other end of the first resistor is electrically connected with one end of the second resistor and a base electrode of the second transistor respectively, and the other end of the second resistor and an emitting electrode of the second transistor are grounded.
Preferably, the second control circuit includes a third transistor;
the transistor is respectively and electrically connected with the power input end, the power pin of the control chip and the grounding end.
Preferably, the power-off protection circuit further comprises a third resistor;
the third transistor is an NMOS (N-channel MOS) transistor; the second control circuit further comprises a fourth resistor;
one end of the third resistor is electrically connected with the power supply input end and the source electrode of the first transistor respectively, the other end of the third resistor is electrically connected with the grid electrode of the first transistor and the grid electrode of the third transistor respectively, the drain electrode of the third transistor is electrically connected with one end of the fourth resistor, the other end of the fourth resistor is electrically connected with the power supply pin of the control chip, and the source electrode of the third transistor is grounded.
Preferably, the power-off protection circuit further comprises a second filter capacitor;
one end of the second filter capacitor is electrically connected with the power input end and the power input pin of the hardware watchdog chip respectively, and the other end of the second filter capacitor is grounded; and/or the presence of a gas in the gas,
the periodic signal comprises a square wave periodic signal.
Preferably, after the reset signal output pin of the hardware watchdog chip generates the set time of the low level signal, the high level signal is automatically generated to trigger the control chip to perform reset restart.
The invention also provides a software upgrading circuit of the control chip, which comprises the power-off protection circuit of the control chip and a connecting unit;
one end of the connecting unit is electrically connected with the power input end, and the other end of the connecting unit is electrically connected with a power pin of the control chip;
when the software upgrading of the control chip is not needed, the connection unit is in a disconnected state; when software upgrading needs to be carried out on the control chip, the control chip is used for controlling the connection unit to be closed.
Preferably, the connection unit includes a timing control circuit;
wherein the timing control circuit automatically opens after a set time of closure.
The invention also provides a control system, which comprises the software upgrading circuit of the control chip and the control chip.
Preferably, the control chip comprises a microcontroller.
The positive progress effects of the invention are as follows:
the power-off protection circuit comprises two control circuits, so that when the MCU is in a normal working state, the first control circuit normally supplies power to the MCU, and the second control circuit does not work; when the MCU is in an abnormal working state, the first control circuit does not work, the MCU is powered off, and the second control circuit discharges the electric energy in the filter capacitor, so that the fault condition of the MCU is processed in a power-off reset mode, and meanwhile, the electric energy in the filter capacitor can be discharged in time to ensure that the MCU is effectively reset and restarted; in addition, by additionally arranging the timing control circuit in the power-off protection circuit, software upgrading can be carried out on the MCU by maintenance personnel at any time under the conditions of no disassembly, no replacement and no power-off, and the MCU cannot be upgraded normally due to the reset signal generated by the hardware watchdog circuit, so that the problem that independent software upgrading operation cannot be carried out on the MCU currently is effectively solved, the maintenance cost is reduced, and the power-off protection circuit has the advantages of rapidness and convenience in operation.
Drawings
Fig. 1 is a schematic diagram of a reset circuit of a control chip in a conventional control system.
Fig. 2 is a schematic structural diagram of a power-off protection circuit of a control chip according to embodiment 1 of the present invention.
Fig. 3 is a schematic circuit structure diagram of a power-off protection circuit of a control chip according to embodiment 1 of the present invention.
Fig. 4 is a schematic structural diagram of a software upgrade circuit of a control chip according to embodiment 2 of the present invention.
Fig. 5 is a first circuit schematic diagram of a software upgrading circuit of a control chip according to embodiment 2 of the present invention.
Fig. 6 is a second circuit schematic diagram of the software upgrading circuit of the control chip according to embodiment 2 of the present invention.
Fig. 7 is a schematic structural diagram of a control system according to embodiment 3 of the present invention.
Detailed Description
The invention is further illustrated by the following examples, which are not intended to limit the scope of the invention.
Example 1
As shown in fig. 2, the power-off protection circuit of the control chip of this embodiment includes a hardware watchdog chip U1, a first control circuit 1, a second control circuit 2, and a first filter capacitor C1.
A first end of the first control circuit 1 is electrically connected with a power supply input end A, a second end of the first control circuit 1 is electrically connected with a reset signal output pin of the hardware watchdog chip U1, and a third end of the first control circuit 1 is electrically connected with a power supply pin of the control chip;
the first end of the second control circuit 2 is electrically connected to the power input end a, the second end of the second control circuit 2 is electrically connected to the power pin of the control chip and one end of the first filter capacitor C1, respectively, and the other end of the first filter capacitor C1 is grounded.
The periodic signal input end of the hardware watchdog chip U1 is electrically connected with the periodic signal output end of the control chip U2;
the periodic signal includes, but is not limited to, a square wave periodic signal.
When the hardware watchdog chip U1 can receive the periodic signal output by the control chip, the reset signal output pin of the hardware watchdog chip U1 generates a high level signal;
the first control circuit 1 is used for supplying power to a power supply pin of the control chip according to a high level signal, the first filter capacitor C1 is used for storing electric energy, and the second control circuit 2 does not work;
when the hardware watchdog chip U1 cannot receive the periodic signal output by the control chip, the reset signal output pin of the hardware watchdog chip U1 generates a low level signal;
wherein, the first control circuit 1 does not work, and the control chip is in a power-off state;
the second control circuit 2 is used to drain the electric energy in the first filter capacitor C1.
In addition, after the reset signal output pin of the hardware watchdog chip U1 generates the set time of the low level signal, the high level signal is automatically generated to trigger the control chip to reset and restart.
Specifically, as shown in fig. 3, the first control circuit 1 includes a first transistor Q1 and a second transistor Q2;
the first transistor Q1 is electrically connected to the second transistor Q2, the power input terminal a, and the power pin VCC of the control chip U2, respectively.
The second transistor Q2 is electrically connected to the reset signal output pin M _ RST of the hardware watchdog chip U1.
Preferably, the first transistor Q1 is a PMOS transistor, and the second transistor Q2 is an NPN transistor;
the first control circuit 1 further comprises a first resistor R1 and a second resistor R2;
the source of the first transistor Q1 is electrically connected with the power input terminal a, the drain of the first transistor Q1 is electrically connected with the power pin VCC of the control chip U2, and the gate of the first transistor Q1 is electrically connected with the collector of the second transistor Q2;
one end of the first resistor R1 is electrically connected to the reset signal output pin M _ RST of the hardware watchdog chip U1, the other end of the first resistor R1 is electrically connected to one end of the second resistor R2 and the base of the second transistor Q2, and the other end of the second resistor R2 and the emitter of the second transistor Q2 are both grounded.
The IN pin of the hardware watchdog chip U1 is a chip power input pin, WDI is a square wave periodic signal input pin, the reset signal output pin M _ RST is set to a high level by default, and GND is a ground pin.
The second control circuit 2 includes a third transistor Q3.
The transistor is electrically connected with the power input end A, a power pin VCC of the control chip U2 and a ground end respectively.
Preferably, the third transistor Q3 is an NMOS transistor;
the power-off protection circuit of the present embodiment further includes a third resistor R3, and the second control circuit 2 further includes a fourth resistor R4. Specifically, one end of the third resistor R3 is electrically connected to the power input terminal a and the source of the first transistor Q1, the other end of the third resistor R3 is electrically connected to the gate of the first transistor Q1 and the gate of the third transistor Q3, the drain of the third transistor Q3 is electrically connected to one end of the fourth resistor R4, the other end of the fourth resistor R4 is electrically connected to the power supply pin VCC of the control chip U2, and the source of the third transistor Q3 is grounded.
The first resistor R1, the second resistor R2, and the third resistor R3 are all common resistors, the fourth resistor R4 is a power resistor (relatively small resistance) which can be set at about 100 ohms, the third transistor Q3 is an NMOS transistor, and can pass a large current to discharge the fourth resistor, which is equivalent to a discharge resistor.
The power-off protection circuit further comprises a second filter capacitor C2;
one end of the second filter capacitor C2 is electrically connected to the power input terminal a and the power input pin of the hardware watchdog chip U1, respectively, and the other end of the second filter capacitor C2 is grounded.
The working principle of the power-off protection circuit of the embodiment is as follows:
when the control chip U2 is in a normal working state, the GPIO pin is controlled to continuously output a square wave periodic signal to the WDI pin of the hardware watchdog chip U1, at the moment, the M _ RST pin continuously outputs a high level signal, the first transistor Q1 and the second transistor Q2 are both in an open working state, the power input end A supplies power normally to the control chip U2 from the first transistor Q1, the Q3 is in a closed state, the fourth resistor R4 does not consume electric energy, the first filter capacitor C1 stores the electric energy, and voltage fluctuation is prevented.
When the power supply input by the power supply input end A is abnormally interrupted or the control chip U2 works abnormally, the GPIO pin cannot normally output a square wave periodic signal to the hardware watchdog chip U1, the M _ RST pin generates a low level signal, the second transistor Q2 is closed, the first transistor Q1 is closed, the third transistor Q3 is opened, the power supply cannot be normally supplied to the control chip U2 through the first transistor Q1, and the control chip U2 is powered off and shut down; meanwhile, the electric energy stored in the first filter capacitor C1 is consumed and discharged in time through the fourth resistor R4 and the third transistor Q3, so that the power-off protection circuit plays a role in power-off reset and power-off protection when a fault condition occurs in the MCU circuit system.
In this embodiment, the power-off protection circuit includes two control circuits, so that when the control chip is in a normal working state, the first control circuit normally supplies power to the control chip, and the second control circuit does not work; when the control chip is in an abnormal working state, the first control circuit does not work, the control chip is powered off, and the second control circuit discharges the electric energy in the filter capacitor so as to ensure that the control chip is effectively reset and restarted.
Example 2
The software upgrade circuit of the control chip of the present embodiment includes the power-off protection circuit of the control chip of embodiment 1.
As shown in fig. 4, the software upgrade circuit further includes a connection unit 3;
one end of the connecting unit 3 is electrically connected with the power input end A, and the other end of the connecting unit 3 is electrically connected with a power pin VCC of the control chip U2;
when the software upgrade of the control chip U2 is not started, the connection unit 3 is in the disconnected state (i.e., the normal state of the connection unit 3 is the disconnected state).
When software upgrading is needed to be performed on the control chip U2, the control chip U2 is used for controlling the connection unit 3 to connect the power input end A with a power pin VCC of the control chip U2;
when the software of the control chip U2 is upgraded, the connection unit 3 automatically restores to the disconnected state by default.
The connection unit 3 includes, but is not limited to, a timing control circuit and a switch.
When the software upgrading of the control chip is not needed, the connection unit is in a disconnected state. As shown in fig. 5, when the connection unit 3 includes the timing control circuit K and software upgrade needs to be performed on the control chip U2, the timing control circuit K may be closed in a manual control manner to ensure that the power input terminal a supplies power to the control chip U2 to complete the software upgrade; or, a control signal is sent to the timing control circuit K through the control chip U2 to control the timing control circuit K to close so as to ensure that the power input terminal a supplies power to the control chip U2 to complete software upgrading.
The timing control circuit K can be automatically switched off after the set time is switched on no matter under manual control or signal control, namely the timing control circuit K is in an off state under a general condition and only needs to be switched on when software upgrading is required.
As shown in fig. 6, when the connection unit 3 is a switch, the switch connecting the terminal B and the terminal C is manually closed, so that the power supplied to the power input terminal a is directly supplied to the control chip U2 through the terminal B and the terminal C, and then software upgrade is performed on the control chip U2; at this time, even if the reset signal generated by the hardware watchdog circuit turns off the Q1 and the Q2 and turns on the Q3, the normal power supply of the control chip U2 can be ensured not to be powered off, so that the software upgrading operation of the control chip U2 is ensured to be normally performed. After the upgrade is finished, the connection between the endpoint B and the endpoint C is disconnected, so that the whole MCU circuit system automatically restores to a normal working state.
In this embodiment, through add timing control circuit in power protection circuit, realize not dismantling, not replace, maintainer can carry out software upgrading to MCU at any time under the circumstances of not cutting off the power supply, and can not produce reset signal because of hardware watchdog circuit and make MCU upgrading unable normal clear, solved effectively and now can't carry out the problem of solitary software upgrading operation to MCU, reduced the maintenance cost, had the advantage that the operation is quick and convenient.
Example 3
As shown in fig. 7, the control system of the present embodiment includes a software upgrade circuit of the control chip in embodiment 3.
The control system also includes a control chip U2. The control chip U2 includes, but is not limited to, a microcontroller.
In the control system in the embodiment, the MCU can be powered off when the control chip is in an abnormal working state, and the filter capacitor is discharged to ensure that the control chip is reset and restarted effectively; the timing control circuit can be controlled to carry out software upgrading operation of the MCU at any time, so that maintainers can carry out software upgrading on the MCU at any time under the conditions of no disassembly, no replacement and no power failure, the problem that independent software upgrading operation cannot be carried out on a control chip at present is effectively solved, the maintenance cost is reduced, and the operation efficiency and the convenience are improved.
While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that this is by way of example only, and that the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the spirit and scope of the invention, and these changes and modifications are within the scope of the invention.
Claims (11)
1. The power-off protection circuit of the control chip is characterized by comprising a hardware watchdog chip, a first control circuit, a second control circuit and a first filter capacitor;
the first end of the first control circuit is electrically connected with a power supply input end, the second end of the first control circuit is electrically connected with a reset signal output pin of the hardware watchdog chip, and the third end of the first control circuit is electrically connected with a power supply pin of the control chip;
the first end of the second control circuit is electrically connected with the power input end, the second end of the second control circuit is respectively electrically connected with the power pin of the control chip and one end of the first filter capacitor, and the other end of the first filter capacitor is grounded;
the periodic signal input end of the hardware watchdog chip is electrically connected with the periodic signal output end of the control chip;
when the hardware watchdog chip can receive the periodic signal output by the control chip, a reset signal output pin of the hardware watchdog chip generates a high-level signal;
the first control circuit is used for supplying power to a power supply pin of the control chip according to the high level signal, the first filter capacitor is used for storing electric energy, and the second control circuit does not work;
when the hardware watchdog chip cannot receive the periodic signal output by the control chip, a reset signal output pin of the hardware watchdog chip generates a low-level signal;
the first control circuit does not work, and the control chip is in a power-off state;
the second control circuit is used for discharging the electric energy in the first filter capacitor.
2. The power-off protection circuit of the control chip according to claim 1, wherein the first control circuit includes a first transistor and a second transistor;
the first transistor is electrically connected with the second transistor, the power supply input end and a power supply pin of the control chip respectively;
the second transistor is electrically connected with a reset signal output pin of the hardware watchdog chip.
3. The power-off protection circuit of the control chip according to claim 2, wherein the first transistor is a PMOS transistor, and the second transistor is an NPN-type triode;
the first control circuit further comprises a first resistor and a second resistor;
the source electrode of the first transistor is electrically connected with the power supply input end, the drain electrode of the first transistor is electrically connected with the power supply pin of the control chip, and the grid electrode of the first transistor is electrically connected with the collector electrode of the second transistor;
one end of the first resistor is electrically connected with a reset signal output pin of the hardware watchdog chip, the other end of the first resistor is electrically connected with one end of the second resistor and a base electrode of the second transistor respectively, and the other end of the second resistor and an emitting electrode of the second transistor are grounded.
4. The power-off protection circuit of the control chip according to claim 3, wherein the second control circuit includes a third transistor;
the transistor is respectively and electrically connected with the power input end, the power pin of the control chip and the grounding end.
5. The power-off protection circuit of the control chip of claim 4, wherein the power-off protection circuit further comprises a third resistor;
the third transistor is an NMOS transistor; the second control circuit further comprises a fourth resistor;
one end of the third resistor is electrically connected with the power supply input end and the source electrode of the first transistor respectively, the other end of the third resistor is electrically connected with the grid electrode of the first transistor and the grid electrode of the third transistor respectively, the drain electrode of the third transistor is electrically connected with one end of the fourth resistor, the other end of the fourth resistor is electrically connected with the power supply pin of the control chip, and the source electrode of the third transistor is grounded.
6. The power-off protection circuit of the control chip of claim 1, wherein the power-off protection circuit further comprises a second filter capacitor;
one end of the second filter capacitor is electrically connected with the power input end and the power input pin of the hardware watchdog chip respectively, and the other end of the second filter capacitor is grounded; and/or the presence of a gas in the gas,
the periodic signal comprises a square wave periodic signal.
7. The power-off protection circuit of the control chip according to any one of claims 1 to 6, wherein a reset signal output pin of the hardware watchdog chip automatically generates the high-level signal after a set time of generating the low-level signal to trigger the control chip to perform reset restart.
8. A software upgrade circuit of a control chip, characterized in that the software upgrade circuit comprises the power-off protection circuit of the control chip of claims 1 to 7, the software upgrade circuit further comprising a connection unit;
one end of the connecting unit is electrically connected with the power input end, and the other end of the connecting unit is electrically connected with a power pin of the control chip;
when the software upgrading of the control chip is not needed, the connection unit is in a disconnected state;
when software upgrading needs to be carried out on the control chip, the control chip is used for controlling the connection unit to be closed.
9. The software upgrade circuit of a control chip according to claim 8, wherein the connection unit includes a timing control circuit;
wherein the timing control circuit automatically opens after a set time of closure.
10. A control system comprising the software upgrade circuit of the control chip of claim 8 or 9, the control system further comprising the control chip.
11. The control system of claim 10, wherein the control chip comprises a microcontroller.
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| CN111708308A (en) * | 2020-07-03 | 2020-09-25 | 迈普通信技术股份有限公司 | Single-board power supply control circuit and electronic equipment |
| CN112084057A (en) * | 2020-09-03 | 2020-12-15 | 青岛海信电子产业控股股份有限公司 | Hardware watchdog system |
| CN113434333A (en) * | 2021-06-07 | 2021-09-24 | 北京航天科颐技术有限公司 | Self-reset circuit and method for on-site protection type ARM processor |
| CN115242234A (en) * | 2022-08-09 | 2022-10-25 | 山东思科赛德矿业安全工程有限公司 | Single chip microcomputer system restarting circuit and method |
| CN115480949A (en) * | 2022-11-14 | 2022-12-16 | 锦浪科技股份有限公司 | Multi-chip fault linkage shutdown system and working method thereof |
| CN117111534A (en) * | 2023-10-16 | 2023-11-24 | 长沙先度科技有限公司 | Automatic power-on control circuit and control method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111708308A (en) * | 2020-07-03 | 2020-09-25 | 迈普通信技术股份有限公司 | Single-board power supply control circuit and electronic equipment |
| CN112084057A (en) * | 2020-09-03 | 2020-12-15 | 青岛海信电子产业控股股份有限公司 | Hardware watchdog system |
| CN113434333A (en) * | 2021-06-07 | 2021-09-24 | 北京航天科颐技术有限公司 | Self-reset circuit and method for on-site protection type ARM processor |
| CN115242234A (en) * | 2022-08-09 | 2022-10-25 | 山东思科赛德矿业安全工程有限公司 | Single chip microcomputer system restarting circuit and method |
| CN115480949A (en) * | 2022-11-14 | 2022-12-16 | 锦浪科技股份有限公司 | Multi-chip fault linkage shutdown system and working method thereof |
| CN117111534A (en) * | 2023-10-16 | 2023-11-24 | 长沙先度科技有限公司 | Automatic power-on control circuit and control method thereof |
| CN117111534B (en) * | 2023-10-16 | 2024-01-16 | 长沙先度科技有限公司 | Automatic power-on control circuit and control method thereof |
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