CN219392624U - Power supply control circuit and computer - Google Patents

Abstract

The application discloses a power control circuit and computer relates to the computer technology field. The power supply control circuit comprises a first switch module and a second switch module, wherein the control end of the first switch module is connected with a BIOS module, the BIOS module is used for outputting a power supply control signal, a first channel end of the first switch module is grounded, a second channel end of the first switch module is connected with a first power supply and is connected with the control end of the second switch module, the first channel end of the second switch module is connected with a second power supply, and the second channel end of the second switch module is used for being connected with a south bridge chip; when the power supply control signal is a low-level signal, the first switch module is cut off, the second switch module is cut off, and the readable and writable chip is powered off. By the technical means, the south bridge chip and the power supply thereof are controlled to be disconnected, so that the CMOS eliminates the modified parameters due to power failure, the short circuit risk caused by battery disassembly in the prior art is avoided, and the operation difficulty for eliminating the CMOS parameters is greatly reduced.

Description

Power supply control circuit and computer

Technical Field

The present disclosure relates to the field of computer technologies, and in particular, to a power control circuit and a computer.

Background

Before the computer leaves the factory, factory testers change function setting items of a BIOS (basic input output system) of the computer to verify whether various functions of the computer are normal. After the test is finished, the function setting items of the BIOS are reset to the default values through keys, so that the function setting items of the BIOS of the computer after leaving the factory are ensured to be the default values. However, the key reset can only restore the function setting item of the BIOS to the default value, and the modified CMOS (read-write chip) parameters cannot be restored. After the computer is installed on the customer site, the problems that the computer cannot be started, cannot be displayed, is started abnormally and the like can be caused by the abnormal CMOS parameters.

In the prior art, CMOS is a Random Access Memory (RAM) in a south bridge chip (PCH), and the effect of clearing CMOS parameters can be achieved by removing the battery of the south bridge chip so that the CMOS has no power supply to maintain parameter setting. However, the battery of the south bridge chip is removed, the battery can be taken out only after the computer is disassembled, the battery is assembled back after the battery is discharged, the operation process of battery disassembly is complex, and the risk of battery short circuit exists.

Disclosure of Invention

The utility model provides a power control circuit and computer, the passageway disconnection between control south bridge chip and its power supply through the power control signal of low level to make the CMOS in the south bridge chip clear away the parameter that modifies because of losing electricity, avoided among the prior art short circuit risk that battery dismantles and bring, greatly reduced the operation degree of difficulty of clearing away the CMOS parameter, improved the efficiency of clearing away the CMOS parameter.

In a first aspect, the present application provides a power control circuit comprising a first switch module and a second switch module, wherein:

the control end of the first switch module is connected with the BIOS module, the BIOS module is used for outputting a power supply control signal, a first channel end of the first switch module is grounded, a second channel end of the first switch module is connected with a first power supply and is connected with the control end of the second switch module, the first channel end of the second switch module is connected with a second power supply, and a second channel end of the second switch module is used for being connected with a south bridge chip;

and under the condition that the power supply control signal is a low-level signal, the first switch module is cut off, the second switch module is cut off, and the south bridge chip is powered off.

In a second aspect, the present application provides a computer, including a BIOS module, a south bridge chip, and the power control circuit according to the first aspect, a signal output pin of the BIOS module is connected to a first channel end of a first switch module of the power control circuit, and a power end of the south bridge chip is connected to a second channel end of a second switch module of the power control circuit, where:

the BIOS module is used for outputting a low-level power supply control signal through the signal output pin under the condition of recovering default setting or abnormal starting.

In the application, the BIOS module is recovering default setting or under the abnormal condition of starting up, the power control signal of low level is transmitted to the power control circuit through the signal output pin, under the action of the power control signal of low level, the first channel end and the second channel end of the first switch module are cut off, the control end of the second switch module is connected with the high level of the first power supply improvement, the first channel end and the second channel end of the second switch module are cut off, and the second power supply stops supplying power to the south bridge chip, so that the south bridge chip loses power. Through the technical means, the BIOS module can cut off the passage between the south bridge chip and the power supply thereof by transmitting the low-level power supply control signal to the power supply control circuit, so that the CMOS in the south bridge chip can clear the modified parameters due to power failure, the CMOS parameters can be automatically cleared when the power on is abnormal or the default setting is restored, the short circuit risk caused by battery disassembly in the prior art is avoided, the operation difficulty of clearing the CMOS parameters is greatly reduced, and the efficiency of clearing the CMOS parameters is improved. And the power supply control circuit does not influence the connection path between the south bridge chip and the power supply when the computer works normally, namely the CMOS in the south bridge chip is always in a charged state, so that the reliability of the CMOS stored data is ensured.

Drawings

Fig. 1 is a schematic structural diagram of a power control circuit according to an embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of another power control circuit according to an embodiment of the present disclosure;

in the figure, 10, a power supply control circuit; 11. a first switch module; 12. a second switch module; 13. a first power supply; 14. a second power supply; 141. a standby power supply; 142. a battery power supply; 20. a south bridge chip; 30. a BIOS module; CLCMOS, power control signal; r1, a first resistor; r2, a second resistor; r3, a third resistor; r4, a fourth resistor; r5, a fifth resistor; r6, a sixth resistor; c1, a first capacitor; c2, a second capacitor; c3, a third capacitor; PQ1, triode; PQ2, P-type field effect transistor; d1, a first diode; d2, a second diode; GND, ground.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the following detailed description of specific embodiments thereof is given with reference to the accompanying drawings. It is to be understood that the specific embodiments described herein are merely illustrative of the application and not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the matters related to the present application are shown in the accompanying drawings. Before discussing exemplary embodiments in more detail, it should be mentioned that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart depicts operations (or steps) as a sequential process, many of the operations can be performed in parallel, concurrently, or at the same time. Furthermore, the order of the operations may be rearranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figures. The processes may correspond to methods, functions, procedures, subroutines, and the like.

The terms first, second and the like in the description and in the claims, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged, as appropriate, such that embodiments of the present application may be implemented in sequences other than those illustrated or described herein, and that the objects identified by "first," "second," etc. are generally of a type and not limited to the number of objects, e.g., the first object may be one or more. Furthermore, in the description and claims, "and/or" means at least one of the connected objects, and the character "/", generally means that the associated object is an "or" relationship.

In an embodiment, after the BIOS module is restored to the default setting, the factory tester disassembles the computer after power failure, disassembles the battery of the south bridge chip from the main board, so that the CMOS in the south bridge chip has no battery power supply and no main board power supply, and the CMOS achieves the effect of thoroughly clearing the CMOS parameters under the condition that the power supply maintenance parameter is not set. However, the disassembly and assembly of the computer and the disassembly and assembly of the south bridge chip battery take much time, and the efficiency of clearing the CMOS parameters is low. And the disassembly process is complex, a non-factory tester is difficult to complete the whole disassembly process under the condition of not damaging the machine, if the computer arrives at the customer site, the customer is difficult to remove the CMOS parameters in a battery disassembly mode after finding that the computer is abnormal due to the starting of the CMOS, and the customer has to send the computer back to the factory or find out the personnel of the factory to get on the door for repair, so that the use experience of the customer is seriously affected. Even if factory test personnel disassemble batteries, the battery disassembling process is at risk of short circuit, and the safety of a computer cannot be guaranteed.

In order to solve the above-mentioned problems, the present embodiment provides a power control circuit and a computer, so as to cut off the connection path between the south bridge chip and the power supply thereof by the power control circuit, so that the CMOS in the south bridge chip clears the modified parameters due to power failure.

Fig. 1 is a schematic structural diagram of a power control circuit according to an embodiment of the present application. Referring to fig. 1, the power control circuit 10 specifically includes: the control end of the first switch module 11 is connected with the BIOS module 30, the BIOS module 30 is used for outputting a power supply control signal CLCMOS, a first channel end of the first switch module 11 is grounded to GND, a second channel end of the first switch module 11 is connected with the first power supply 13 and is connected with the control end of the second switch module 12, a first channel end of the second switch module 12 is connected with the second power supply 14, and a second channel end of the second switch module 12 is used for being connected with the south bridge chip 20; in the case where the power control signal CLCMOS is a low level signal, the first switch module 11 is turned off, the second switch module 12 is turned off, and the south bridge chip 20 is powered off.

For example, when the power control signal CLCMOS is a low level signal, the control terminal of the first switch module 11 inputs a low level, and the first channel terminal and the second channel terminal of the first switch module 11 are disconnected such that the level of the second channel terminal of the first switch module 11 is equal to the voltage of the first power source 13, i.e., the control terminal of the second switch module 12 inputs a high level. When the control terminal of the second switch module 12 inputs a high level, the first channel terminal and the second channel terminal of the second switch module 12 are disconnected, so that the second power supply 14 cannot supply power to the south bridge chip 20. The second power supply 14 is the only power supply of the south bridge chip 20, when the second power supply 14 no longer supplies power to the south bridge chip 20, the south bridge chip 20 and the CMOS are powered off, and the COMS in the south bridge chip 20 thoroughly clears the modified parameters under the condition that no power maintenance parameter is set, so that the effect that the COMS parameters can be cleared without disassembling the battery of the south bridge chip 20 is achieved.

Further, when the power control signal CLCMOS is a high level signal, the control terminal of the first switch module 11 inputs a high level, and the first channel terminal and the second channel terminal of the first switch module 11 are turned on, so that the second channel terminal of the first switch module 11 is shorted to the ground GND. When the second channel end of the first switch module 11 is shorted to the ground GND, the control end of the second switch module 12 inputs a low level, and the first channel end and the second channel end of the second switch module 12 are turned on, so that the second power supply 14 supplies power to the south bridge chip 20. It can be understood that the computer can transmit the high-level power control signal CLCMOS to the power control circuit 10 during normal operation, so that the second power supply 14 supplies power to the south bridge chip 20, and the COMS in the south bridge chip 20 can be ensured to maintain the parameter setting in a charged state, so that the power control circuit 10 set in this embodiment does not affect the normal use of the south bridge chip 20 and the COMS.

In an embodiment, the first switch module 11 is a triode PQ1, and the second switch module 12 is a P-type field effect transistor PQ2; the first switch module 11 is a triode PQ1, a base electrode of the triode PQ1 corresponds to a control end of the first switch module 11, an output end of the triode PQ1 corresponds to a first channel end of the first switch module 11, and an input end of the triode PQ1 corresponds to a second channel end of the first switch module 11. The second switch module 12 is a P-type field effect transistor PQ2, the gate of the P-type field effect transistor PQ2 corresponds to the control end of the second switch module 12, the source of the P-type field effect transistor PQ2 corresponds to the first channel end of the second switch module 12, and the drain of the P-type field effect transistor PQ2 corresponds to the second channel end of the second switch module 12. The present embodiment will be described taking the transistor PQ1 as an NPN transistor PQ1 as an example. Fig. 2 is a schematic structural diagram of another power control circuit according to an embodiment of the present application. As shown in fig. 2, the emitter of the transistor PQ1 is grounded GND, and the collector of the transistor PQ1 is connected to the first power supply 13. The voltage of the first power supply 13 is 3V. When the power control signal CLCMOS is a low level signal, the transistor PQ1 is turned off, the control terminal voltage of the P-type field effect transistor PQ2 is equal to 3v, the P-type field effect transistor PQ2 is turned off, and the second power supply 14 stops supplying power to the south bridge chip 20, and the south bridge chip 20 and CMOS lose power. When the power control signal CLCMOS is a high level signal, the transistor PQ1 is turned on, the control terminal of the P-type field effect transistor PQ2 is shorted to the ground GND, the P-type field effect transistor PQ2 is turned on, the second power supply 14 supplies power to the south bridge chip 20, and the south bridge chip 20 and the CMOS are powered. It can be understood that the present embodiment utilizes the switching characteristics of the triode PQ1 and the P-type field effect transistor PQ2 to precisely control the connection state between the south bridge chip 20 and the power supply thereof, so as to realize the power-on maintenance parameter setting of the south bridge chip 20 and the COMS during normal operation of the computer and the power-off control of the south bridge chip 20 and the COMS when the COMS parameter needs to be cleared.

In the present embodiment, the first switch module 11 and the second switch module 12 may employ a relay, a photocoupler, or the like in addition to the transistor PQ1 and the field effect transistor. Compared with a relay and a photoelectric coupler, the triode PQ1 and the field effect transistor have the advantages of higher response speed and lower power consumption, are universal electronic devices in industry, and have more obvious cost advantage and practical advantage.

Referring to fig. 2, the power control circuit 10 further includes a first resistor R1 and a second resistor R2, wherein a first end of the first resistor R1 is connected to a control end of the first switch module 11 and a first end of the second resistor R2, the power control signal CLCMOS is connected to the ground GND through a second end of the first resistor R1, and a second end of the second resistor R2 is grounded. The first resistor R1 is used as a current limiting resistor to shunt the power control signal CLCMOS, so as to prevent a large current from directly acting on the control terminal of the first switch module 11, thereby improving the working safety of the first switch module 11 and further improving the circuit reliability. The second resistor R2 can be used as a pull-down resistor to stabilize the level of the control end of the first switch module 11 at a low level when the power control signal CLCMOS is a low level signal, so as to prevent the first switch module 11 from malfunction caused by high level interference, and improve the power control accuracy of the south bridge chip 20.

Referring to fig. 2, the power control circuit 10 further includes a third resistor R3, a first end of the third resistor R3 is connected to the second channel end of the first switch module 11 and the control end of the second switch module 12, and a second end of the third resistor R3 is connected to the first power supply 13. The third resistor R3 is used as a current limiting resistor to shunt the current of the first power supply 13, so as to avoid the first power supply 13 from being directly shorted to the ground GND when the first switch module 11 is turned on, and further avoid a large current from passing through the first switch module 11, so as to improve the working safety of the first switch module 11, and further improve the circuit reliability.

Referring to fig. 2, the power control circuit 10 further includes a first capacitor C1, a first end of the first capacitor C1 is connected to the second channel end of the first switch module 11 and the control end of the second switch module 12, and a second end of the first capacitor C1 is grounded GND. Illustratively, when the computer is operating normally, the power control signal CLCMOS is high, the first switch module 11 is turned on, the second switch module 12 is turned on, and the second power supply 14 supplies power to the south bridge chip 20. If the computer outputs the high-level processor control signal at this time, the first capacitor C1 can isolate the interference of the processor control signal on the second switch module 12, so that the second switch module 12 is kept in the on state, and the reliability of supplying power to the south bridge chip 20 by the second power supply 14 is ensured.

Referring to fig. 2, the second power supply 14 includes a standby power supply 141 and a battery power supply 142, and the power supply control circuit 10 further includes a fourth resistor R4, a fifth resistor R5, a first diode D1, and a second diode D2, the resistance value of the fourth resistor R4 being smaller than the resistance value of the fifth resistor R5; the first end of the fourth resistor R4 is connected to the standby power supply 141, the second end of the fourth resistor R4 is connected with the anode of the first diode D1, and the cathode of the first diode D1 is connected with the first channel end of the second switch module 12; the first end of the fifth resistor R5 is connected to the battery power supply 142, the second end of the fifth resistor R5 is connected to the anode of the second diode D2, and the cathode of the second diode D2 is connected to the first channel end of the second switch module 12. The standby power 141 is a power source for supplying power to the south bridge chip 20 through the motherboard, and the battery power 142 is a power source for the battery of the south bridge chip 20. When the second switch module 12 is turned on, if the main board is charged, the anode voltage of the first diode D1 is higher than the anode voltage of the second diode D2, the first diode D1 is turned on and the second diode D2 is turned off, and the standby power 141 supplies power to the south bridge chip 20. If the motherboard is powered off, the anode voltage of the first diode D1 is lower than the anode voltage of the second diode D2, the second diode D2 is turned on and the first diode D1 is turned off, and the battery power supply 142 supplies power to the south bridge chip 20. In this embodiment, regardless of the standby or shutdown state of the computer, the south bridge chip 20 and the COMS can maintain the parameter setting with electricity, and the reliability of the COMS parameter storage is improved.

Referring to fig. 2, the power control circuit 10 further includes a second capacitor C2, a third capacitor C3, and a sixth resistor R6, wherein the first end of the second capacitor C2, the first end of the third capacitor C3, and the first end of the sixth resistor R6 are all connected to the second channel end of the second switch module 12, and the second end of the second capacitor C2, the second end of the third capacitor C3, and the second end of the sixth resistor R6 are all grounded GND. Illustratively, when the computer is to clear the COMS parameter, the power control signal CLCMOS is low, the first switch module 11 is turned off, the second switch module 12 is turned off, and the second power supply 14 stops supplying power to the south bridge chip 20. If the computer outputs a high-level processor control signal at this time, the second capacitor C2 can isolate the interference of the processor control signal on the south bridge chip 20, so that the south bridge chip 20 and the COMS are kept in a power-off state. When the second power source 14 supplies power to the south bridge chip 20, the third capacitor C3 may store electric power to supply instantaneous current to the south bridge chip 20. When the second power supply 14 stops supplying power to the south bridge chip 20, the south bridge chip 20 can discharge rapidly through the sixth resistor R6, so as to accelerate the power consumption of the south bridge chip 20 and improve the efficiency of clearing the COMS parameter.

On the basis of the above embodiment, the present embodiment further provides a computer, where the computer includes a BIOS module 30, a south bridge chip 20 and a power control circuit 10, a signal output pin of the BIOS module 30 is connected to a first channel end of a first switch module 11 of the power control circuit 10, and a power end of the south bridge chip 20 is connected to a second channel end of a second switch module 12 of the power control circuit 10. The BIOS module 30 is configured to output a low-level power control signal CLCMOS through a signal output pin in case of recovering a default setting or a power-on abnormality. For example, the BIOS module 30 transmits the low-level power control signal CLCMOS to the power control circuit 10 through the signal output pin when the default setting is restored, so that the second power supply 14 is controlled by the power control circuit 10 to stop supplying power to the south bridge chip 20, so that the CMOS clears the parameters due to power failure, the CMOS parameters are cleared while the BIOS module 30 is restored to the default setting, no additional clearing operation instruction is required, and the operation of the BIOS module 30 for restoring the default setting is optimized. If the problem of abnormal starting up of the computer occurs due to abnormal CMOS parameters in the customer site, the BIOS module 30 transmits a low-level power control signal CLCMOS to the power control circuit 10 through the signal output pin when the abnormal starting up is detected, so that the power control circuit 10 controls the second power supply 14 to stop supplying power to the south bridge chip 20, the CMOS eliminates the parameters due to power failure, the problem of abnormal starting up can be easily solved in the customer site, and the use experience of a user is improved.

In this embodiment, the signal output pin is used to output a low-level power control signal CLCMOS for a preset period of time. The preset duration is set according to the actual power-down situation of the south bridge chip 20. Illustratively, the BIOS module 30 outputs a low-level power control signal CLCMOS for a preset duration on the control signal output pin after restoring the default setting or detecting a power-on abnormality. Under the action of the low-level power control signal CLCMOS, the power control circuit 10 cuts off the path between the second power supply 14 and the power supply end of the south bridge chip 20, and the south bridge chip 20 loses the ability to maintain the setting because no power is supplied for a preset period of time, so that enough time is ensured to thoroughly clear CMOS parameters.

In summary, in the power control circuit 10 and the computer provided in this embodiment of the present application, under the condition of recovering the default setting or the abnormal startup through the BIOS module 30, the low-level power control signal CLCMOS is transmitted to the power control circuit 10 through the signal output pin, under the effect of the low-level power control signal CLCMOS, the first channel end and the second channel end of the first switch module 11 are turned off, the control end of the second switch module 12 is connected to the high level raised by the first power supply 13, the first channel end and the second channel end of the second switch module 12 are turned off, and the second power supply 14 stops supplying power to the south bridge chip 20, so that the south bridge chip 20 is powered off. Through the above technical means, the BIOS module 30 can cut off the path between the south bridge chip 20 and its power supply by transmitting the low-level power supply control signal CLCMOS to the power supply control circuit 10, so that the CMOS20 in the south bridge chip clears the modified parameters due to power failure, thereby automatically clearing the CMOS parameters when the power is on abnormality or recovering the default setting, avoiding the short circuit risk caused by battery disassembly in the prior art, greatly reducing the operation difficulty of clearing the CMOS parameters, and improving the efficiency of clearing the CMOS parameters. And the power control circuit 10 does not affect the connection path between the south bridge chip 20 and the power supply thereof when the computer works normally, namely the CMOS in the south bridge chip 20 is always in a charged state, so that the reliability of the CMOS stored data is ensured.

The foregoing description is only of the preferred embodiments of the present application and the technical principles employed. The present application is not limited to the specific embodiments described herein, but is capable of numerous obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the present application. Therefore, while the present application has been described in connection with the above embodiments, the present application is not limited to the above embodiments, but may include many other equivalent embodiments without departing from the spirit of the present application, and the scope of the present application is determined by the scope of the claims.

Claims (10)

1. A power control circuit comprising a first switch module and a second switch module, wherein:

the control end of the first switch module is connected with a BIOS module, and the BIOS module is used for outputting a power supply control signal; the first channel end of the first switch module is grounded, the second channel end of the first switch module is connected with a first power supply and is connected with the control end of the second switch module, the first channel end of the second switch module is connected with a second power supply, and the second channel end of the second switch module is used for being connected with a south bridge chip;

and under the condition that the power supply control signal is a low-level signal, the first switch module is cut off, the second switch module is cut off, and the south bridge chip is powered off.

2. The power control circuit of claim 1, wherein the first switch module is a triode, a base of the triode corresponds to a control terminal of the first switch module, an output terminal of the triode corresponds to a first channel terminal of the first switch module, and an input terminal of the triode corresponds to a second channel terminal of the first switch module.

3. The power control circuit of claim 1, wherein the second switch module is a P-type field effect transistor, a gate of the P-type field effect transistor is correspondingly a control terminal of the second switch module, a source of the P-type field effect transistor is correspondingly a first channel terminal of the second switch module, and a drain of the P-type field effect transistor is correspondingly a second channel terminal of the second switch module.

4. The power control circuit of claim 1, further comprising a first resistor and a second resistor, wherein a first end of the first resistor is connected to the control end of the first switch module and a first end of the second resistor, the power control signal is coupled through a second end of the first resistor, and a second end of the second resistor is grounded.

5. The power control circuit of claim 1, further comprising a third resistor, a first end of the third resistor connected to the second channel end of the first switch module and the control end of the second switch module, a second end of the third resistor connected to the first power supply.

6. The power control circuit of claim 1, further comprising a first capacitor having a first end connected to the second channel end of the first switch module and the control end of the second switch module, the second end of the first capacitor being grounded.

7. The power supply control circuit of claim 1, wherein the second power supply comprises a standby power supply and a battery power supply, the power supply control circuit further comprising a fourth resistor, a fifth resistor, a first diode, and a second diode, the fourth resistor having a resistance value less than the fifth resistor; the first end of the fourth resistor is connected to the standby power supply, the second end of the fourth resistor is connected with the anode of the first diode, and the cathode of the first diode is connected with the first channel end of the second switch module; the first end of the fifth resistor is connected to the battery power supply, the second end of the fifth resistor is connected with the anode of the second diode, and the cathode of the second diode is connected with the first channel end of the second switch module.

8. The power control circuit of claim 1, further comprising a second capacitor, a third capacitor, and a sixth resistor, wherein the first end of the second capacitor, the first end of the third capacitor, and the first end of the sixth resistor are each connected to the second channel end of the second switch module, and wherein the second end of the second capacitor, the second end of the third capacitor, and the second end of the sixth resistor are each grounded.

9. A computer, comprising a BIOS module, a south bridge chip, and a power control circuit according to any one of claims 1-8, wherein a signal output pin of the BIOS module is connected to a first channel end of a first switch module of the power control circuit, and a power end of the south bridge chip is connected to a second channel end of a second switch module of the power control circuit, wherein:

the BIOS module is used for outputting a low-level power supply control signal through the signal output pin under the condition of recovering default setting or abnormal starting.

10. The computer of claim 9, wherein the signal output pin is configured to output a low-level power control signal for a preset duration.