CN116231577A

CN116231577A - Fault isolation circuit, fault isolation method, storage medium and electronic device

Info

Publication number: CN116231577A
Application number: CN202111471255.2A
Authority: CN
Inventors: 赵俊
Original assignee: ZTE Corp
Current assignee: ZTE Corp
Priority date: 2021-12-03
Filing date: 2021-12-03
Publication date: 2023-06-06

Abstract

The embodiment of the application provides a fault isolation circuit, a fault isolation method, a storage medium and an electronic device, wherein the method comprises the following steps: detecting the current of the load; under the condition that the current of the load is abnormal, the power supply for the load is disconnected by closing the PMOS tube connected with the load, the problem that the influence of instantaneous heavy current cannot be filtered by adopting the technology of combining the MOS tube switching characteristic and the voltage comparator to carry out load overcurrent protection in the related technology is solved, the problem of low detection accuracy is solved, the accurate detection of load faults and the self-isolation of the load faults are realized, the faults are not spread, the intelligent degree of the product is higher and more reliable, and the structure is simple and the cost is low.

Description

Fault isolation circuit, fault isolation method, storage medium and electronic device

Technical Field

The embodiment of the application relates to the field of communication, in particular to a fault isolation circuit, a fault isolation method, a storage medium and an electronic device.

Background

In a bus type power supply circuit, when a certain load on a bus is abnormal, the power supply circuit is greatly influenced, and particularly, the power supply circuit cannot work normally due to load short circuit or abnormal load impedance, so that the normal work of other loads on the bus is influenced.

In the current load fault detection scheme using discrete devices, a load overcurrent protection scheme is widely used by adopting a technology of combining MOS tube switching characteristics and a voltage comparator, but the scheme also has the following defects: the influence of instantaneous heavy current cannot be filtered out, and the detection accuracy is not high. When the capacitive impedance of the load is large, the load is a large impact current, and the load is possibly misjudged to be a load fault, so that the system cannot be powered up normally.

Aiming at the problems that the influence of instantaneous heavy current cannot be filtered out by adopting the technology of combining the switching characteristic of the MOS tube and the voltage comparator to carry out load overcurrent protection in the related technology, and the detection accuracy is not high, no solution is proposed yet.

Disclosure of Invention

The embodiment of the application provides a fault isolation circuit, a fault isolation method, a storage medium and an electronic device, which are used for at least solving the problems that the influence of instantaneous heavy current cannot be filtered out by adopting the technology of combining MOS tube switching characteristics and a voltage comparator for load overcurrent protection in the related technology, and the detection accuracy is not high.

According to one embodiment of the present application, there is provided a fault isolation circuit comprising: the device comprises a detection circuit 1, a quick turn-off circuit 3, a self-recovery circuit 4 and a PMOS tube 6, wherein the detection circuit 1 is connected with the quick turn-off circuit 3, the quick turn-off circuit 3 is connected with the PMOS tube 6, and the PMOS tube 6 is connected with a load;

the detection circuit 1 is used for detecting the current of the load, and sending a turn-off signal to the quick turn-off circuit 3 when the current of the load is abnormal;

and the quick turn-off circuit 3 is used for controlling the PMOS tube to be turned off according to the turn-off signal and disconnecting the power supply for the load.

In an exemplary embodiment, the fault isolation circuit further comprises a self-recovery circuit 4, wherein the self-recovery circuit 4 is connected to the detection circuit 1,

the detection circuit 1 is further configured to output an abnormal overcurrent protection signal to the self-recovery circuit 4 when the current of the load is abnormal;

the self-recovery circuit 4 is configured to reset the detection circuit 1 after a preset time according to the abnormal overcurrent protection signal;

the detection circuit 1 is further configured to send an on signal to the quick turn-off circuit 3 after reset;

the quick turn-off circuit 3 is used for controlling the PMOS tube to be turned on according to the turn-on signal, and normally supplies power to the load.

In an exemplary embodiment, the self-recovery circuit 4 is further configured to perform discharging according to the shutdown signal, and output a reset signal to the detection circuit 1 when the discharge amount reaches a preset threshold;

the detection circuit 1 is further configured to perform reset according to the reset signal.

In an exemplary embodiment, the detection circuit 1 is further configured to send the abnormal overcurrent protection signal to a CPU, and reset under the driving of the CPU.

In an exemplary embodiment, the fault isolation circuit further includes: a slow start driving circuit 2, wherein the slow start driving circuit 2 is connected with the PMOS tube,

the detection circuit 1 is further configured to send a slow start signal to the slow start driving circuit 2 when the current of the load is normal;

and the slow start driving circuit 2 is used for slowly starting the PMOS tube according to the slow start signal and starting to supply power to the load.

In an exemplary embodiment, the slow start driving circuit 2 is driven by a CPU or by VCC.

In an exemplary embodiment, the detection circuit 1 is further configured to send a normal overcurrent protection signal to the CPU when the current is normal;

the slow start driving circuit 2 is further configured to slowly start the PMOS transistor according to the slow start signal under the driving of the CPU.

According to another embodiment of the present application, there is further provided a fault isolation method, applied to the fault isolation circuit, including:

detecting the current of the load;

judging whether the current of the load is abnormal or not;

and under the condition that the current of the load is abnormal, the power supply for the load is disconnected by closing the PMOS tube connected with the load.

In an exemplary embodiment, in a case that the current of the load is abnormal, disconnecting the power supply to the load by closing the PMOS transistor connected to the load includes:

under the condition that the current of the load is abnormal, an abnormal overcurrent protection signal is sent to the CPU;

receiving a reset signal sent by the CPU;

and resetting according to the reset signal, and disconnecting the power supply for the load by closing the PMOS tube connected with the load after resetting.

In an exemplary embodiment, the method further comprises:

and under the condition that the current of the load is normal, starting the PMOS tube to supply power to the load.

In an exemplary embodiment, under a condition that the current of the load is normal, starting the PMOS transistor to supply power to the load includes:

under the condition that the current of the load is normal, sending a normal overcurrent protection signal to the CPU;

and starting the PMOS tube to supply power to the load in a slow start mode under the drive of the CPU.

In an exemplary embodiment, determining whether the current of the load is abnormal includes:

judging whether the current of the load is larger than a first preset threshold or smaller than a second preset threshold, wherein the first preset threshold is larger than the second preset threshold;

if the judgment result is yes, determining that the current of the load is abnormal;

and under the condition that the judgment result is negative, determining that the current of the load is normal.

According to a further embodiment of the present application, there is also provided a computer readable storage medium having stored therein a computer program, wherein the computer program is arranged to perform the steps of any of the method embodiments described above when run.

According to a further embodiment of the present application, there is also provided an electronic device comprising a memory having stored therein a computer program and a processor arranged to run the computer program to perform the steps of any of the method embodiments described above.

In the embodiment of the application, the current of a load is detected; under the condition that the current of the load is abnormal, the PMOS tube connected with the load is turned off to supply power to the load, so that the problem that the influence of instantaneous heavy current cannot be filtered out by adopting the technology of combining the MOS tube switching characteristic with a voltage comparator to carry out load overcurrent protection in the related technology can be solved, the problem that the detection accuracy is low is solved, the accurate detection of load faults and the self-isolation of the load faults are realized, the faults are not spread, the intelligent degree of the product is higher and more reliable, and the structure is simple and the cost is low.

Drawings

FIG. 1 is a block diagram of a fault isolation circuit according to an embodiment of the present application;

FIG. 2 is a block diagram one of a fault isolation circuit according to an alternative embodiment of the present application;

FIG. 3 is a block diagram two of a fault isolation circuit according to an alternative embodiment of the present application;

FIG. 4 is a schematic diagram of a fault isolation circuit application scenario according to an embodiment of the present application;

FIG. 5 is a block diagram III of a fault isolation circuit according to an alternative embodiment of the present application;

FIG. 6 is a flow chart of a fault isolation method according to an embodiment of the invention;

FIG. 7 is a schematic diagram of fault isolation based on a fault isolation circuit according to an embodiment of the present application;

fig. 8 is a circuit diagram of a fault isolation circuit according to an embodiment of the present application.

Detailed Description

Embodiments of the present application will be described in detail below with reference to the accompanying drawings in conjunction with the embodiments.

It should be noted that the terms "first," "second," and the like in the description and claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.

The embodiment of the application provides a fault isolation circuit, which can effectively solve the defects of other isolation schemes under a board-level bus type power supply architecture, realize the functions of accurate detection of load faults, self-isolation of load faults, self-recovery of load faults and the like, ensure that faults are not spread, have higher intelligent degree and more reliability, and have simple structure, low cost and important practical value for load protection.

FIG. 1 is a block diagram of a fault isolation circuit according to an embodiment of the present application, as shown in FIG. 1, the fault isolation circuit includes: the device comprises a detection circuit 1, a quick turn-off circuit 3 and a PMOS tube 6, wherein the detection circuit 1 is connected with the quick turn-off circuit 3, the quick turn-off circuit 3 is connected with the PMOS tube 6, and the PMOS tube 6 is connected with a load;

a detection circuit 1 for detecting a current of a load, and transmitting a shutdown signal to a quick shutdown circuit 3 when the current of the load is abnormal;

the fast turn-off circuit 3 is used for controlling the PMOS tube 6 to be turned off according to the turn-off signal, and cutting off power supply to the load.

In an exemplary embodiment, fig. 2 is a block diagram one of a fault isolation circuit according to an alternative embodiment of the present application, and as shown in fig. 2, the fault isolation circuit further includes a self-recovery circuit 4, where the self-recovery circuit 4 is connected to a detection circuit 1, and the detection circuit 1 outputs an abnormal overcurrent protection signal to the self-recovery circuit 4 in a case that a current of a load is abnormal; the self-recovery circuit 4 resets the detection circuit 1 after a preset time according to the abnormal overcurrent protection signal; the detection circuit 1 sends an on signal to the quick turn-off circuit 3 after reset; the rapid turn-off circuit 3 controls the PMOS tube 6 to be turned on according to the turn-on signal, and normally supplies power to the load.

The detection circuit in the embodiment of the present application may reset under the drive of the self-recovery circuit 4, or may reset by the drive of the CPU. On the other hand, the self-recovery circuit 4 discharges according to the off signal, and when the discharge amount reaches a preset threshold, a reset signal is output to the detection circuit 1, and the detection circuit 1 resets according to the reset signal. On the other hand, the detection circuit 1 transmits an abnormal overcurrent protection signal to the CPU, and after the CPU receives the abnormal overcurrent inclusion signal, transmits a drive signal to the detection circuit 1, and the detection circuit 1 resets under the drive of the CPU.

In an exemplary embodiment, fig. 3 is a block diagram two of a fault isolation circuit according to an alternative embodiment of the present application, and as shown in fig. 3, the fault isolation circuit further includes: the slow start driving circuit 2 is connected with the PMOS tube 6, and the detection circuit 1 sends a slow start signal to the slow start driving circuit 2 under the condition that the current of a load is normal; and the slow start driving circuit 2 slowly starts the PMOS tube 6 according to the slow start signal and starts to supply power for a load. The slow start circuit is carried, the influence of large current impact caused by capacitive load on the detection accuracy of the detection circuit in the power supply power-on process can be effectively solved, the characteristic that parameters can be adjusted according to needs is achieved, and the load fault isolation requirements of various on-board large-power and small-power supply circuits are met.

In some embodiments, the slow start drive circuit 2 is driven by a CPU or by VCC. Further, the detection circuit 1 is further configured to send a normal overcurrent protection signal to the CPU under the condition that the current is normal; the slow start driving circuit 2 is further configured to slowly start the PMOS transistor 6 according to the slow start signal under the driving of the CPU.

Fig. 4 is a schematic diagram of an application scenario of a fault isolation circuit according to an embodiment of the present application, as shown in fig. 4, a plurality of loads are mounted under a power supply bus, and power is supplied to the plurality of loads at the same time, and an isolation module built by using a discrete device is added on each load power supply link. When the rear-stage load of the isolation module fails, other loads are not affected or damaged, so that other loads can be effectively protected, and the maintenance cost is reduced. Meanwhile, the module also has an automatic recovery function, can automatically open the isolation module, prevents the occurrence of voltage bus abnormality caused by misoperation, and has parameter adjustability, so that the recovery period is adjusted according to requirements. The fault reporting function can be selected, the fault point can be quickly and effectively found and maintained, the time cost is saved, and the product intellectualization is improved.

The fault isolation circuit provided by the embodiment of the application can solve the problems of load fault isolation and self-recovery under the on-board bus type power supply scene. By adopting discrete devices, the system can realize multiple functions of fault isolation, fault isolation self-recovery, alarm reporting and load full life cycle state monitoring; the detection accuracy is high, the use field is wide, and the impact of impact current and other emergency conditions can be eliminated.

In order to achieve the above characteristics and purposes, the embodiment of the application uses the self-recovery circuit, and the circuit can freely configure the capacitor discharging time through device parameters, so that the scheme has a self-recovery function after fault isolation.

FIG. 5 is a block diagram III of a fault isolation circuit according to an alternative embodiment of the present application, as shown in FIG. 5, comprising: the detection circuit 1, the quick turn-off circuit 3, the self-recovery circuit 4 and the PMOS tube 6 (main MOS tube).

The detection circuit 1 detects the current of the high-precision sampling resistor R1 by using a current detection chip, the high-precision sampling resistor R1 is connected with the self-recovery circuit 4 through a detection signal, an output reset signal of the self-recovery circuit 4 is connected with the detection circuit 1, the detection circuit 1 is connected with the quick turn-off circuit 3 through the detection signal, and the quick turn-off circuit 3 is connected with the PMOS tube 6.

In the scheme, the detection circuit 1 is connected with the quick turn-off circuit 3, and the function of quickly turning off the PMOS tube 6 under the abnormal load or short circuit state is realized through the fault signal, so that the purpose of quickly off-loading the power supply bus and protecting the power supply bus is achieved.

In the above-described configuration, the self-recovery circuit 4 starts discharging when the detection circuit 1 detects that an overcurrent occurs in the circuit. The discharging time is controlled by adjusting RC parameters, when the discharging time reaches a certain threshold value, a reset signal is output, after the detection circuit 1 is reset, the detection circuit 1 outputs a signal to the quick turn-off circuit 3, so that the PMOS tube 6 is turned on again, and the self-recovery function is realized. If the fault still exists, the detection circuit 1 drives the quick turn-off circuit 3 to turn off the PMOS tube 6, so that the purpose of off-load is achieved.

In a traditional PMOS tube driving circuit, a slow start circuit is added, the influence caused by instantaneous impact current is eliminated, and fault isolation under different loads is realized through configuration parameters.

As shown in fig. 5, includes: 2, slowly starting the driving circuit; 3, rapidly switching off the circuit; 6, PMOS.

The slow start drive circuit 2 and the quick turn-off circuit 3 are simultaneously connected to the grid electrode of the PMOS tube 6.

In the above scheme, the slow start driving circuit 2 is used to slowly start the PMOS transistor 6, so that the scheme can drive a large capacitive load. And capacitive loads with different capacitance values can be realized by adjusting the parameters of the slow start circuit.

Whether the fault reports to the CPU or not, whether the load state monitoring function is carried out in real time or not can be selected according to requirements.

The fault isolation circuit provided by the embodiment of the application has a fault self-recovery function, the outside of the recovery period can be adjusted at will, the system protection is followed by counting down, the PMOS tube 6 is restarted after the counting down is finished, the circuit self-recovery power supply function is realized, and the whole process does not need CPU intervention. Therefore, the scheme has higher tolerance to load fault detection, can not influence the use due to power supply problems caused by sporadic or misoperation, and has high intelligent degree. The slow start function is added, the influence of instantaneous impact current on detection accuracy is eliminated, and the detection accuracy is higher. Meanwhile, the gate rapid discharging function is integrated, so that the high-side PMOS switch can carry a large capacitive load and can rapidly isolate faults such as short circuit and the like. The contradiction between capacity carrying capacity and quick protection capacity is well solved.

According to another embodiment of the present application, there is further provided a fault isolation method, applied to the fault isolation circuit described above, and fig. 6 is a flowchart of a fault isolation method according to an embodiment of the present invention, as shown in fig. 6, including:

step S602, detecting the current of a load;

step S604, judging whether the current of the load is abnormal;

in this embodiment of the present application, the step S604 may specifically include: judging whether the current of the load is larger than a first preset threshold or smaller than a second preset threshold, wherein the first preset threshold is larger than the second preset threshold; if the judgment result is yes, determining that the current of the load is abnormal; and under the condition that the judgment result is negative, determining that the current of the load is normal.

And step S606, under the condition that the current of the load is abnormal, the power supply to the load is disconnected by closing the PMOS tube connected with the load.

In this embodiment of the present application, the step S606 may specifically include: under the condition that the current of the load is abnormal, an abnormal overcurrent protection signal is sent to the CPU; receiving a reset signal sent by the CPU; and resetting according to the reset signal, and disconnecting the power supply for the load by closing the PMOS tube connected with the load after resetting.

Through the steps S602 to S606, the problems that the influence of instantaneous heavy current cannot be filtered out by adopting the technology of combining the MOS tube switching characteristic and the voltage comparator to carry out load overcurrent protection in the related technology and the detection accuracy is low can be solved, the accurate detection of load faults and the self-isolation of the load faults are realized, the faults are not spread, the intelligent degree of the product is higher and more reliable, and the structure is simple and the cost is low.

In an optional embodiment, under a condition that the current of the load is normal, the PMOS transistor is turned on to supply power to the load in a slow start manner. Further, under the condition that the current of the load is normal, a normal overcurrent protection signal is sent to the CPU; and starting the PMOS tube to supply power to the load in a slow start mode under the drive of the CPU.

Based on the fault isolation circuit, fig. 7 is a schematic diagram of fault isolation based on the fault isolation circuit according to an embodiment of the present application, as shown in fig. 7, a single board is powered on, and a slow start driving circuit is started; whether the detection circuit is normal or not, if yes, opening the PMOS tube, and if no, on one hand, rapidly opening and closing the PMOS tube by rapidly switching off the circuit; on the other hand, the PMOS tube is opened through the detection circuit and the quick turn-off circuit by the self-recovery circuit and the delay reset; and the PMOS tube is used for driving to supply power for a load.

Embodiments of the present application are described in detail below with reference to specific circuit diagrams.

Fig. 8 is a circuit diagram of a fault isolation circuit according to an embodiment of the present application, as shown in fig. 8, when a load is not abnormal, a single board is powered on, after detecting that a power supply bus is powered on normally, a detection circuit 1 outputs a normal overcurrent protection signal, at this time, an NPN tube Q5 of a self-recovery circuit 4 is turned off, VCC charges a capacitor C2, and after the charging is completed, voltages at two ends of C2 are maintained at VCC. The NPN tube Q2 and the PNP tube Q4 of the quick turn-off circuit 3 are closed, and the quick turn-off circuit does not work. NPN transistor Q3 in slow start drive circuit 2 is in the open state under CPU drive signal or power signal' S drive, and DC input power charges electric capacity C3, and after electric capacity at C3 both ends reaches the gate (G) of Q1 and the open threshold voltage of source (S), source and drain (D) of Q1 begin switching on, then VGS voltage continues rising, until source and drain are fully switched on, and DC input power just supplies power to the load through Q1. And the time of power-on startup can be adjusted by adjusting the parameters of C3 and R15.

When the load is abnormal, the detection circuit 1 can quickly detect the abnormal power supply of the power supply bus and output an overcurrent protection signal. The over-current protection signal turns on Q4 in the quick turn-off circuit 3, thereby turning on Q2. After the Q2 is conducted, the grid electrode and the source electrode of the PMOS tube Q1 are connected together through the Q2, and the MOS tube is turned off, so that the purpose of rapidly turning off the MOS tube is achieved, and rapid fault isolation is realized.

For the self-recovery circuit 4, the over-current protection signal drives Q5 on. After Q5 turns on, C2 starts discharging and the discharge time is controlled by the RC time. When the voltage at two ends of the C2 is reduced to the reset threshold value of the detection circuit 1, a reset signal is output to reset the overcurrent detection chip, so that the detection circuit 1 outputs a normal overcurrent protection signal, the quick turn-off circuit 3 is turned off, the PMOS tube is turned on again, and the load is powered normally, so that an automatic recovery function is realized. If the load is in an abnormal state, the detection circuit 1 continues to drive the quick turn-off circuit 3 to turn off the MOS tube, so as to achieve the purpose of protection. And the self-recovery process does not require the CPU to take part in control.

The overcurrent protection signal can be introduced into the CPU, the CPU can judge whether the fault exists or not by detecting the overcurrent protection signal, the state of the load is monitored in real time, and the load state visualization is realized. If the fault exists, the fault point can be rapidly and accurately judged, and the positioning and the maintenance are convenient. And the CPU may output a reset signal to complete the reset of the detection circuit 1 together with the self-recovery circuit 4.

Embodiments of the present application also provide a computer readable storage medium having a computer program stored therein, wherein the computer program is arranged to perform the steps of any of the method embodiments described above when run.

In one exemplary embodiment, the computer readable storage medium may include, but is not limited to: a usb disk, a Read-only Memory (ROM), a random access Memory (Random Access Memory, RAM), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing a computer program.

Embodiments of the present application also provide an electronic device comprising a memory having a computer program stored therein and a processor arranged to run the computer program to perform the steps of any of the method embodiments described above.

In an exemplary embodiment, the electronic apparatus may further include a transmission device connected to the processor, and an input/output device connected to the processor.

Specific examples in this embodiment may refer to the examples described in the foregoing embodiments and the exemplary implementation, and this embodiment is not described herein.

It will be appreciated by those skilled in the art that the modules or steps of the application described above may be implemented in a general purpose computing device, they may be concentrated on a single computing device, or distributed across a network of computing devices, they may be implemented in program code executable by computing devices, so that they may be stored in a storage device for execution by computing devices, and in some cases, the steps shown or described may be performed in a different order than that shown or described herein, or they may be separately fabricated into individual integrated circuit modules, or multiple modules or steps of them may be fabricated into a single integrated circuit module. Thus, the present application is not limited to any specific combination of hardware and software.

The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the same, but rather, various modifications and variations may be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application should be included in the protection scope of the present application.

Claims

1. A fault isolation circuit, comprising: the device comprises a detection circuit 1, a quick turn-off circuit 3, a self-recovery circuit 4 and a PMOS tube 6, wherein the detection circuit 1 is connected with the quick turn-off circuit 3, the quick turn-off circuit 3 is connected with the PMOS tube 6, and the PMOS tube 6 is connected with a load;

2. The fault isolation circuit of claim 1, further comprising a self-recovery circuit 4, wherein the self-recovery circuit 4 is connected to the detection circuit 1,

3. The fault isolation circuit of claim 2, wherein,

the self-recovery circuit 4 is further configured to perform discharging according to the shutdown signal, and output a reset signal to the detection circuit 1 when the discharge amount reaches a preset threshold;

4. The fault isolation circuit of claim 2, wherein,

the detection circuit 1 is further configured to send the abnormal overcurrent protection signal to a CPU, and reset the CPU under the drive of the CPU.

5. The fault isolation circuit of claim 1, further comprising: a slow start driving circuit 2, wherein the slow start driving circuit 2 is connected with the PMOS tube,

6. The fault isolation circuit of claim 5, wherein,

the slow start driving circuit 2 is driven by a CPU or VCC.

7. The fault isolation circuit of claim 5, wherein,

the detection circuit 1 is further configured to send a normal overcurrent protection signal to the CPU under the condition that the current is normal;

8. A fault isolation method applied to the fault isolation circuit of any one of claims 1 to 7, comprising:

detecting the current of the load;

judging whether the current of the load is abnormal or not;

9. The method of claim 8, wherein in the event of an abnormal current in the load, disconnecting the power to the load by closing a PMOS tube connected to the load comprises:

receiving a reset signal sent by the CPU;

10. The method of claim 8, wherein the method further comprises:

11. The method of claim 10, wherein turning on the power to the load by slowly starting the PMOS transistor in the case that the current of the load is normal comprises:

12. The method of claim 8, wherein determining whether the current of the load is abnormal comprises:

13. A computer-readable storage medium, characterized in that the storage medium has stored therein a computer program, wherein the computer program is arranged to execute the method of any of the claims 8 to 12 when run.

14. An electronic device comprising a memory and a processor, characterized in that the memory has stored therein a computer program, the processor being arranged to run the computer program to perform the method of any of the claims 8 to 12.