CN112416646A - Watchdog control circuit and watchdog circuit - Google Patents
Watchdog control circuit and watchdog circuit Download PDFInfo
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- CN112416646A CN112416646A CN202011445905.1A CN202011445905A CN112416646A CN 112416646 A CN112416646 A CN 112416646A CN 202011445905 A CN202011445905 A CN 202011445905A CN 112416646 A CN112416646 A CN 112416646A
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- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
- G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
- G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
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Abstract
The invention relates to the field of circuit boards, and comprises a watchdog control circuit and a watchdog circuit, wherein the watchdog control circuit comprises a watchdog chip, a first gate circuit and a high-level output device, the first gate circuit is used for adjusting a signal output by the watchdog chip, one end of the first gate circuit is connected with the output end of the watchdog chip, and the other end of the first gate circuit is connected with the high-level output device in a break-make manner; the output end of the first gate circuit is used for being connected with the reset end of the microprocessor. The method supports the starting/shielding of the watchdog function, meets the scene requirements of program programming and normal operation of the program, has no influence on the watchdog function, and keeps the watchdog function reliable and stable; supporting forced resetting of the microprocessor; the circuit is simplified, and the manufacturing cost is lower.
Description
Technical Field
The invention relates to the field of circuit boards, in particular to a watchdog control circuit and a watchdog circuit.
Background
The watchdog is a timer circuit, generally has an input called feeding dog, and an output to RST end of Microprocessor (MCU), when MCU normally works, it outputs a signal to feeding dog end at intervals, and clears WDT, if the prescribed time is exceeded and no feeding dog is fed (generally when program is run away), the WDT timing is exceeded, and then a reset signal is given to MCU, so that MCU is reset. The MCU is prevented from crashing. The watchdog is used to prevent the program from endless cycling.
During the development and debugging stage or the production programming program, the MCU needs to be ensured to work continuously and cannot be reset midway, and the watchdog circuit needs to be forbidden under the condition. And the watchdog function needs to be started before the product with the programmed program is delivered, so that the MCU of the product can be reset by the watchdog when the hang-up condition occurs in the operation process, and the normal operation is automatically recovered. In the prior art, the implementation mode of enabling/disabling the watchdog function is complex, and the normal performance of the watchdog chip is affected when the watchdog function is disabled by partial technologies, so that the use requirements of different scenes cannot be well met.
Disclosure of Invention
The present invention is directed to overcoming at least one of the disadvantages of the prior art, and to providing a watchdog control circuit and a watchdog circuit.
The technical scheme adopted by the invention is that a watchdog control circuit is provided, which comprises a watchdog chip; the first gate circuit is used for adjusting signals output by the watchdog chip, one input end of the first gate circuit is connected with the output end of the watchdog chip, and the other input end of the first gate circuit is connected with the high-level output device in a break-make manner; and the output end of the first gate circuit is used for being connected with the reset end of the microprocessor.
The first gate circuit enables the output signal of the watchdog chip to reach the reset end of the microprocessor after specific logic operation, and the output signal is received by the microprocessor, and the goal of starting or shielding the watchdog function can be achieved through the matching of the first gate circuit and the high-level output device: when the watchdog function needs to be started, the connection between the high-level output device and one input end of the first gate circuit is cut off, the output signal of the watchdog chip is kept in an original state after passing through the first gate circuit, the monitoring function is normally executed, and the program is prevented from generating dead circulation or running away; when the watchdog function needs to be shielded, the high-level output device is connected to one input end of the first gate circuit, a high-level signal is input into the first gate circuit, an output signal of the watchdog chip enters from the other input end of the first gate circuit, no matter whether the output signal of the watchdog chip is a high-level signal or a low-level signal, an output result after logical operation of the first gate circuit is a high-level signal, and the microprocessor receives the high-level signal and does not reset.
The shielding watchdog is substantially generated in the transmission process of the output signal of the watchdog chip, the watchdog chip still normally responds in the shielding process and outputs a correct signal, and the normal operation of the watchdog chip is not influenced, so that the realization method of the shielding watchdog does not influence the function of the original watchdog circuit. In the watchdog circuit requiring accurate reset, the signals of the watchdog chip usually connected with the microprocessor only comprise the dog feeding signal of the microprocessor to the watchdog chip and the reset signal of the watchdog chip to the microprocessor, and the simple circuit design can ensure that the watchdog chip accurately and reliably monitors the abnormal operation state of the microprocessor, and can ensure that the reset signal sent by the watchdog chip rapidly and accurately reaches the microprocessor, thereby improving the operation reliability. The watchdog control circuit of the invention also conforms to the thought, the connection between the watchdog chip and the first gate circuit is simple, the accuracy of the reset signal transmission is not affected when the watchdog function stage is started, and the watchdog control circuit can be applied to the situation requiring accurate reset.
On the other hand, after the first gate is connected to the high-level output device in a single way, the output result is stable, and a high-level signal is kept, wherein the high-level signal is not influenced by elements such as other resistors and capacitors of a circuit, so that the watchdog function is continuously and reliably shielded, and a reliable guarantee is created in the situation that the microprocessor cannot be reset midway, such as research, development and debugging.
Further, the watchdog control circuit adopts positive logic; the first gate circuit is an OR gate. In the positive logic circuit, a high level indicates a logic 1, and a low level indicates a logic 0. When the watchdog function is shielded, the high-level output device inputs a high-level signal of logic 1 to the OR gate, and the output is logic 1 as long as one logic 1 exists in the input according to the operation logic of the OR gate; only when all inputs are logic 0, the output is low level logic 0, no matter the watchdog chip inputs low level signals of logic 0 or high level signals of logic 1 to the or gate, and finally the output of the or gate is high level signals of logic 1, and the microprocessor receives the high level signals and does not reset.
Furthermore, the watchdog control circuit adopts negative logic; the first gate circuit is an AND gate. In the negative logic circuit, a high level indicates a logic 0, and a low level indicates a logic 1. The operation logic of the AND gate is that when all the inputs are logic 1 at the same time, the output is logic 1, otherwise, the output is logic 0. Similarly, when the watchdog function is shielded, no matter what signal is sent by the watchdog chip, the output of the and gate is a high-level signal.
The two first gate circuits are designed into the simplest and most direct scheme, the number of input ends of the first gate circuits is only two, input signals needing to be processed are few, complex logic operation is not needed, and signals can be output rapidly. On the other hand, the watchdog control circuit is simplified to the maximum extent, and the normal operation function of the watchdog is stably kept.
Further, the high level output device is a power supply VCC.
Furthermore, the IO end of the watchdog chip is configured with a ground resistor, and the resistance value of the ground resistor is adjustable. The timing time of the watchdog chip can be changed by adjusting the resistance value of the ground resistor, and the microprocessor usually uses two different timing times in the loading (including power-on loading and reset loading) stage and the normal operation stage, wherein the timing times are the interval duration of two adjacent times of sending out the dog feeding signals. Because the loading phase is relatively long, the timing time of the microprocessor in this phase is usually longer than that of the microprocessor in the normal operation phase, i.e., in normal operation, the microprocessor sends out the dog feeding signal more frequently, and the watchdog chip is communicated with the information that the reset is not needed. In the prior art, the watchdog circuit is usually provided with two watchdog chips, which are respectively responsible for monitoring the loading stage and the running stage. The invention uses a watchdog chip, takes the timing time of the loading stage as the uniform timing time, the watchdog chip does not need to frequently receive the dog feeding signal, avoids the error reset caused by the normal operation of the microprocessor but not sending the dog feeding signal, realizes the adjustment of the timing time by configuring the ground resistor capable of changing the resistance value, ensures that one timing time is simultaneously suitable for the loading stage and the operation stage of the microprocessor, simplifies the watchdog circuit and reduces the manufacturing cost.
Furthermore, an indicator light is arranged on a line connecting the first gate circuit and the high-level output device. The indicating lamp and the high-level output device are connected in series into the first gate circuit, the high-level output device is connected into the first gate circuit in a disconnection mode, the first gate circuit goes out along with the lighting of the indicating lamp, the lighting indication watchdog function is shielded, the going out indication watchdog function is started, the indicating effect is visual and reliable, and the additional circuit of the watchdog control circuit is not increased.
More specifically, the indicator light is an LED light. The LED lamp has the advantages that the lamp body is small and exquisite, the material and the space are saved, the idea of simplifying the circuit is met, meanwhile, the LED lamp has the advantages of low energy consumption, less heat dissipation and the like, and the LED lamp is suitable for being used as an indicating lamp to be applied to a watchdog circuit.
Furthermore, the watchdog control circuit also comprises a second gate circuit and a low level output device; the second gate circuit is used for forcing the microprocessor to receive a reset signal, one end input end of the second gate circuit is connected with the output end of the first gate circuit, the output end of the first gate circuit is connected with the microprocessor through the second gate circuit, and the other end input end of the second gate circuit is connected with the low level output device in a break-make mode. The second gate circuit has the same action principle as the first gate circuit, and when the low-level output device is connected to the output end of the first gate circuit, the logic operation of the second gate circuit ensures that the microprocessor receives a reset signal (namely a low-level signal) certainly, and the microprocessor is manually and forcibly reset by skipping the judgment of the watchdog chip. The watchdog control circuit adds a forced reset function, but is not complicated thereby, and keeps the normal and stable function of the watchdog.
More specifically, the low level output device is a powered pull-down resistor.
The invention also provides a watchdog circuit applying the watchdog control circuit, which comprises a microprocessor; one end of the microprocessor is connected with the output end of the first gate circuit, and the other end of the microprocessor is connected with the watchdog chip. The microprocessor is connected with the output end of the first gate circuit, the end of the microprocessor connected with the output end of the first gate circuit is a reset end, and the end of the microprocessor connected with the watchdog chip is a dog feeding end. The watchdog circuit has the functions of starting/shielding the watchdog, forcibly resetting and the like, and is simple in whole circuit, low in manufacturing cost and reliable and stable in watchdog function.
Compared with the prior art, the invention has the beneficial effects that: the starting/shielding watchdog function is supported, the scene requirements of program programming and normal operation of the program are met, the watchdog function is not influenced, and the reliability and the stability of the watchdog function are kept; supporting forced resetting of the microprocessor; the circuit is simplified, and the manufacturing cost is lower.
Drawings
Fig. 1 is a schematic diagram of a watchdog control circuit according to the present invention.
Fig. 2 is a schematic diagram of a watchdog control circuit supporting forced reset according to the present invention.
FIG. 3 is a schematic diagram of a watchdog circuit according to the present invention.
Description of reference numerals: a watchdog chip 1; a first gate circuit 2; a high level output device 3; a second gate circuit 4; a low level output device 5; a microprocessor 6.
Detailed Description
The drawings are only for purposes of illustration and are not to be construed as limiting the invention. For a better understanding of the following embodiments, certain features of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.
Example 1
As shown in fig. 1, the present embodiment provides a watchdog control circuit for connecting to a microprocessor to monitor the microprocessor, the watchdog control circuit includes a watchdog chip 1, a first gate circuit 2, and a high level output device 3. The first gate circuit 2 is used for adjusting the signal output by the watchdog chip 1, and has one end input end connected with the reset end of the watchdog chip 1 and the other end input end connected with the high-level output device 3 in a break-make manner; the output of the first gate 2 is used to connect to the reset terminal of the microprocessor.
The first gate circuit 2 makes the output signal of the watchdog chip 1 reach the reset end of the microprocessor after specific logic operation, and the output signal is received by the microprocessor, and the goal of starting or shielding the watchdog function can be achieved through the matching of the first gate circuit 2 and the high level output device 3: when the watchdog function needs to be started, the connection between the high-level output device 3 and one input end of the first gate circuit 2 is cut off, the output signal of the watchdog chip 1 passes through the first gate circuit 2 and then is kept in the original state, the monitoring function is normally executed, and the program is prevented from generating dead circulation or running away; when the watchdog function needs to be shielded, the high-level output device 3 is connected to one input end of the first gate circuit 2, a high-level signal is input into the first gate circuit 2, an output signal of the watchdog chip 1 enters from the other input end of the first gate circuit 2, no matter the output signal of the watchdog chip 1 is a high-level signal or a low-level signal, an output result after logical operation of the first gate circuit 2 is a high-level signal, and the microprocessor receives the high-level signal and does not reset. In this embodiment, the watchdog control circuit adopts positive logic, the first gate circuit 2 is an or gate, and when the watchdog function is masked, the high level output device 3 inputs a high level signal of logic 1 to the or gate first gate circuit 2, so as to ensure that the output result of the or gate first gate circuit 2 is a high level signal of logic 1. When the watchdog function is started, the high-level output device 3 is switched off, and the signal sent by the watchdog chip 1 is kept as it is through the first gate circuit 2. In some embodiments where the circuit is negative logic, the first gate 2 is an and gate. It should be noted that, this embodiment provides an idea of applying a gate circuit to the watchdog control circuit to shield the watchdog function, the first gate circuit does not refer to a logic circuit only including one or more circuits, and it falls within the protection scope of the present invention to use one or more combinations of an and gate, an or gate, a not gate, and a nand gate to make the signal output by the watchdog chip reach the microprocessor after logic operation.
The high level output device 3 of this embodiment is the power VCC, is equipped with the jumper cap switch on the circuit that high level output device 3 connects first gate circuit 2, connects the jumper cap switch, and the power VCC is to or gate input high level, and the watchdog function is shielded this moment. In other embodiments, the high-level output device 3 may also be a common emitter amplifier circuit, and the means for turning on and off the high-level output device 3 may be replaced by other means commonly used in the art.
The IO end of the watchdog chip of this embodiment is configured with a ground resistor, the resistance of the ground resistor is adjustable, the specific resistance of the ground resistor can be integrated with the timing duration requirement of the microprocessor in the loading stage and the running stage for compromise processing, one timing duration is used in the two stages, so that one microprocessor only needs to be configured with the watchdog control circuit of this embodiment, and meanwhile, this embodiment is also applicable to different microprocessors.
The circuit that first gate circuit 2 and high level output device 3 of this embodiment are connected is equipped with the pilot lamp on, the pilot lamp is simply the circuit that high level output device 3 and first gate circuit 1 are connected to the series connection, switch-on high level output device 3 when shielding watchdog function, the pilot lamp lights thereupon, the user can directly perceivedly learn watchdog control circuit's mode, the pilot lamp also has the function of instructing the trouble simultaneously, if switch-on high level output device 3 back pilot lamp is not bright, it breaks down to explain some components on this series connection circuit, unable normal shielding, can learn the fault location fast, avoid need burn program microprocessor but the condition that resets. LED lights are a preferred type of indicator light.
Example 2
As shown in fig. 2, in this embodiment, in addition to embodiment 1, a second gate circuit 4 and a low level output device 5 are added, and a signal output from the first gate circuit 2 is subjected to a logic operation. The watchdog control circuit of the embodiment has a function of forcing the microprocessor to reset, one end input end of the second gate circuit 4 is connected with the output end of the first gate circuit 2, so that the output end of the first gate circuit 2 is connected with the microprocessor through the second gate circuit 4, and the other end input end of the second gate circuit 4 is connected with the low level output device 5 in a break-and-make manner. In this embodiment, the second gate circuit 4 is an and gate, and when the low level output device 5 inputs a low level signal of logic 0 to the and gate, the and gate second gate circuit 4 outputs a low level signal of logic 0 no matter the signal is a high level signal or a low level signal after passing through the first gate circuit 2, and the microprocessor resets after receiving the low level signal, thereby implementing a function of skipping over the watchdog chip to forcibly reset the microprocessor. It should be noted that, this embodiment provides an idea of applying a gate circuit to a watchdog control circuit to forcibly reset a microprocessor, the second gate circuit does not refer to a logic circuit containing only one or more types, and it falls within the scope of the present invention to use one or more combinations of and gate, or gate, not gate, and nand gate to make a signal reaching the microprocessor after logic operation necessarily be a reset signal. The low level output device 5 of this embodiment is a pull-down resistor with one end connected to a power supply, and the other end connected to one input end of the second gate circuit 4, and is switched on and off by using a jumper switch.
Example 3
The embodiment provides a watchdog circuit comprising the watchdog control circuit of embodiment 2 and a microprocessor 6, wherein one end of the microprocessor 6 is connected with the output end of the first gate circuit 2, and the other end is connected with a watchdog chip 1. And one end of the microprocessor 6, which is connected with the output end of the first gate circuit 2, is a reset end, and one end of the microprocessor, which is connected with the watchdog chip 1, is a dog feeding end. In the watchdog circuit in other embodiments, the microprocessor may further be connected to two watchdog control circuits, and the two watchdog control circuits are responsible for implementing the watchdog functions in the loading stage and the running stage.
The preferred workflow when the watchdog function is enabled in this embodiment is as follows: the microprocessor is powered on and loaded to prepare for a normal operation stage; after the power-on loading is finished, the microprocessor runs a program, a dog feeding signal is sent to the watchdog chip at the interval duration of the timing time, and the watchdog chip 1 sends a high-level signal after receiving the dog feeding signal within the timing time; if the watchdog control circuit normally starts the watchdog function, the high level output device 3 is not connected with the input end of the first gate circuit 2, a high level signal sent by the watchdog chip passes through the second gate circuit 4 after passing through the first gate circuit 2 in an original state, the low level output device 5 is not connected with the second gate circuit 4, the high level signal reaches the microprocessor 6, the microprocessor 6 keeps a normal operation program after receiving the high level signal, and resetting is not performed;
similarly, if the watchdog chip 1 does not receive the dog feeding signal within the timing time, a low level signal is sent to instruct the microprocessor to reset, and the low level signal reaches the microprocessor through the first gate circuit 2 and the second gate circuit 4 as it is.
The preferred workflow when the watchdog function is masked is: the watchdog chip 1 keeps the normal operation, outputs a high level signal or a low level signal according to whether a dog feeding signal is received, the first gate circuit 2 is connected to the high level output device 3, the high level output device 3 inputs the high level signal to the first gate circuit 2, the signal output by the watchdog chip 1 and the high level signal output by the high level output device 3 are subjected to logic operation, finally, the high level signal is definitely obtained, and the high level signal subjected to the logic operation is kept in an original state (the low level output device 5 is not connected) through the second gate circuit 4 to reach the microprocessor 6.
The preferred working flow during forced reset is as follows: the low level output device 5 is connected to the second gate circuit 4, a low level signal is input to the second gate circuit 4, the result output by the first gate circuit 2 and the low level signal output by the low level output device 5 are subjected to logic operation, the finally obtained signal is necessarily a low level signal, and the microprocessor 6 receives the low level signal transmitted by the second gate circuit to reset.
It should be understood that the above-mentioned embodiments of the present invention are only examples for clearly illustrating the technical solutions of the present invention, and are not intended to limit the specific embodiments of the present invention. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention claims should be included in the protection scope of the present invention claims.
Claims (10)
1. A watchdog control circuit comprises a watchdog chip and is characterized in that,
the first gate circuit is used for adjusting signals output by the watchdog chip, one input end of the first gate circuit is connected with the output end of the watchdog chip, and the other input end of the first gate circuit is connected with the high-level output device in a break-make manner; and the output end of the first gate circuit is used for being connected with the reset end of the microprocessor.
2. A watchdog control circuit according to claim 1,
the watchdog control circuit adopts positive logic;
the first gate circuit is an OR gate.
3. A watchdog control circuit according to claim 1,
the watchdog control circuit adopts negative logic;
the first gate circuit is an AND gate.
4. A watchdog control circuit according to claim 1,
the high level output device is a power supply VCC.
5. A watchdog control circuit according to claim 1,
the IO end of the watchdog chip is provided with a ground resistor, and the resistance value of the ground resistor is adjustable.
6. A watchdog control circuit according to claim 1,
and an indicator light is arranged on a line connecting the first gate circuit and the high-level output device.
7. A watchdog control circuit according to claim 6,
the indicator light is an LED light.
8. A watchdog control circuit according to one of claims 1 to 7,
the gate circuit and the low level output device are also included;
the second gate circuit is used for forcing the microprocessor to receive a reset signal, one end input end of the second gate circuit is connected with the output end of the first gate circuit, the output end of the first gate circuit is connected with the microprocessor through the second gate circuit, and the other end input end of the second gate circuit is connected with the low level output device in a break-make mode.
9. A watchdog control circuit according to claim 8,
the low level output device is a powered pull-down resistor.
10. A watchdog circuit comprising a microprocessor, wherein,
further comprising the watchdog control circuit of any one of claims 1-9;
one end of the microprocessor is connected with the output end of the first gate circuit, and the other end of the microprocessor is connected with the watchdog chip.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011445905.1A CN112416646A (en) | 2020-12-09 | 2020-12-09 | Watchdog control circuit and watchdog circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011445905.1A CN112416646A (en) | 2020-12-09 | 2020-12-09 | Watchdog control circuit and watchdog circuit |
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| CN112416646A true CN112416646A (en) | 2021-02-26 |
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| CN202011445905.1A Pending CN112416646A (en) | 2020-12-09 | 2020-12-09 | Watchdog control circuit and watchdog circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113342151A (en) * | 2021-06-08 | 2021-09-03 | 江苏金智科技股份有限公司 | Watchdog control circuit and control method of relay protection device for preventing startup from being locked |
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| US20130067287A1 (en) * | 2011-09-14 | 2013-03-14 | Honda Motor Co., Ltd. | Electronic control device |
| CN105892607A (en) * | 2016-04-01 | 2016-08-24 | 上海斐讯数据通信技术有限公司 | Circuit and method for preventing switch from being repetitively reset |
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