CN113342151A - Watchdog control circuit and control method of relay protection device for preventing startup from being locked - Google Patents
Watchdog control circuit and control method of relay protection device for preventing startup from being locked Download PDFInfo
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- CN113342151A CN113342151A CN202110634703.XA CN202110634703A CN113342151A CN 113342151 A CN113342151 A CN 113342151A CN 202110634703 A CN202110634703 A CN 202110634703A CN 113342151 A CN113342151 A CN 113342151A
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
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- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
- G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
- G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
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Abstract
The invention discloses a watchdog control circuit and a control method of a relay protection device for preventing a startup card from being dead, comprising a software enabling control module, a watchdog chip module and a hardware enabling control module, wherein the software enabling control module is used for generating a CPU enabling signal for feeding a watchdog according to a CPU dead halt signal of the relay protection device; the watchdog chip module is used for generating an initial reset signal according to the enabled CPU dog feeding signal; the hardware enabling control module judges whether the initial reset signal is effective or not according to the initial reset signal and the CPU operation information; if the initial reset signal is effective, sending a reset signal to the CPU according to the start dog feeding signal; if the initial reset signal is invalid, the reset signal is not sent to the CPU, and the method and the device have the stability of the hardware watchdog and the control flexibility of the hardware switch watchdog.
Description
Technical Field
The invention relates to the technical field of power grid relay protection, in particular to a watchdog control circuit and a watchdog control method of a relay protection device for preventing a startup card from being dead.
Background
With the development of modern electronic technology, relay protection devices with microprocessing function have been widely used in the electric power automation industry in China. Along with the functions of the protection device are more and more powerful, the program structure is more and more complex, the instruction codes are longer and longer, and under the influence of a strong electromagnetic environment of a power field, the device is out of control, the program is run away, and the probability of the crash of each functional module is also multiplied. In this regard, a common solution is to place a watchdog circuit during circuit design, and the basic principle is as follows: after the CPU program is halted, the CPU will not reset the watchdog circuit regularly, and the watchdog circuit controls the reset signal to reset the device after a certain time.
In the software development and debugging stage of the device, the watchdog cannot exist, the reset signal output by the watchdog chip is directly disconnected in a mode of pulling out the jumper cap, the function development of the device is stable and reliable, and the jumper cap is plugged when the device leaves a factory to restore the function of the watchdog chip. However, in the transportation and field installation processes of the device, the jumper cap is easy to loose and has poor contact or directly falls off, and cannot be found in the device, so that the phenomenon that the reset signal of the watchdog is disconnected and invalid exists in some devices.
Disclosure of Invention
The purpose of the invention is as follows: in order to overcome the defects in the prior art, the invention provides a watchdog control circuit and a control method of a relay protection device for preventing a startup card from being locked, so as to solve the problem that a reset signal jumper cap is easy to loosen and fall off, and simultaneously, the watchdog control circuit has the stability of a hardware watchdog and the control flexibility of the functions of a software and hardware switching watchdog chip.
The technical scheme is as follows: in order to achieve the purpose, the invention adopts the technical scheme that:
the utility model provides a prevent dead relay protection device watchdog control circuit of start-up card, includes software enable control module, watchdog chip module, hardware enable control module, wherein:
the software enabling control module is used for generating an enabling CPU dog feeding signal according to a CPU crash signal of the relay protection device and sending the enabling CPU dog feeding signal to the watchdog chip module.
The watchdog chip module is used for generating an initial reset signal according to the enabled CPU dog feeding signal and sending the initial reset signal to the hardware enabling control module.
The hardware enabling control module is used for receiving an initial reset signal sent by the watchdog chip module, receiving CPU operation information sent by a CPU of the relay protection device and a signal for starting to feed dogs. And judging whether the initial reset signal is effective or not according to the initial reset signal and the CPU operation information. And if the initial reset signal is effective, sending a reset signal to the CPU according to the start dog feeding signal. If the initial reset signal is invalid, the reset signal is not transmitted to the CPU.
Preferably: the software enabling control module comprises a logic chip I1, a resistor I R1 and a capacitor I C1, wherein one end of the resistor I R1 is used for being connected with an enabling signal CPU-WDI-EN pin of the CPU, and the other end of the resistor I R1 is connected with an enabling pin OE of the logic chip I U1. A DIR pin of the first logic chip U1 is connected with a power supply voltage, a pin A1 of the first logic chip U1 is used for being connected with a feeding dog signal CPU-WDI pin of the CPU, a VCC pin of the first logic chip U1 is connected with the power supply voltage, a GND pin of the first logic chip U1 is grounded, one end of the first capacitor C1 is connected with the VCC pin of the first logic chip U1, the other end of the first capacitor C1 is connected with the GND pin of the first logic chip U1, and a pin B1 of the first logic chip U1 is connected with the watchdog chip module.
Preferably: the watchdog chip module comprises a watchdog chip U2 and a capacitor II C2, wherein a feeding dog signal input end WDI of the watchdog chip U2 is connected with a pin B1 of a logic chip I1, a VCC pin of the watchdog chip U2 is connected with a power supply voltage, a GND pin of the watchdog chip U2 is grounded, one end of the capacitor II C2 is connected with the VCC pin of the watchdog chip U2, the other end of the capacitor II C2 is connected with the GND pin of the watchdog chip U2, and a RESET signal output pin RESET of the watchdog chip U2 is connected with the hardware enable control module.
Preferably: the hardware enabling control module comprises an OR gate logic chip U3, a resistor II R2, a resistor III R3 and a capacitor III C3, wherein an input end A of the OR gate logic chip U3 is connected with a RESET signal output pin RESET of a watchdog chip U2, and an input end II B of the OR gate logic chip U3 is used for being connected with a jumper cap J1. The VCC pin of the OR gate logic chip U3 is connected with a power supply voltage, the GND pin of the OR gate logic chip U3 is grounded, one end of the capacitor tri C3 is connected with the VCC pin of the OR gate logic chip U3, and the other end of the capacitor tri C3 is connected with the GND pin of the OR gate logic chip U3. One end of the resistor three R3 is connected with the output end Y of the OR gate logic chip U3, and the other end of the resistor three R3 is used for being connected with the reset signal input end of the CPU.
Preferably: the first logic chip U1 is an AiP74HC24tta.
Preferably: the watchdog chip U2 is a TPV6823S-TR chip.
A watchdog control method of a relay protection device for preventing a startup card from being dead comprises the following steps:
the first resistor R1 is connected with an enable signal CPU-WDI-EN pin of the CPU, and the A1 pin of the first logic chip U1 is connected with a dog feeding signal CPU-WDI pin of the CPU.
The first input end A of the OR gate logic chip U3 is connected with a RESET signal output pin RESET of the watchdog chip U2, the second input end B is connected with a jumper cap J1 and is pulled down to a low level through a second resistor R2, and the output end Y of the OR gate logic chip U3 is connected with a third resistor R3 in series and is connected with the RESET signal input end of the CPU.
The DIR pin of the first logic chip U1 is connected to VCC high level, and the signal direction of the first control logic chip U1 is transmitted from the side of chip A to the side of chip B. An OE pin of the first logic chip U1 is an enable pin of the chip, the CPU controls chip enabling by adopting a low level, the enable pin is pulled up to a high level through a first resistor R1, it is ensured that the first logic chip U1 is not enabled in the loading process of CPU software, all pins on the B side of the first logic chip U1 are in a high-impedance state at the moment, a pin B1 of the first logic chip U1 is connected to a dog feeding signal input end WDI of a watchdog chip U2, and the high-impedance state of a pin U1B1 of the first logic chip U2 enables the watchdog chip U2 to be in an inoperative state, so that a RESET signal output pin RESET of the watchdog chip U2 cannot output a RESET signal.
When the jumper J1 is plugged in, the second input terminal B of the or gate logic chip U3 is at a high level, and since the or gate logic chip U3 adopts or gate logic, no matter whether the watchdog chip U2 is feeding a dog or not, the output terminal Y of the or gate logic chip U3 is at a high level, which will not cause CPU reset.
When the jumper J1 is not plugged, the second input terminal B of the or gate logic chip U3 is at a low level, and the state of the output terminal Y of the or gate logic chip U3 is consistent with the RESET signal output pin RESET of the watchdog chip U2U 2. When the CPU is in the software loading process, the enable pin OE of the first logic chip U1 is pulled up to a high level through the first resistor R1, the first logic chip U1 is not enabled, the pin B1 of the first logic chip U1 is in a high-impedance state, the watchdog chip U2 does not work, the RESET signal output pin RESET of the watchdog chip U2 outputs a high level, the output end Y of the gate logic chip U3 also outputs a high level, and the CPU cannot be RESET. When the CPU software normally runs, if the enable signal CPU-WDI-EN pin of the CPU outputs high level, the logic chip one U1 is not enabled, and the CPU is not reset. When CPU software normally runs, if an enable signal CPU-WDI-EN pin of a CPU outputs a low level, a chip logic chip I U1 is enabled, at the moment, a dog feeding signal CPU-WDI pin of the CPU must output a matched dog feeding signal to ensure that a RESET output signal of a RESET signal output pin of a watchdog chip U2 keeps a high level state all the time, if a CPU program is in 'running' or 'dead halt', the dog feeding signal is overtime, the watchdog chip U2 outputs a low level RESET signal to an input end I A of an OR logic chip, and an output end Y of the OR logic chip outputs a low level to the RESET signal input end of the CPU to RESET and restart the CPU.
Compared with the prior art, the invention has the following beneficial effects:
the invention not only has the stability of the hardware watchdog, but also has the control flexibility of the hardware watchdog.
Drawings
Fig. 1 is a schematic structural diagram of a design method of a watchdog of a relay protection device for preventing a startup jam according to the present invention;
fig. 2 is a circuit diagram of a design method of a watchdog of a relay protection device for preventing a startup jam according to the present invention.
Detailed Description
The present invention is further illustrated by the following description in conjunction with the accompanying drawings and the specific embodiments, it is to be understood that these examples are given solely for the purpose of illustration and are not intended as a definition of the limits of the invention, since various equivalent modifications will occur to those skilled in the art upon reading the present invention and fall within the limits of the appended claims.
The utility model provides a prevent dead relay protection device watchdog control circuit of start-up card, as shown in figure 1, includes software enable control module, watchdog chip module, hardware enable control module, wherein:
the software enabling control module is used for generating an enabling CPU dog feeding signal according to a CPU crash signal of the relay protection device and sending the enabling CPU dog feeding signal to the watchdog chip module.
The watchdog chip module is used for generating an initial reset signal according to the enabled CPU dog feeding signal and sending the initial reset signal to the hardware enabling control module.
The hardware enabling control module is used for receiving an initial reset signal sent by the watchdog chip module, receiving CPU operation information sent by a CPU of the relay protection device and a signal for starting to feed dogs. And judging whether the initial reset signal is effective or not according to the initial reset signal and the CPU operation information. If the initial reset signal is effective, the reset signal is sent to the CPU according to the starting dog feeding signal, when the watchdog signal is controlled to be effective, the CPU can select whether to start feeding the dog or not through the software control enabling circuit, and the situation that the reset signal is repeatedly output by a watchdog chip to cause the repeated resetting of the CPU or the locking of the starting-up of the relay protection device due to the fact that the CPU loading program is started for too long time is prevented. If the initial reset signal is invalid, the reset signal is not sent to the CPU, and when the watchdog signal is controlled to be invalid, the CPU is not reset no matter whether the CPU feeds the dog normally, so that the normal operation of a CPU board software development stage and a software debugging stage is facilitated. In the CPU board software development stage, the jumper cap is inserted into the hardware enabling control module, so that the device can be prevented from being reset by the watchdog, the device leaving the factory can have a normal watchdog function without being matched with the jumper cap, and the device is safer and more reliable.
As shown in fig. 2, the software enable control module includes a logic chip one U1, a resistor one R1, and a capacitor one C1, wherein one end of the resistor one R1 is used for being connected to an enable signal CPU-WDI-EN pin of the CPU, and the other end is connected to an enable pin OE of the logic chip one U1. A DIR pin of the first logic chip U1 is connected with a power supply voltage, a pin A1 of the first logic chip U1 is used for being connected with a feeding dog signal CPU-WDI pin of the CPU, a VCC pin of the first logic chip U1 is connected with the power supply voltage, a GND pin of the first logic chip U1 is grounded, one end of the first capacitor C1 is connected with the VCC pin of the first logic chip U1, the other end of the first capacitor C1 is connected with the GND pin of the first logic chip U1, and a pin B1 of the first logic chip U1 is connected with the watchdog chip module. The logic chip I1 adopts AiP74HC24tta.TB chip, and the software enabling control module ensures that after the CPU is powered on, in the software loading process, a pin B1 of the logic chip is in a high-resistance state, so that the watchdog chip is in an inoperative state, and the CPU cannot be reset. In the CPU software debugging stage, the control circuit can be enabled through the IO pin control software, so that a pin B1 of a logic chip of the circuit is in a high-resistance state, and even if the CPU performs software simulation or single-step debugging and the like, a dog feeding signal is not sent, the CPU is not reset. The dog feeding signal is not provided directly by the CPU but by the software enabled control circuit.
The watchdog chip module comprises a watchdog chip U2 and a capacitor II C2, wherein a feeding dog signal input end WDI of the watchdog chip U2 is connected with a pin B1 of a logic chip I1, a VCC pin of the watchdog chip U2 is connected with a power supply voltage, a GND pin of the watchdog chip U2 is grounded, one end of the capacitor II C2 is connected with the VCC pin of the watchdog chip U2, the other end of the capacitor II C2 is connected with the GND pin of the watchdog chip U2, and a RESET signal output pin RESET of the watchdog chip U2 is connected with the hardware enable control module. The watchdog chip U2 adopts a TPV6823S-TR chip. The reset signal output by the watchdog chip module is not directly connected to the reset signal of the device, but is provided to the hardware enabling control module.
The hardware enabling control module comprises an OR gate logic chip U3, a resistor II R2, a resistor III R3 and a capacitor III C3, wherein an input end A of the OR gate logic chip U3 is connected with a RESET signal output pin RESET of a watchdog chip U2, and an input end II B of the OR gate logic chip U3 is used for being connected with a jumper cap J1. The VCC pin of the OR gate logic chip U3 is connected with a power supply voltage, the GND pin of the OR gate logic chip U3 is grounded, one end of the capacitor tri C3 is connected with the VCC pin of the OR gate logic chip U3, and the other end of the capacitor tri C3 is connected with the GND pin of the OR gate logic chip U3. One end of the resistor three R3 is connected with the output end Y of the OR gate logic chip U3, and the other end of the resistor three R3 is used for being connected with the reset signal input end of the CPU. The hardware enabling control module receives a reset signal of the watchdog chip and can enable the reset signal to be invalid through hardware jumper design. Hardware enables control module, pulls out the wire jumper cap, and the watchdog reset signal is effective for this wire jumper cap of device that dispatches from the factory need not dispose installation, has avoided jolting in the transportation, the easy insecure drawback that becomes flexible of wire jumper cap. When the outgoing line software of the CPU board of the device has a fault, the jumper cap is inserted, so that the reset signal of the watchdog can be invalid, the CPU is not always reset, and the signal measurement and the software problem positioning are facilitated. When the hardware enabling control module controls the watchdog signal to be effective, the CPU can control the enabling circuit through software to select whether to start feeding the watchdog or not, and the situation that the watchdog chip repeatedly outputs a reset signal to cause the repeated resetting of the CPU or the startup blocking of the relay protection device due to the fact that the CPU loading program is started for too long time is prevented. The hardware enabling control module controls the watchdog signal to be invalid, and the CPU can not be reset no matter whether the CPU feeds the watchdog normally, so that the normal operation of a CPU board software development stage and a software debugging stage is facilitated.
A watchdog control method of a relay protection device for preventing a startup card from being dead comprises the following steps:
the first resistor R1 is connected with an enable signal CPU-WDI-EN pin of the CPU, and the A1 pin of the first logic chip U1 is connected with a dog feeding signal CPU-WDI pin of the CPU.
The first input end A of the OR gate logic chip U3 is connected with a RESET signal output pin RESET of the watchdog chip U2, the second input end B is connected with a jumper cap J1 and is pulled down to a low level through a second resistor R2, and the output end Y of the OR gate logic chip U3 is connected with a third resistor R3 in series and is connected with the RESET signal input end of the CPU.
The DIR pin of the first logic chip U1 is the direction control pin of the chip, and is connected to VCC high level, and the signal direction for controlling the first logic chip U1 is transmitted from the side of the chip A to the side of the chip B. An I/O port of a CPU is connected with an OE pin of a U1, the OE pin of a first logic chip U1 is an enable pin of the chip, the CPU controls chip enable by adopting a low level, the enable pin is pulled up to a high level through a first resistor R1, it is ensured that the first logic chip U1 is not enabled in the loading process of CPU software, all pins of a B side of the first logic chip U1 are in a high-resistance state at the moment, a pin B1 of the first logic chip U1 is connected to a dog feeding signal input end WDI of a watchdog chip U2, and a pin U1B1 is in a high-resistance state, so that the watchdog chip U2 is in an off-work state, and a RESET signal output pin RESET of the watchdog chip U2 cannot output a RESET signal.
When the jumper J1 is plugged in, the second input terminal B of the or gate logic chip U3 is at a high level, and since the or gate logic chip U3 adopts or gate logic, no matter whether the watchdog chip U2 is feeding a dog or not, the output terminal Y of the or gate logic chip U3 is at a high level, which will not cause CPU reset.
When the jumper J1 is not plugged, the second input terminal B of the or gate logic chip U3 is at a low level, and the state of the output terminal Y of the or gate logic chip U3 is consistent with the RESET signal output pin RESET of the watchdog chip U2U 2. When the CPU is in the software loading process, the enable pin OE of the first logic chip U1 is pulled up to a high level through the first resistor R1, the first logic chip U1 is not enabled, the pin B1 of the first logic chip U1 is in a high-impedance state, the watchdog chip U2 does not work, the RESET signal output pin RESET of the watchdog chip U2 outputs a high level, the output end Y of the gate logic chip U3 also outputs a high level, and the CPU cannot be RESET. When the CPU software normally runs, if the enable signal CPU-WDI-EN pin (I/O pin) of the CPU outputs high level, the logic chip one U1 is not enabled and the CPU will not reset as in the above case. When CPU software normally runs, if an enable signal CPU-WDI-EN pin (I/O pin) of a CPU outputs a low level, a chip logic chip I U1 is enabled, at the moment, a dog feeding signal CPU-WDI pin (I/O pin) of the CPU must output a matched dog feeding signal to ensure that a RESET signal output pin RESET output signal of a watchdog chip U2 keeps a high level state all the time, if a CPU program runs away or crashes, the dog feeding signal is overtime, the watchdog chip U2 outputs a low level RESET signal to an input end A of an OR logic chip, and an output end Y of the OR logic chip outputs a low level to a RESET signal input end of the CPU to RESET and restart the CPU.
The above description is only of the preferred embodiments of the present invention, and it should be noted that: it will be apparent to those skilled in the art that various modifications and adaptations can be made without departing from the principles of the invention and these are intended to be within the scope of the invention.
Claims (7)
1. The utility model provides a prevent dead relay protection device watchdog control circuit of start-up card which characterized in that: the system comprises a software enabling control module, a watchdog chip module and a hardware enabling control module, wherein the hardware enabling control module is connected with the watchdog chip module;
the software enabling control module is used for generating an enabling CPU dog feeding signal according to a CPU crash signal of the relay protection device and sending the enabling CPU dog feeding signal to the watchdog chip module;
the watchdog chip module is used for generating an initial reset signal according to the enabled CPU dog feeding signal and sending the initial reset signal to the hardware enabling control module;
the hardware enabling control module is used for receiving an initial reset signal sent by the watchdog chip module, receiving CPU operation information sent by a CPU of the relay protection device and a signal for starting to feed dogs; judging whether the initial reset signal is effective or not according to the initial reset signal and the CPU operation information; if the initial reset signal is effective, sending a reset signal to the CPU according to the start dog feeding signal; if the initial reset signal is invalid, the reset signal is not transmitted to the CPU.
2. The protection relay device watchdog control circuit of claim 1, wherein: the software enabling control module comprises a logic chip I1, a resistor I R1 and a capacitor I C1, wherein one end of the resistor I R1 is used for being connected with an enabling signal CPU-WDI-EN pin of the CPU, and the other end of the resistor I R1 is connected with an enabling pin OE of the logic chip I U1; a DIR pin of the first logic chip U1 is connected with a power supply voltage, a pin A1 of the first logic chip U1 is used for being connected with a feeding dog signal CPU-WDI pin of the CPU, a VCC pin of the first logic chip U1 is connected with the power supply voltage, a GND pin of the first logic chip U1 is grounded, one end of the first capacitor C1 is connected with the VCC pin of the first logic chip U1, the other end of the first capacitor C1 is connected with the GND pin of the first logic chip U1, and a pin B1 of the first logic chip U1 is connected with the watchdog chip module.
3. The protection relay device watchdog control circuit of claim 2, wherein: the watchdog chip module comprises a watchdog chip U2 and a capacitor II C2, wherein a feeding dog signal input end WDI of the watchdog chip U2 is connected with a pin B1 of a logic chip I1, a VCC pin of the watchdog chip U2 is connected with a power supply voltage, a GND pin of the watchdog chip U2 is grounded, one end of the capacitor II C2 is connected with the VCC pin of the watchdog chip U2, the other end of the capacitor II C2 is connected with the GND pin of the watchdog chip U2, and a RESET signal output pin RESET of the watchdog chip U2 is connected with the hardware enable control module.
4. The protection device watchdog control circuit of claim 3, wherein: the hardware enabling control module comprises an OR gate logic chip U3, a resistor II R2, a resistor III R3 and a capacitor III C3, wherein an input end A of the OR gate logic chip U3 is connected with a RESET signal output pin RESET of a watchdog chip U2, and an input end II B of the OR gate logic chip U3 is used for being connected with a jumper cap J1; the VCC pin of the OR gate logic chip U3 is connected with a power supply voltage, the GND pin of the OR gate logic chip U3 is grounded, one end of the capacitor tri C3 is connected with the VCC pin of the OR gate logic chip U3, and the other end of the capacitor tri C3 is connected with the GND pin of the OR gate logic chip U3; one end of the resistor three R3 is connected with the output end Y of the OR gate logic chip U3, and the other end of the resistor three R3 is used for being connected with the reset signal input end of the CPU.
5. The protection relay device watchdog control circuit of claim 1, wherein: the first logic chip U1 is an AiP74HC24tta.
6. The protection relay device watchdog control circuit of claim 1, wherein: the watchdog chip U2 is a TPV6823S-TR chip.
7. The control method of the watchdog control circuit of the relay protection device for preventing the startup jam as recited in claim 4, comprising the following steps:
connecting a resistor I R1 with an enable signal CPU-WDI-EN pin of a CPU, and connecting an A1 pin of a logic chip I U1 with a dog feeding signal CPU-WDI pin of the CPU;
an input end A of the OR gate logic chip U3 is connected with a RESET signal output pin RESET of the watchdog chip U2, an input end B is connected with a jumper cap J1 and is pulled down to a low level through a resistor II R2, and an output end Y of the OR gate logic chip U3 is connected with a resistor III R3 in series and is connected with a RESET signal input end of the CPU;
the DIR pin of the first logic chip U1 is connected to VCC high level, and the signal direction of the first logic chip U1 is controlled to be transmitted from the side of the chip A to the side of the chip B; an OE pin of the first logic chip U1 is an enable pin of the chip, the CPU controls the chip to enable by adopting a low level, the enable pin is pulled up to a high level through a first resistor R1, so that the first logic chip U1 is ensured not to be enabled in the loading process of CPU software, all pins at the B side of the first logic chip U1 are in a high-impedance state at the moment, a pin B1 of the first logic chip U1 is connected to a dog feeding signal input end WDI of a watchdog chip U2, and the high-impedance state of a pin U1B1 of the first logic chip U2 enables the watchdog chip U2 to be in an inoperative state, so that a RESET signal output pin RESET of the watchdog chip U2 cannot output a RESET signal;
when the jumper J1 is plugged in, the second input end B of the OR gate logic chip U3 is at a high level, and because the OR gate logic chip U3 adopts OR gate logic, no matter whether the watchdog chip U2 feeds a dog or not, the output end Y of the OR gate logic chip U3 is at a high level, so that the CPU is not reset;
when the jumper J1 is not plugged, the second input terminal B of the or gate logic chip U3 is at a low level, and at this time, the state of the output terminal Y of the or gate logic chip U3 is consistent with the RESET signal output pin RESET of the watchdog chip U2U 2; when the CPU is in the software loading process, an enable pin OE of a first logic chip U1 is pulled up to a high level through a first resistor R1, the first logic chip U1 is not enabled, a pin B1 of the first logic chip U1 is in a high-impedance state, a watchdog chip U2 does not work, a RESET signal output pin RESET of the watchdog chip U2 outputs the high level, an output end Y of the logic chip U3 also outputs the high level, and the CPU cannot be RESET; when the CPU software normally runs, if the enable signal CPU-WDI-EN pin of the CPU outputs high level, the logic chip I U1 is not enabled, and the CPU is not reset; when CPU software normally runs, if an enable signal CPU-WDI-EN pin of a CPU outputs a low level, a chip logic chip I U1 is enabled, at the moment, a dog feeding signal CPU-WDI pin of the CPU must output a matched dog feeding signal to ensure that a RESET output signal of a RESET signal output pin of a watchdog chip U2 keeps a high level state all the time, if a CPU program is in 'running' or 'dead halt', the dog feeding signal is overtime, the watchdog chip U2 outputs a low level RESET signal to an input end I A of an OR logic chip, and an output end Y of the OR logic chip outputs a low level to the RESET signal input end of the CPU to RESET and restart the CPU.
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| CN202110634703.XA CN113342151A (en) | 2021-06-08 | 2021-06-08 | Watchdog control circuit and control method of relay protection device for preventing startup from being locked |
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| CN202110634703.XA CN113342151A (en) | 2021-06-08 | 2021-06-08 | Watchdog control circuit and control method of relay protection device for preventing startup from being locked |
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| CN202110634703.XA Pending CN113342151A (en) | 2021-06-08 | 2021-06-08 | Watchdog control circuit and control method of relay protection device for preventing startup from being locked |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114336536A (en) * | 2022-03-03 | 2022-04-12 | 北京金橙子科技股份有限公司 | Safety protection method and safety protection circuit for control signal |
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| CN105892607A (en) * | 2016-04-01 | 2016-08-24 | 上海斐讯数据通信技术有限公司 | Circuit and method for preventing switch from being repetitively reset |
| CN108415791A (en) * | 2018-02-02 | 2018-08-17 | 上海康斐信息技术有限公司 | A kind of watchdog circuit and control method |
| CN112416646A (en) * | 2020-12-09 | 2021-02-26 | 威创集团股份有限公司 | Watchdog control circuit and watchdog circuit |
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| CN202230469U (en) * | 2011-05-16 | 2012-05-23 | 中兴通讯股份有限公司 | Buffer and watchdog circuit system |
| CN105892607A (en) * | 2016-04-01 | 2016-08-24 | 上海斐讯数据通信技术有限公司 | Circuit and method for preventing switch from being repetitively reset |
| CN108415791A (en) * | 2018-02-02 | 2018-08-17 | 上海康斐信息技术有限公司 | A kind of watchdog circuit and control method |
| CN112416646A (en) * | 2020-12-09 | 2021-02-26 | 威创集团股份有限公司 | Watchdog control circuit and watchdog circuit |
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| CN114336536A (en) * | 2022-03-03 | 2022-04-12 | 北京金橙子科技股份有限公司 | Safety protection method and safety protection circuit for control signal |
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