CN111914497A - DSP core module fault recovery method - Google Patents
DSP core module fault recovery method Download PDFInfo
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- CN111914497A CN111914497A CN202010552201.8A CN202010552201A CN111914497A CN 111914497 A CN111914497 A CN 111914497A CN 202010552201 A CN202010552201 A CN 202010552201A CN 111914497 A CN111914497 A CN 111914497A
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- 238000000034 method Methods 0.000 title claims abstract description 16
- 238000011084 recovery Methods 0.000 title claims abstract description 13
- 238000012544 monitoring process Methods 0.000 claims abstract description 6
- 241000282472 Canis lupus familiaris Species 0.000 claims description 7
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
- G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
- G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
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Abstract
The invention provides a fault recovery method for a DSP core module, which enables the DSP to have the functions of VCC power supply monitoring, application and debugging module switching, multi-core fault recovery and reset control of an external circuit. The invention can improve the stability and reliability of circuit design by adopting the fault recovery mechanism, realizes that the DSP can be recovered under the conditions of DSP starting process, power supply abnormity, any DSP core abnormity and the like, and ensures the normal work of the module.
Description
Technical Field
The invention relates to the field of circuit design, in particular to a fault recovery mechanism of a DSP (digital signal processor), especially a multi-core DSP (digital signal processor).
Background
The increase of application of the DSP, particularly the multi-core DSP, has higher failure rate of the DSP when a task multi-system is more responsible or is subjected to stress test. The method for introducing the CPLD or the FPGA to realize the dog feeding of the watchdog chip in the power-on process for realizing fault recovery causes more DSP peripheral circuits. Alternatively, a max706 watchdog or the like is adopted, so that the watchdog function is not used, and only the power-on reset and power monitoring functions are reserved. This may result in failure of the DSP chip to recover during power-up.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention provides a fault recovery method for a DSP core module, so that the DSP has the functions of VCC power supply monitoring, application and debugging module switching, multi-core fault recovery and reset control of an external circuit.
The technical scheme adopted by the invention for solving the technical problem comprises the following detailed steps:
step 1: before power-on, selecting a debugging mode or a working mode, grounding the GSE signal when the debugging mode is selected, and suspending the GSE signal when the working mode is selected; in the power-on process, when the monitoring VCC power supply reaches a threshold level, triggering a power-on reset signal, resetting the DSP and loading a program;
step 2: after electrification, judging whether the GSE is grounded, if the GSE is grounded, entering a debugging mode of the step 3, and if the GSE is not grounded, entering a working mode of the step 4;
and step 3: in a debugging mode, the GSE signal controls an SET signal of a watchdog chip, the watchdog does not work through an MOS (metal oxide semiconductor) tube, or the watchdog is SET to output reset pulse time which is longer than software program burning time and enters debugging or program burning; in the state, after the external reset MR outputs an effective reset signal, the DSP resets and reloads the program, so that the DSP is reset and reloaded by the outside;
and 4, step 4: in the working mode, if the DSP cannot be loaded and started normally, the watchdog starts overtime reset to reload the program for the DSP; if the DSP is normally loaded and started, setting the reset time of the watchdog, wherein the watchdog time interval after the DSP is set ensures that the DSP is recovered in the shortest time after the DSP fails, and the DSP feeds the watchdog through a WDI signal; if the DSP feeds dogs normally, the DSP works normally and continuously and circularly detects whether the DSP feeds dogs; in this state, after the external reset MR outputs an effective reset signal, the DSP resets and reloads the program, thereby implementing the control of resetting and reloading the DSP from the outside.
Furthermore, when the multi-core DSP is applied, if the DSP core is not internally communicated, the cores of the GPIO are controlled to increase the number of the watchdog, the output of the watchdog is connected to the input of the AND gate, and when any core fails, the DSP can recover.
Further, if the DSP is provided with an internal watchdog, the internal watchdog is started, and if the core of the internal watchdog of the DSP fails, WDOUT is output to an AND gate to control POR, and the software is reloaded.
Furthermore, a plurality of external reset inputs MR are connected with the AND gate to support the hot reset control of a plurality of reset sources to the DSP.
Furthermore, GPIO or other reset functional pins of the DSP control the reset of the peripheral chip circuit.
The invention has the beneficial effect that the stability and the reliability of the circuit design can be improved due to the adoption of the fault recovery mechanism. The DSP can be recovered under the conditions of DSP starting process, power supply abnormity, any DSP core abnormity and the like, and the normal work of the module is ensured.
Drawings
Fig. 1 is a circuit diagram of the recovery system according to the present invention.
Fig. 2 is a flow chart of the operation of the recovery system of the present invention.
Detailed Description
The invention is further illustrated with reference to the following figures and examples.
As shown in fig. 1 and 2, the operation is divided into two states, namely a normal operation mode and a debugging mode.
Step 1: before power-on, selecting a debugging mode or a working mode, grounding the GSE signal when the debugging mode is selected, and suspending the GSE signal when the working mode is selected; in the power-on process, when the monitoring VCC power supply reaches a threshold level, triggering a power-on reset signal, resetting the DSP and loading a program;
step 2: after electrification, judging whether the GSE is grounded, if the GSE is grounded, entering a debugging mode of the step 3, and if the GSE is not grounded, entering a working mode of the step 4;
and step 3: in a debugging mode, the GSE signal controls an SET signal of a watchdog chip, the watchdog does not work through an MOS (metal oxide semiconductor) tube, or the watchdog is SET to output reset pulse time which is longer than software program burning time and enters debugging or program burning; in the state, after the external reset MR outputs an effective reset signal, the DSP resets and reloads the program, so that the DSP is reset and reloaded by the outside;
and 4, step 4: in the working mode, if the DSP cannot be loaded and started normally, the watchdog starts overtime reset to reload the program for the DSP; if the DSP is normally loaded and started, setting the reset time of the watchdog, wherein the watchdog time interval after the DSP is set ensures that the DSP is recovered in the shortest time after the DSP fails, and the DSP feeds the watchdog through a WDI signal; if the DSP feeds dogs normally, the DSP works normally and continuously and circularly detects whether the DSP feeds dogs; in the state, after the external reset MR outputs an effective reset signal, the DSP resets and reloads the program, so that the DSP is reset and reloaded by the outside;
furthermore, when the multi-core DSP is applied, if the DSP core is not internally communicated, the cores of the GPIO are controlled to increase the number of the watchdog, the output of the watchdog is connected to the input of the AND gate, and when any core fails, the DSP can be recovered;
further, if the DSP is provided with an internal watchdog, the internal watchdog is started, and if the core of the internal watchdog of the DSP fails, WDOUT is output to an AND gate to control POR, and the software is reloaded.
Furthermore, a plurality of external reset inputs MR are connected with the AND gate to support the hot reset control of a plurality of reset sources to the DSP;
furthermore, GPIO or other reset functional pins of the DSP control the reset of the peripheral chip circuit.
Claims (5)
1. A fault recovery method for a DSP core module is characterized by comprising the following steps:
step 1: before power-on, selecting a debugging mode or a working mode, grounding the GSE signal when the debugging mode is selected, and suspending the GSE signal when the working mode is selected; in the power-on process, when the monitoring VCC power supply reaches a threshold level, triggering a power-on reset signal, resetting the DSP and loading a program;
step 2: after electrification, judging whether the GSE is grounded, if the GSE is grounded, entering a debugging mode of the step 3, and if the GSE is not grounded, entering a working mode of the step 4;
and step 3: in a debugging mode, the GSE signal controls an SET signal of a watchdog chip, the watchdog does not work through an MOS (metal oxide semiconductor) tube, or the watchdog is SET to output reset pulse time which is longer than software program burning time and enters debugging or program burning; in the state, after the external reset MR outputs an effective reset signal, the DSP resets and reloads the program, so that the DSP is reset and reloaded by the outside;
and 4, step 4: in the working mode, if the DSP cannot be loaded and started normally, the watchdog starts overtime reset to reload the program for the DSP; if the DSP is normally loaded and started, setting the reset time of the watchdog, wherein the watchdog time interval after the DSP is set ensures that the DSP is recovered in the shortest time after the DSP fails, and the DSP feeds the watchdog through a WDI signal; if the DSP feeds dogs normally, the DSP works normally and continuously and circularly detects whether the DSP feeds dogs; in this state, after the external reset MR outputs an effective reset signal, the DSP resets and reloads the program, thereby implementing the control of resetting and reloading the DSP from the outside.
2. The method for recovering the fault of the DSP core module according to claim 1, wherein:
when the multi-core DSP is applied, if no communication exists in the DSP core, the cores of the GPIO are controlled to increase the number of the watchdog, the output of the watchdog is connected to the input of the AND gate, and when any core breaks down, the DSP can recover.
3. The method for recovering the fault of the DSP core module according to claim 1, wherein:
if the DSP has the internal watchdog, the internal watchdog is started, and if the core of the internal watchdog of the DSP fails, WDOUT is output to an AND gate to control POR, and the software is reloaded.
4. The method for recovering the fault of the DSP core module according to claim 1, wherein:
and the plurality of external reset inputs MR are connected with the AND gate to support the hot reset control of the plurality of reset sources to the DSP.
5. The method for recovering the fault of the DSP core module according to claim 1, wherein:
GPIO or other reset function pins of the DSP control the reset of the peripheral chip circuit.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010552201.8A CN111914497B (en) | 2020-06-17 | 2020-06-17 | DSP core module fault recovery method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114116271A (en) * | 2021-10-08 | 2022-03-01 | 飞思未来(深圳)科技有限公司 | Watchdog circuit and embedded industrial equipment |
| CN115167651A (en) * | 2022-09-05 | 2022-10-11 | 北京紫光芯能科技有限公司 | Load balancing circuit and system for multi-core SOC reset |
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| JPH0612294A (en) * | 1992-06-26 | 1994-01-21 | Sekisui Chem Co Ltd | Monitor device |
| CN2713538Y (en) * | 2004-06-09 | 2005-07-27 | 港湾网络有限公司 | Watchdog control circuit |
| KR20050078829A (en) * | 2004-02-03 | 2005-08-08 | 엘지이노텍 주식회사 | Reset circuit |
| CN102360315A (en) * | 2011-09-30 | 2012-02-22 | 中国航空工业集团公司第六三一研究所 | Management method of watchdog circuit of fault-tolerant control system |
| CN102681907A (en) * | 2012-02-06 | 2012-09-19 | 北京广利核系统工程有限公司 | Multifunctional watchdog circuit |
| CN103744754A (en) * | 2014-01-26 | 2014-04-23 | 上海交通大学 | Radiation resistance and reinforcement parallel on-board computer system and use method thereof |
| CN104331341A (en) * | 2014-11-24 | 2015-02-04 | 中国航空工业集团公司洛阳电光设备研究所 | FPGA (field programmable gate array)-based failure recovery method |
| CN105068880A (en) * | 2015-08-17 | 2015-11-18 | 上海斐讯数据通信技术有限公司 | Device resetting method based on watchdog |
-
2020
- 2020-06-17 CN CN202010552201.8A patent/CN111914497B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH0612294A (en) * | 1992-06-26 | 1994-01-21 | Sekisui Chem Co Ltd | Monitor device |
| KR20050078829A (en) * | 2004-02-03 | 2005-08-08 | 엘지이노텍 주식회사 | Reset circuit |
| CN2713538Y (en) * | 2004-06-09 | 2005-07-27 | 港湾网络有限公司 | Watchdog control circuit |
| CN102360315A (en) * | 2011-09-30 | 2012-02-22 | 中国航空工业集团公司第六三一研究所 | Management method of watchdog circuit of fault-tolerant control system |
| CN102681907A (en) * | 2012-02-06 | 2012-09-19 | 北京广利核系统工程有限公司 | Multifunctional watchdog circuit |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114116271A (en) * | 2021-10-08 | 2022-03-01 | 飞思未来(深圳)科技有限公司 | Watchdog circuit and embedded industrial equipment |
| CN114116271B (en) * | 2021-10-08 | 2023-10-20 | 飞思未来(深圳)科技有限公司 | Watchdog circuit and embedded industrial equipment |
| CN115167651A (en) * | 2022-09-05 | 2022-10-11 | 北京紫光芯能科技有限公司 | Load balancing circuit and system for multi-core SOC reset |
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| CN111914497B (en) | 2024-04-09 |
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