CN115167651A - Load balancing circuit and system for multi-core SOC reset - Google Patents

Abstract

The application provides a load balancing circuit and a load balancing system for multi-core SOC reset, which can be applied to the technical field of system-level chip SOC debugging. The circuit comprises a control circuit, a first load circuit, a second load circuit, a control point and a protection circuit; the control circuit controls the second load circuit to be not conducted when the debugging signal is invalid and/or the CPU operation signal is invalid, and to be conducted when the CPU is switched from the operation state to the reset state at the same time. Through setting up the second load circuit, utilize control circuit control the second load circuit switches on when CPU is by the running state switch to reset state simultaneously, utilize the effect of second load circuit performance spare load when a plurality of CPUs reset simultaneously, avoid a plurality of CPUs to reset the load sudden change that causes simultaneously, and then avoid output voltage to appear the phenomenon of uprush.

Description

A load balancing circuit and system for multi-core SOC reset

technical field

The present application relates to the technical field of SOC debugging, and in particular, to a load balancing circuit and system for resetting a multi-core SOC.

Background technique

CPU is the English abbreviation of Central Processing Unit (Central Processing Unit). It has the ability to control and process information and is the control center of computers and smart devices. If the packaging and auxiliary circuits (such as pin interface circuits, power supply circuits and clock circuits, etc.) in the traditional CPU chip are excluded, only the core circuits that complete the control and information processing functions are retained. This part of the circuit is the CPU core, also referred to as CPU core. A CPU core is basically a completely independent processor that can read instructions from internal memory and perform control and computational tasks specified by the instructions.

If a CPU core and related auxiliary circuits are packaged in one chip, the chip is a traditional single-core CPU chip, or single-core CPU for short. If multiple CPU cores and related auxiliary circuits are packaged in one chip, the chip is a multi-core CPU chip, abbreviated as a multi-core CPU. If some other functional components and interface circuits are integrated into the multi-core CPU chip to form a complete system, then the chip becomes a multi-core SOC chip, referred to as a multi-core SOC.

A multi-core SOC chip integrates multiple CPUs inside to meet the growing demand for computing power. In the process of debugging the CPU, if each core CPU cannot be individually reset and controlled, it is usually only possible to reset all the normal running core CPUs at the same time. Simultaneous reset of multi-core CPUs means a sudden change in the load, which will cause the output voltage to appear. Overshoot, severe voltage overshoot will lead to a series of unpredictable consequences.

SUMMARY OF THE INVENTION

In view of this, embodiments of the present application provide a load balancing circuit and system for resetting a multi-core SOC, aiming to solve the problem of overshoot of output voltage caused by simultaneous resetting of multi-core CPUs in the prior art.

In a first aspect, an embodiment of the present application provides a load balancing circuit for multi-core SOC reset, the circuit includes: the circuit includes: a control circuit, a first load circuit, a second load circuit, a control point, and a protection circuit;

The output end of the control circuit is connected to the control point; the output end of the first load circuit is connected to the control point; the input end of the second load circuit is connected to the control point; the protection circuit connected to the control point;

The control circuit controls the second load circuit to be non-conductive when the first load circuit is in a first state, and to be turned on when the first load circuit is in a second state; the first state is that the CPU is running The signal is invalid and/or the debug signal is invalid, and the second state is that the debug signal is valid, the CPU running signal is valid, and the reset signal is valid;

The protection circuit provides protection for the load balancing circuit of the multi-core SOC reset;

The control circuit, the first load circuit, the second load circuit, the control point and the protection circuit are used to control the load balance during multi-core SOC debugging.

Optionally, the second load circuit includes a first N-channel power MOS transistor and a first resistor, the first resistor is connected to the source of the first N-channel power MOS transistor, and the first N-channel power MOS transistor is connected. The drain of the channel power MOS transistor is connected to the power supply; the gate of the first N-channel power MOS transistor is connected to the control point.

Optionally, the control circuit includes a P-channel power MOS transistor, a second resistor and a third resistor;

The gate of the P-channel power MOS transistor is input with a reset signal and is connected to the third resistor, the drain of the P-channel power MOS transistor is connected to the control point, and the P-channel power MOS transistor is connected to the control point. The source is connected to the second resistor;

An external power supply is connected to the second resistor and the third resistor.

Optionally, the first load circuit includes a NAND gate device and a second N-channel power MOS transistor;

The debug signal is input to the first end of the NAND gate device, and the CPU operation signal is input to the second end;

The gate of the second N-channel power MOS transistor is connected to the output end of the NAND device, the drain of the second N-channel power MOS transistor is connected to the control point, and the second N-channel power MOS transistor is connected to the control point. The source of the channel power MOS transistor is grounded.

Optionally, the protection circuit includes a fourth resistor and a capacitor, the fourth resistor is connected to the control point, and the fourth resistor is connected in parallel with the capacitor.

Optionally, the on-current of the first N-channel power MOS transistor is set within a preset range.

Optionally, the capacitor is used to control the equivalent resistance of the first N-channel power MOS transistor.

Optionally, according to the width of the reset signal, the running time of the second load circuit can be matched with the time required for CPU reset by adjusting the second resistance.

In a second aspect, an embodiment of the present application provides a load balancing system for resetting a multi-core SOC, including the load balancing circuit for resetting a multi-core SOC described above.

The embodiment of the present application provides a load balancing circuit for resetting a multi-core SOC. The circuit includes: a control circuit, a first load circuit, a second load circuit, a control point and a protection circuit; the output end of the control circuit is connected to the control point; the output end of the first load circuit is connected to the The input end of the second load circuit is connected to the control point; the protection circuit is connected to the control point; the control circuit controls the second load circuit when the first load circuit is in the Not conducting in the first state, and conducting when the first load circuit is in the second state; the first state is that the CPU running signal is invalid and/or the debugging signal is invalid, and the second state is the debugging signal is valid and the CPU running signal is valid; the protection circuit provides protection for the load balancing circuit of the multi-core SOC reset; using the control circuit, the first load circuit, the second load circuit, the control point and the protection circuit to control load balance during multi-core SOC debugging. By arranging the second load circuit, and using the control circuit to control the second load circuit to be turned on when the CPUs are switched from the running state to the reset state at the same time, the second load circuit can be used to play the role of a backup load when multiple CPUs are reset at the same time , to avoid the sudden change of load caused by the simultaneous reset of multiple CPUs, thereby avoiding the phenomenon of overshoot of the output voltage.

Description of drawings

In order to more clearly illustrate the technical solutions in the present embodiment or the prior art, the following briefly introduces the accompanying drawings required in the description of the embodiment or the prior art. Obviously, the accompanying drawings in the following description are only For some embodiments of the present application, for those of ordinary skill in the art, other drawings can also be obtained according to these drawings without any creative effort.

Fig. 1 is the scheme frame diagram that the embodiment of this application provides;

FIG. 2 is a load balancing circuit diagram of a multi-core SOC reset provided by an embodiment of the present application.

Detailed ways

CPU is the English abbreviation of Central Processing Unit (Central Processing Unit). It has the ability to control and process information and is the control center of computers and smart devices. If the packaging and auxiliary circuits (such as pin interface circuits, power supply circuits and clock circuits, etc.) in the traditional CPU chip are excluded, only the core circuits that complete the control and information processing functions are retained. This part of the circuit is the CPU core, also referred to as CPU core. A CPU core is basically a completely independent processor that can read instructions from internal memory and perform control and computational tasks specified by the instructions.

If a CPU core and related auxiliary circuits are packaged in one chip, the chip is a traditional single-core CPU chip, or single-core CPU for short. If multiple CPU cores and related auxiliary circuits are packaged in one chip, the chip is a multi-core CPU chip, abbreviated as a multi-core CPU. If some other functional components and interface circuits are integrated into the multi-core CPU chip to form a complete system, then the chip becomes a multi-core SOC chip, referred to as a multi-core SOC.

A multi-core SOC chip integrates multiple CPUs inside to meet the growing demand for computing power. In the process of debugging the CPU, if each core CPU cannot be individually reset and controlled, it is usually only possible to reset all the normal running core CPUs at the same time. Simultaneous reset of multi-core CPUs means a sudden change in the load, which will cause the output voltage to appear. Overshoot, severe voltage overshoot will lead to a series of unpredictable consequences.

At present, the load mutation caused by the simultaneous reset of the multi-core CPU, and then the voltage overshoot is caused. If a backup load circuit can be turned on during the simultaneous reset of the multi-core CPU, the load mutation can be avoided. The phenomenon of voltage overshoot occurs. Therefore, this proposal is proposed.

Referring to FIG. 1, FIG. 1 is a schematic diagram of a scheme provided by an embodiment of the present application. In the present application, a MOSFET tube is used as a backup load circuit, and the backup load circuit is controlled by a control circuit to be turned on when the CPU is switched from the running state to the reset state at the same time. When multiple CPUs are reset at the same time, the second load circuit is used to play the role of a backup load, so as to avoid the sudden change of the load caused by the simultaneous reset of the multiple CPUs, thereby avoiding the phenomenon of overshoot of the output voltage.

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

Referring to FIG. 2, FIG. 2 is a load balancing circuit diagram of a multi-core SOC reset provided by an embodiment of the present application. The application scenario of this circuit diagram may be a multi-core SOC chip testing multi-core CPU scenario. The circuit includes: a control circuit, a first load circuit , a second load circuit, a control point and a protection circuit. The control circuit is used to control the opening and closing of the second load circuit; the first load circuit is used to reflect the debugging state and the operating state of the CPU during debugging; the second load circuit is equivalent to a backup load circuit, and the first load circuit It is turned on when it is not working. In this scheme, it can be understood that the second load circuit is turned on during the process of resetting multiple CPUs at the same time; the control point is the node that inputs signals to the second load circuit; the protection circuit is to avoid the load circuit. A security failure has occurred.

The second load circuit includes a first N-channel power MOS transistor and a first resistor, the first N-channel power MOS transistor can be set as an N-channel power MOSFET transistor and set as Q1, the first resistor is set as R1, and R1 and The source 2 of Q1 is connected to the source 2, the drain 3 of Q1 is connected to the power supply VDD, the gate 1 of Q1 is connected to the control point, and the control point is used for inputting signals to control the turn-on and turn-off of the second load circuit.

The control circuit includes a P-channel power MOS transistor, a second resistor and a third resistor. The P-channel power MOS transistor is set as Q2, the second resistor and the third resistor are set as R2 and R3 respectively, and the gate input of Q2 is reset. Signal CPU_RESET, and the gate of Q2 is connected to R3, the drain of Q2 is connected to the control point, the source of Q2 is connected to R2, R2, R3 are connected in parallel, and the external power supply VEXT.

The first load circuit includes a NAND gate device and a second N-channel power MOS transistor, the NAND gate device is set as U1, and the second N-channel power MOS transistor is set as Q3; the first input of the NAND gate device The debug signal is input to the terminal. In this embodiment, the debug signal is used to represent the signal when a debugging fault occurs, and the signal is set as the DEBUG signal; the other input terminal of the NAND gate device inputs the running signal CPU_RUN of the multi-core CPU, and the output of the NAND gate The terminal is connected to the gate 1 of Q3. Only when the debug signal and the running signal of the multi-core CPU are valid, Q3 is turned on, and only when the debug signal and the running signal of the multi-core CPU are both valid, the second load circuit will be affected. Control of the reset signal. The drain 3 of Q3 is connected to the control point, and the source 2 of Q3 is grounded.

The protection circuit includes a fourth resistor and a capacitor, and the fourth resistor is set as R4, and the capacitor is set as C1; R4 is connected to the control point, and R4 is connected in parallel with C1.

The output end of the control circuit is connected with the control point; the output end of the first load circuit is connected with the control point; the input end of the second load circuit is connected with the control point; the protection circuit is connected with the control point; the control circuit controls the second load circuit to run on the CPU When the signal is invalid and/or the debugging signal is invalid, it is not turned on, and the first load circuit is turned on when the debugging signal is valid, the CPU running signal is valid, and the reset signal is valid; the protection circuit provides protection for the load balancing circuit of the multi-core SOC reset; The control circuit, the first load circuit, the second load circuit, the control point and the protection circuit are used to control the load balance during multi-core SOC debugging. The specific implementation process is as follows:

After the debugging starts, this embodiment is applied to the case where a failure occurs in the debugging process, that is, the case where the debugging signal DEBUG_EN is effectively at a high level.

In the embodiment of the present application, in order to avoid the phenomenon of sudden change of load during the simultaneous reset process of the multi-core CPU during operation, a NAND gate is set in the first load circuit, which is used only in the case of failure during the debugging process, that is, When the DEBUG signal is valid and the multi-core CPU is running, the reset signal enables the simultaneous reset operation of the multi-core CPU, so that a sudden change of load occurs. In this embodiment, the reset signal is enabled until the reset of the multi-core CPU is completed. The second load circuit is controlled to be turned on, that is, to be turned on when the first load circuit is not turned on, as a backup load circuit to avoid sudden load changes. For example, the second load circuit is controlled by the reset signal CPU_RESET only when the debug signal DEBUG_EN is active and the CPU is already running. Otherwise, U1 outputs a high level, the N-channel MOSFET transistor Q3 is turned on, the gate voltage of Q1 in the second load circuit is zero, and the second load circuit does not work.

Under the condition that the debug signal DEBUG_EN is valid and the CPU is running, when the reset signal CPU_RESET is triggered, it is generally a falling edge trigger, Q2 is turned on, and then Q1 in the second load circuit is saturated and turned on, the second load circuit starts to work, and the CPU The second load circuit stops operating when the reset is completed.

When the reset signal is triggered, that is, after the reset of the multi-core CPU is completed, due to the existence of the capacitor C1, the capacitor C1 can control the equivalent resistance of Q1 within the variable range, so the gate voltage of Q1 will not disappear immediately but Slowly falling, Q1 first leaves the saturated conduction area and enters the variable resistance area, and finally C1 is discharged and Q1 is turned off. Therefore the current flowing through the second load gradually drops to zero. In this way, it can also be realized that the second load circuit does not have a sudden load change.

The embodiment of the present application provides a load balancing circuit for resetting a multi-core SOC. The circuit includes: a control circuit, a first load circuit, a second load circuit, a control point and a protection circuit; the output end of the control circuit is connected to the control point; the output end of the first load circuit is connected to the The input end of the second load circuit is connected to the control point; the protection circuit is connected to the control point; the control circuit controls the second load circuit when the first load circuit is in the Not conducting in the first state, and conducting when the first load circuit is in the second state; the first state is that the CPU running signal is invalid and/or the debugging signal is invalid, and the second state is the debugging signal is valid and the CPU running signal is valid; the protection circuit provides protection for the load balancing circuit of the multi-core SOC reset; using the control circuit, the first load circuit, the second load circuit, the control point and the protection circuit to control load balance during multi-core SOC debugging. By arranging the second load circuit, and using the control circuit to control the second load circuit to be turned on when the CPUs are switched from the running state to the reset state at the same time, the second load circuit can be used to play the role of a backup load when multiple CPUs are reset at the same time , to avoid the sudden change of load caused by the simultaneous reset of multiple CPUs, thereby avoiding the phenomenon of overshoot of the output voltage.

In an optional embodiment of the present application, the first N-channel power MOS transistor in the second load circuit, that is, the on-current of Q1 in the embodiment needs to be set within a preset range. For example, the saturation conduction of Q1 can be designed. The passing current is about 70%-90% of the full load current of the CPU. The specific value setting depends on the specific circuit design, that is, the resistance value of R1.

In an optional embodiment of the present application, the reset signal CPU_RESET is generally valid at the falling edge, and the width of the reset signal is the time required for the reset process of the multi-core CPU. In this embodiment, the reset process of the multi-core CPU is equivalent to that the first load circuit stops working , the second load circuit needs to be turned on at this time, and after the reset of the multi-core CPU is completed, it is equivalent to the normal operation of the first load circuit, and the second load circuit does not need to work, so the second load circuit needs to be turned on. The time matches the width of the reset signal CPU_RESET, that is, the second load circuit is controlled to be turned on only during the reset process of the multi-core CPU, which can be achieved by adjusting R2. The larger R2 is, the longer the charging period of the capacitor C1 is, and the longer the delay time of the saturated conduction of Q1 is, so that the conduction time of the second load circuit can be matched with the width of the reset signal CPU_RESET.

On the basis of the foregoing embodiments, the embodiments of the present application further provide a load balancing system for resetting a multi-core SOC, including the above-mentioned load balancing circuit for resetting a multi-core SOC.

It should be noted that the load balancing system for multi-core SOC reset provided in this embodiment has the same beneficial effects as the load balancing circuit for multi-core SOC reset provided in the foregoing embodiment, and for the For the specific introduction of the load balancing circuit for resetting the multi-core SOC, please refer to the above-mentioned embodiment, which will not be repeated in this application.

The "first" and "second" in the names of "first load circuit" and "second load circuit" mentioned in the embodiments of this application are only used for name identification, and do not represent the first, second.

Each embodiment in this specification is described in a progressive manner, and the same and similar parts between the various embodiments may be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the circuit embodiment, the description is relatively simple, and for related parts, please refer to the partial description of the circuit embodiment. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution in this embodiment. Those of ordinary skill in the art can understand and implement it without creative effort.

The above descriptions are only exemplary embodiments of the present application, and are not intended to limit the protection scope of the present application.

Claims (9)

1. A load balancing circuit for multi-core SOC reset, wherein the circuit comprises: a control circuit, a first load circuit, a second load circuit, a control point and a protection circuit; The output end of the control circuit is connected to the control point; the output end of the first load circuit is connected to the control point; the input end of the second load circuit is connected to the control point; the protection circuit connected to the control point; The control circuit controls the second load circuit to be non-conductive when the first load circuit is in a first state, and to be turned on when the first load circuit is in a second state; the first state is that the CPU is running The signal is invalid and/or the debug signal is invalid, and the second state is that the debug signal is valid, the CPU running signal is valid, and the reset signal is valid; The protection circuit provides protection for the load balancing circuit of the multi-core SOC reset; The control circuit, the first load circuit, the second load circuit, the control point and the protection circuit are used to control the load balance during multi-core SOC debugging. 2 . The load balancing circuit for multi-core SOC reset according to claim 1 , wherein the second load circuit comprises a first N-channel power MOS transistor and a first resistor, and the first resistor is connected to the first N-channel power MOS transistor. 3 . The source of an N-channel power MOS transistor is connected, the drain of the first N-channel power MOS transistor is connected to the power supply, and the gate of the first N-channel power MOS transistor is connected to the control point. 3. The load balancing circuit for multi-core SOC reset according to claim 1, wherein the control circuit comprises a P-channel power MOS transistor, a second resistor and a third resistor; The gate of the P-channel power MOS transistor is input with a reset signal and is connected to the third resistor, the drain of the P-channel power MOS transistor is connected to the control point, and the P-channel power MOS transistor is connected to the control point. The source is connected to the second resistor; An external power supply is connected to the second resistor and the third resistor. 4. The load balancing circuit for multi-core SOC reset according to claim 1, wherein the first load circuit comprises a NAND gate device and a second N-channel power MOS transistor; The debug signal is input to the first end of the NAND gate device, and the CPU operation signal is input to the second end; The gate of the second N-channel power MOS transistor is connected to the output end of the NAND device, the drain of the second N-channel power MOS transistor is connected to the control point, and the second N-channel power MOS transistor is connected to the control point. The source of the channel power MOS transistor is grounded. 5 . The load balancing circuit for multi-core SOC reset according to claim 1 , wherein the protection circuit comprises a fourth resistor and a capacitor, the fourth resistor is connected to the control point, and the fourth resistor is connected to the control point. 6 . The capacitors are connected in parallel. 6 . The load balancing circuit for multi-core SOC reset according to claim 1 , wherein the on-current of the first N-channel power MOS transistor is set within a preset range. 7 . 7 . The load balancing circuit for multi-core SOC reset according to claim 4 , wherein the capacitor is used to control the equivalent resistance of the first N-channel power MOS transistor. 8 . 8 . The load balancing circuit for multi-core SOC reset according to claim 1 , wherein, according to the width of the reset signal, the matching between the running time of the second load circuit and the time required for CPU reset is realized by adjusting the second resistance. 9 . . 9 . A load balancing system for resetting a multi-core SOC, comprising the load balancing circuit for resetting a multi-core SOC according to any one of claims 1 to 8 . 10 .

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