CN115167651A - Load balancing circuit and system for multi-core SOC reset - Google Patents
Load balancing circuit and system for multi-core SOC reset Download PDFInfo
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- CN115167651A CN115167651A CN202211080066.7A CN202211080066A CN115167651A CN 115167651 A CN115167651 A CN 115167651A CN 202211080066 A CN202211080066 A CN 202211080066A CN 115167651 A CN115167651 A CN 115167651A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
- G06F1/305—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations in the event of power-supply fluctuations
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
- G06F11/2242—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors in multi-processor systems, e.g. one processor becoming the test master
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Abstract
The application provides a load balancing circuit and a load balancing system for multi-core SOC reset, which can be applied to the technical field of system-level chip SOC debugging. The circuit comprises a control circuit, a first load circuit, a second load circuit, a control point and a protection circuit; the control circuit controls the second load circuit to be not conducted when the debugging signal is invalid and/or the CPU operation signal is invalid, and to be conducted when the CPU is switched from the operation state to the reset state at the same time. Through setting up the second load circuit, utilize control circuit control the second load circuit switches on when CPU is by the running state switch to reset state simultaneously, utilize the effect of second load circuit performance spare load when a plurality of CPUs reset simultaneously, avoid a plurality of CPUs to reset the load sudden change that causes simultaneously, and then avoid output voltage to appear the phenomenon of uprush.
Description
Technical Field
The application relates to the technical field of SOC debugging, in particular to a load balancing circuit and system for multi-core SOC reset.
Background
The CPU is an english abbreviation of a Central Processing Unit (Central Processing Unit), has control and information Processing capabilities, and is a control center of a computer and intelligent equipment. If the package and auxiliary circuits (such as interface circuit of pins, power supply circuit and clock circuit) in the traditional CPU chip are excluded, only the core circuit for completing the control and information processing functions is reserved, and the part of the circuit is the CPU core, which is also called CPU core for short. A CPU core is essentially a completely independent processor that can read instructions from internal memory and perform the control and computational tasks specified by the instructions.
If a CPU core and related auxiliary circuits are packaged in a chip, the chip is a traditional single-core CPU chip, which is called a single-core CPU for short. If a plurality of CPU cores and related auxiliary circuits are packaged in one chip, the chip is a multi-core CPU chip, which is called a multi-core CPU for short. If some other functional components and interface circuits are integrated in the multi-core CPU chip, a complete system is formed, and then the chip becomes a multi-core SOC chip, which is referred to as a multi-core SOC for short.
Multiple CPUs are integrated inside a multi-core SOC chip to meet the increasing demand for computing power. In the process of debugging the CPU, under the condition that the independent reset control of each core CPU cannot be carried out, all the core CPUs in normal operation can only be reset at the same time, the simultaneous reset of the multi-core CPUs means sudden load change, so that the output voltage is upswept, and serious voltage upswept can lead to a series of results which are difficult to predict.
Disclosure of Invention
In view of this, embodiments of the present application provide a load balancing circuit and system for multi-core SOC reset, which aim to solve the problem in the prior art that an output voltage is upsurge due to simultaneous resetting of multi-core CPUs.
In a first aspect, an embodiment of the present application provides a load balancing circuit for multi-core SOC reset, where the circuit includes: the circuit comprises: the circuit comprises a control circuit, a first load circuit, a second load circuit, a control point and a protection circuit;
the output end of the control circuit is connected with the control point; the output end of the first load circuit is connected with the control point; the input end of the second load circuit is connected with the control point; the protection circuit is connected with the control point;
the control circuit controls the second load circuit to be non-conductive when the first load circuit is in a first state and to be conductive when the first load circuit is in a second state; the first state is that a CPU running signal is invalid and/or a debugging signal is invalid, and the second state is that the debugging signal is valid, the CPU running signal is valid and a reset signal is valid;
the protection circuit provides protection for the load balancing circuit of the multi-core SOC reset;
and controlling the load balance during the debugging of the multi-core SOC by utilizing the control circuit, the first load circuit, the second load circuit, the control point and the protection circuit.
Optionally, the second load circuit includes a first N-channel power MOS transistor and a first resistor, the first resistor is connected to a source of the first N-channel power MOS transistor, and a drain of the first N-channel power MOS transistor is connected to a power supply; and the grid electrode of the first N-channel power MOS tube is connected with the control point.
Optionally, the control circuit includes a P-channel power MOS transistor, a second resistor, and a third resistor;
a grid electrode of the P-channel power MOS tube inputs a reset signal and is connected with the third resistor, a drain electrode of the P-channel power MOS tube is connected with the control point, and a source electrode of the P-channel power MOS tube is connected with the second resistor;
and an external power supply is connected with the second resistor and the third resistor.
Optionally, the first load circuit includes a nand gate device and a second N-channel power MOS transistor;
the first end of the NAND gate device inputs the debugging signal, and the second end inputs the CPU running signal;
the grid electrode of the second N-channel power MOS tube is connected with the output end of the NAND gate device, the drain electrode of the second N-channel power MOS tube is connected with the control point, and the source electrode of the second N-channel power MOS tube is grounded.
Optionally, the protection circuit includes a fourth resistor and a capacitor, the fourth resistor is connected to the control point, and the fourth resistor is connected in parallel to the capacitor.
Optionally, the conduction current of the first N-channel power MOS transistor is set within a preset range.
Optionally, the capacitor is used for controlling an equivalent resistance value of the first N-channel power MOS transistor.
Optionally, according to the width of the reset signal, matching between the running time of the second load circuit and the time required by the reset of the CPU is achieved by adjusting the second resistor.
In a second aspect, an embodiment of the present application provides a load balancing system for resetting a multi-core SOC, including any one of the load balancing circuits for resetting a multi-core SOC.
The embodiment of the application provides a load balancing circuit for multi-core SOC reset. The circuit comprises: the circuit comprises a control circuit, a first load circuit, a second load circuit, a control point and a protection circuit; the output end of the control circuit is connected with the control point; the output end of the first load circuit is connected with the control point; the input end of the second load circuit is connected with the control point; the protection circuit is connected with the control point; the control circuit controls the second load circuit to be non-conductive when the first load circuit is in a first state and to be conductive when the first load circuit is in a second state; the first state is that a CPU running signal is invalid and/or a debugging signal is invalid, and the second state is that the debugging signal is valid and the CPU running signal is valid; the protection circuit provides protection for the load balancing circuit of the multi-core SOC reset; and controlling the load balance during the debugging of the multi-core SOC by utilizing the control circuit, the first load circuit, the second load circuit, the control point and the protection circuit. Through setting up the second load circuit to utilize control circuit control the second load circuit switches on when CPU is by the running state switch to reset state simultaneously, can utilize the effect of second load circuit performance spare load when a plurality of CPUs reset simultaneously, in order to avoid a plurality of CPUs to reset the load sudden change that causes simultaneously, and then avoid output voltage to appear the phenomenon of uprush.
Drawings
To illustrate the technical solutions in the present embodiment or the prior art more clearly, the drawings needed to be used in the description of the embodiment or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a block diagram of a solution provided by an embodiment of the present application;
fig. 2 is a load balancing circuit diagram of multi-core SOC reset according to an embodiment of the present disclosure.
Detailed Description
The CPU is an english abbreviation of a Central Processing Unit (Central Processing Unit), has control and information Processing capabilities, and is a control center of a computer and intelligent equipment. If the package and auxiliary circuits (such as interface circuit of pins, power supply circuit and clock circuit) in the traditional CPU chip are excluded, only the core circuit for completing the control and information processing functions is reserved, and the part of the circuit is the CPU core, also called CPU core for short. A CPU core is basically a completely independent processor that can read instructions from internal memory and perform the control and computational tasks specified by the instructions.
If a CPU core and related auxiliary circuits are packaged in a chip, the chip is a traditional single-core CPU chip, which is called a single-core CPU for short. If a plurality of CPU cores and related auxiliary circuits are packaged in one chip, the chip is a multi-core CPU chip, which is called a multi-core CPU for short. If some other functional components and interface circuits are integrated in the multi-core CPU chip, a complete system is formed, and then the chip becomes a multi-core SOC chip, referred to as a multi-core SOC.
Multiple CPUs are integrated inside a multi-core SOC chip to meet the increasing demand for computing power. In the process of debugging the CPU, under the condition that the independent reset control of each core CPU cannot be carried out, all the core CPUs in normal operation can only be reset at the same time, the simultaneous reset of the multi-core CPUs means sudden load change, so that the output voltage is upswept, and serious voltage upswept can lead to a series of results which are difficult to predict.
At present, the phenomenon that the voltage is uprushed due to sudden load change caused by simultaneous resetting of a multi-core CPU can be avoided if a standby load circuit can be connected in the process of simultaneous resetting of the multi-core CPU, and the phenomenon that the voltage is uprushed can not be caused. Thus, the present solution is proposed.
Referring to fig. 1, fig. 1 is a schematic diagram of a scheme provided by an embodiment of the present application, in which a MOSFET is used as a standby load circuit, and a control circuit controls the standby load circuit to be turned on when a CPU is simultaneously switched from an operating state to a reset state, so that a second load circuit can be used to play a role of a standby load when a plurality of CPUs are simultaneously reset, thereby avoiding sudden load change caused by simultaneous reset of the plurality of CPUs, and further avoiding an overshoot phenomenon of an output voltage.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present application, and not all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making any creative effort belong to the protection scope of the present application.
Referring to fig. 2, fig. 2 is a load balancing circuit diagram for multi-core SOC reset according to an embodiment of the present disclosure, an application scenario of the circuit diagram may be a scenario where a multi-core SOC chip tests a multi-core CPU, and the circuit includes: the circuit comprises a control circuit, a first load circuit, a second load circuit, a control point and a protection circuit. The control circuit is used for controlling the on and off of the second load circuit; the first load circuit is used for reflecting a debugging state during debugging and the running state of the CPU; the second load circuit is equivalent to a standby load circuit and is switched on when the first load circuit does not work, and in the scheme, the second load circuit can be switched on in the process of simultaneously resetting a plurality of CPUs; the control point is a node which inputs a signal to the second load circuit; the protection circuit prevents the load circuit from generating a safety fault.
The second load circuit comprises a first N-channel power MOS tube and a first resistor, the first N-channel power MOS tube can be set to be an N-channel power MOSFET tube and set to be Q1, the first resistor is set to be R1, the R1 is connected with a source electrode 2 of the Q1, a drain electrode 3 of the Q1 is connected with a power supply VDD, a grid electrode 1 of the Q1 is connected with a control point, and the control point is used for inputting signals to control the on and off of the second load circuit.
The control circuit comprises a P-channel power MOS tube, a second resistor and a third resistor, wherein the P-channel power MOS tube is set to be Q2, the second resistor and the third resistor are respectively set to be R2 and R3, the grid electrode of the Q2 is input with a RESET signal CPU _ RESET, the grid electrode of the Q2 is connected with the R3, the drain electrode of the Q2 is connected with the control point, the source electrode of the Q2 is connected with the R2, and the R2 and the R3 are connected in parallel and are externally connected with a power supply VEXT.
The first load circuit comprises a NAND gate device and a second N-channel power MOS tube, wherein the NAND gate device is set to be U1, and the second N-channel power MOS tube is set to be Q3; the first input end of the nand gate device inputs a debugging signal, the debugging signal represents a signal when a debugging fault occurs, and the signal is set as a DEBUG signal; the other input end of the NAND gate device inputs an operation signal CPU _ RUN of the multi-core CPU, the output end of the NAND gate is connected with a grid 1 of a Q3, the Q3 is conducted only when the debugging signal and the operation signal of the multi-core CPU are both effective, and the second load circuit is controlled by the reset signal only when the debugging signal and the operation signal of the multi-core CPU are both effective. Drain 3 of Q3 is connected to the control point and source 2 of Q3 is connected to ground.
The protection circuit comprises a fourth resistor and a capacitor, the fourth resistor is set to be R4, and the capacitor is set to be C1; r4 is connected to the control point and R4 is connected in parallel with C1.
The output end of the control circuit is connected with the control point; the output end of the first load circuit is connected with the control point; the input end of the second load circuit is connected with the control point; the protection circuit is connected with the control point; the control circuit controls the second load circuit to be not conducted when the CPU operation signal is invalid and/or the debugging signal is invalid, and to be conducted when the first load circuit is in the state that the debugging signal is valid, the CPU operation signal is valid and the reset signal is valid; the protection circuit provides protection for the load balancing circuit of the multi-core SOC reset; and controlling the load balance during the debugging of the multi-core SOC by using the control circuit, the first load circuit, the second load circuit, the control point and the protection circuit. The specific implementation process is as follows:
when debugging starts, the present embodiment is applied to a case where the debugging process fails, that is, the DEBUG signal DEBUG _ EN is active at a high level.
The embodiment of the application aims to avoid the phenomenon of load mutation in the process of simultaneous resetting when a multi-core CPU runs, and therefore a NAND gate is arranged in a first load circuit and is used for controlling the second load circuit to be switched on during the period that the reset signal enables the multi-core CPU to complete resetting of the multi-core CPU, namely, a DEBUG signal is effective, and when the multi-core CPU is in a running state, the multi-core CPU can be reset simultaneously by the reset signal, so that the load mutation can be generated. For example, the second load circuit is controlled by the RESET signal CPU _ RESET only when the DEBUG signal DEBUG _ EN is active and the CPU is already running. Otherwise, U1 outputs high level, N channel MOSFET pipe Q3 switches on, and the grid voltage of Q1 among the second load circuit is zero, and second load circuit does not work.
Under the condition that the DEBUG signal DEBUG _ EN is effective and the CPU is running, when the RESET signal CPU _ RESET is triggered, generally, a falling edge triggers, Q2 is turned on, and then Q1 in the second load circuit is saturated and turned on, the second load circuit starts to operate, and the second load circuit stops running when the CPU RESET is completed.
After the reset signal is triggered, namely after the multi-core CPU is reset, due to the existence of the capacitor C1, the capacitor C1 can control the equivalent resistance value of the Q1 to be in a variable range, therefore, the grid voltage of the Q1 does not disappear immediately but slowly decreases, the Q1 is separated from a saturated conducting area firstly and enters a variable resistance area, and finally, the discharge of the C1 is finished, and the Q1 is cut off. The current through the second load gradually drops to zero. This also makes it possible to prevent sudden load changes in the second load circuit.
The embodiment of the application provides a load balancing circuit for multi-core SOC reset. The circuit comprises: the circuit comprises a control circuit, a first load circuit, a second load circuit, a control point and a protection circuit; the output end of the control circuit is connected with the control point; the output end of the first load circuit is connected with the control point; the input end of the second load circuit is connected with the control point; the protection circuit is connected with the control point; the control circuit controls the second load circuit to be non-conductive when the first load circuit is in a first state and to be conductive when the first load circuit is in a second state; the first state is that a CPU running signal is invalid and/or a debugging signal is invalid, and the second state is that the debugging signal is valid and the CPU running signal is valid; the protection circuit provides protection for the load balancing circuit of the multi-core SOC reset; and controlling the load balance during the debugging of the multi-core SOC by using the control circuit, the first load circuit, the second load circuit, the control point and the protection circuit. By arranging the second load circuit and controlling the second load circuit to be switched on when the CPUs are simultaneously switched from the running state to the reset state by using the control circuit, the second load circuit can be used for playing the role of a standby load when a plurality of CPUs are simultaneously reset, so that the phenomenon that the output voltage is uprushed due to sudden load change caused by simultaneous reset of the plurality of CPUs is avoided.
In an optional embodiment of the present application, the first N-channel power MOS transistor in the second load circuit, that is, the conduction current of Q1 in the embodiment, needs to be set within a preset range, for example, the saturation conduction current of Q1 may be designed to be approximately equal to 70% -90% of the full load current of the CPU, and the setting of a specific value depends on the specific circuit design, that is, the resistance of R1.
In an optional embodiment of the present application, the RESET signal CPU _ RESET is generally valid at the falling edge, and the width of the RESET signal is the time required by the multi-core CPU RESET process, in this embodiment, the first load circuit is equivalent to stop working in the multi-core CPU RESET process, at this time, the second load circuit needs to be turned on, and after the multi-core CPU RESET is completed, the first load circuit is equivalent to normal working, and the second load circuit does not need to work, so that the conduction time of the second load circuit needs to be matched with the width of the RESET signal CPU _ RESET, that is, the second load circuit is controlled to be conducted only in the multi-core CPU RESET process, which can be implemented by adjusting R2. The larger R2, the longer the charging period of the capacitor C1, and the longer the delay time for the saturation conduction of Q1, whereby matching of the conduction time of the second load circuit with the width of the RESET signal CPU _ RESET can be achieved.
On the basis of the above embodiment, the embodiment of the present application further provides a multi-core SOC reset load balancing system, which includes the above multi-core SOC reset load balancing circuit.
It should be noted that the load balancing system for multi-core SOC reset provided in this embodiment has the same beneficial effects as the load balancing circuit for multi-core SOC reset provided in the foregoing embodiment, and for specific description of the load balancing circuit for multi-core SOC reset related in this embodiment, please refer to the foregoing embodiment, which is not described herein again.
In the embodiments of the present application, the names "first" and "second" in the names "first load circuit" and "second load circuit" are used merely as name labels, and do not represent the sequential first and second.
The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, as for the system embodiment, since it is substantially similar to the circuit embodiment, the description is simple, and the relevant points can be referred to the partial description of the circuit embodiment. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement without inventive effort.
The above description is only an exemplary embodiment of the present application, and is not intended to limit the scope of the present application.
Claims (9)
1. A load balancing circuit for multi-core SOC reset, the circuit comprising: the circuit comprises a control circuit, a first load circuit, a second load circuit, a control point and a protection circuit;
the output end of the control circuit is connected with the control point; the output end of the first load circuit is connected with the control point; the input end of the second load circuit is connected with the control point; the protection circuit is connected with the control point;
the control circuit controls the second load circuit to be non-conductive when the first load circuit is in a first state and to be conductive when the first load circuit is in a second state; the first state is that a CPU running signal is invalid and/or a debugging signal is invalid, and the second state is that the debugging signal is valid, the CPU running signal is valid and a reset signal is valid;
the protection circuit provides protection for the load balancing circuit of the multi-core SOC reset;
and controlling the load balance during the debugging of the multi-core SOC by utilizing the control circuit, the first load circuit, the second load circuit, the control point and the protection circuit.
2. The multi-core SOC reset load balancing circuit of claim 1, wherein the second load circuit comprises a first N-channel power MOS transistor and a first resistor, the first resistor is connected with a source of the first N-channel power MOS transistor, and a drain of the first N-channel power MOS transistor is connected with a power supply; and the grid electrode of the first N-channel power MOS tube is connected with the control point.
3. The multi-core SOC reset load balancing circuit of claim 1, wherein the control circuit comprises a P-channel power MOS transistor, a second resistor and a third resistor;
a grid electrode of the P-channel power MOS tube inputs a reset signal and is connected with the third resistor, a drain electrode of the P-channel power MOS tube is connected with the control point, and a source electrode of the P-channel power MOS tube is connected with the second resistor;
and an external power supply is connected with the second resistor and the third resistor.
4. The multi-core SOC reset load balancing circuit of claim 1, wherein the first load circuit comprises a NAND gate device and a second N-channel power MOS transistor;
the first end of the NAND gate device inputs the debugging signal, and the second end inputs the CPU running signal;
the grid electrode of the second N-channel power MOS tube is connected with the output end of the NAND gate device, the drain electrode of the second N-channel power MOS tube is connected with the control point, and the source electrode of the second N-channel power MOS tube is grounded.
5. The multi-core SOC reset load balancing circuit of claim 1, wherein the protection circuit comprises a fourth resistor and a capacitor, the fourth resistor is connected to the control point, and the fourth resistor is connected in parallel with the capacitor.
6. The multi-core SOC reset load balancing circuit of claim 1, wherein a conduction current of the first N-channel power MOS transistor is set within a preset range.
7. The multi-core SOC reset load balancing circuit of claim 4 or 5, wherein the capacitor is used for controlling an equivalent resistance value of the first N-channel power MOS transistor.
8. The load balancing circuit for multi-core SOC reset according to claim 1, wherein the matching of the running time of the second load circuit and the time required by CPU reset is achieved by adjusting the second resistor according to the width of the reset signal.
9. A multi-core SOC reset load balancing system, characterized in that, the load balancing circuit of multi-core SOC reset of any claim 1 to 8 is included.
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| CN202211080066.7A CN115167651B (en) | 2022-09-05 | 2022-09-05 | Multi-core SOC reset load balancing circuit and system |
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| CN202211080066.7A CN115167651B (en) | 2022-09-05 | 2022-09-05 | Multi-core SOC reset load balancing circuit and system |
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