CN114527857A - Multi-core system resetting method, device and equipment and readable storage medium - Google Patents
Multi-core system resetting method, device and equipment and readable storage medium Download PDFInfo
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Abstract
The application provides a multi-core system resetting method, a device, equipment and a readable storage medium, wherein the method comprises the following steps: acquiring reset information of a target processor after the multi-core system executes bus reset; after the target processor is judged to be successfully reset, whether all the rest processors of the multi-core system are successfully reset is detected through the target processor; if yes, ending the multi-core reset; and if any processor is detected to be unsuccessfully reset, controlling the register corresponding to the processor which is unsuccessfully reset to reset again through the target processor until all the rest processors of the multi-core system are successfully reset, and ending the multi-core reset. According to the method and the device, the reset detection and the reset operation are carried out on the rest processors through the target processor which is successfully reset, the condition that the processors are idle due to accidental failure of the available processors of the multi-core system can be avoided, and when any processor is abnormal, the reset is carried out in time to prevent the application from being in fault, so that the stability of the multi-core system is improved.
Description
Technical Field
The present application relates to the field of chip design technologies, and in particular, to a method, an apparatus, a device, and a readable storage medium for resetting a multi-core system.
Background
With the continuous development and improvement of scientific technology, the functional requirements on the CPU are higher and higher, and the functions of the common single-core system cannot meet the application requirements in some technical fields. With the advent of the multi-core system, the multi-core system is gradually favored by users due to the advantage of the execution efficiency. With the advent of multi-core systems, some technical problems between systems have arisen, particularly with regard to how to coordinate and manage the reset of multiple cores, and only if the reset of the CPU is managed, the system and other components can be in a certain initial state, and the normal operation can be started from the initial state.
In the course of conceiving and implementing the present application, the inventors found that at least the following problems existed: at present, when not all the multi-core CPU chips are successfully reset, the cores which fail to be reset can be shielded, but the failure of the reset is not necessarily the failure of the cores, and the temporary failure can also be caused by the instability of a clock, so that the accidental failure of the reset can be caused; meanwhile, in the conventional multi-core system, the reset state of other cores is realized by accessing a shared register during reset, so that when two or more cores operate the shared register simultaneously, a bus error is easy to occur; moreover, the reset states of other cores cannot be flexibly switched after the conventional multi-core system is successfully reset, so that the software reset cannot be generated when external interference or artificial damage occurs; in addition, the existing multi-core system reset technology cannot flexibly control which core has priority to BOOT when the system is started for the first time, and the flexibility is low.
The foregoing description is provided for general background information and is not admitted to be prior art.
Disclosure of Invention
In view of the foregoing technical problems, the present application provides a method, an apparatus, a device, and a readable storage medium for resetting a multi-core system, in which a target processor that is successfully reset performs reset detection and reset operations on remaining processors, thereby avoiding a situation that an available processor of the multi-core system is idle due to accidental failure, and improving stability of the multi-core system.
In order to solve the above technical problem, the present application provides a multi-core system reset method, including the following steps:
after the multi-core system executes bus reset, acquiring reset information of a target processor;
after the target processor is judged to be successfully reset according to the reset information, whether all the rest processors of the multi-core system are successfully reset is detected through the target processor;
if all the rest processors are detected to be successfully reset, ending the multi-core reset;
and if any processor is detected to be unsuccessfully reset, controlling the register corresponding to the processor which is unsuccessfully reset to reset again through the target processor until all the rest processors of the multi-core system are successfully reset, and ending the multi-core reset.
Optionally, the target processor is a first processor arranged in a starting sequence in the multi-core system, and the starting sequence is set according to option bytes.
Optionally, the controlling, by the target processor, the register corresponding to the processor that has not been successfully reset to reset again specifically includes:
if the number of times of executing the reset operation on the processor which is not successfully reset is detected to be smaller than a first preset number of times, continuing the reset operation on the processor which is not successfully reset through the target processor until the reset is successful or the number of times of executing the reset operation is larger than or equal to the first preset number of times.
Optionally, the multi-core system resetting method further includes:
if the number of times of executing reset operation on the processor which is not successfully reset is detected to be larger than or equal to the first preset number of times and the processor is not successfully reset, the processor which is not successfully reset is judged to be a fault processor, and the fault processor is shielded.
Optionally, the detecting, by the target processor, whether all the remaining processors of the multi-core system are successfully reset includes:
and reading the register corresponding to each residual processor through the target processor, and judging whether the residual processors are all reset successfully.
Optionally, after the ending multi-core reset, the method further includes:
polling and reading registers of the rest processors by any processor of the multi-core system;
when any processor reads a processor with a fault in the rest processors, the register of the fault processor is controlled by the processor to reset the fault processor, and the running state of the fault processor is read.
Optionally, after the resetting operation of the failing processor is performed by the register controlling the failing processor by any processor, the method further includes:
if the number of times of executing the reset operation on the fault processor is detected to be less than a second preset number of times, continuing the reset operation on the fault processor until the reset is successful or the number of times of executing the reset operation is greater than or equal to the second preset number of times;
and if the times of executing the reset operation on the fault processor are greater than or equal to a second preset time and the reset is not successful, shielding the fault processor.
Correspondingly, the present application also provides a multi-core system resetting device, including:
the system comprises an acquisition module, a reset module and a control module, wherein the acquisition module is used for acquiring the reset information of a target processor after the multi-core system executes bus reset;
the detection module is used for detecting whether all the rest processors of the multi-core system are successfully reset or not through the target processor after the target processor is judged to be successfully reset according to the reset information;
the reset module is used for finishing multi-core reset if detecting that all the rest processors are successfully reset; and if any processor is detected to be unsuccessfully reset, controlling the register corresponding to the processor which is unsuccessfully reset to reset again through the target processor until all the rest processors of the multi-core system are successfully reset, and ending the multi-core reset.
The present application further provides a computer device, including a memory and a processor, where the memory stores a computer program, and the processor implements the steps of the multi-core system reset method described in any one of the above when executing the computer program.
The present application also proposes a computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the multicore system reset method of any of the above mentioned.
The embodiment of the invention has the following beneficial effects:
as described above, the present application provides a multi-core system reset method, apparatus, device and readable storage medium, where the method includes: after the multi-core system executes bus reset, acquiring reset information of a target processor; after the target processor is judged to be successfully reset according to the reset information, whether all the rest processors of the multi-core system are successfully reset is detected through the target processor; if all the rest processors are detected to be successfully reset, ending the multi-core reset; and if any processor is detected to be unsuccessfully reset, controlling the register corresponding to the processor which is unsuccessfully reset to reset again through the target processor until all the rest processors of the multi-core system are successfully reset, and ending the multi-core reset. According to the multi-core system resetting method, the first target processor arranged in the starting sequence of the multi-core system is reset and detected, and the flexibility of the multi-core system is improved; then, the target processor which is successfully reset carries out reset detection and reset operation on the rest processors until all the processors of the multi-core system are successfully reset, so that the condition that the processors are idle due to accidental failure of the processors available for the multi-core system can be avoided, and when any processor is abnormal, the processor is timely reset to prevent application from being failed, and the stability and reliability of the multi-core system are further improved; in addition, each processor in the multi-core system can read and control registers of other processors, and the situation of bus errors is avoided.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application. In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments will be briefly described below, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
Fig. 1 is a schematic flowchart of a first implementation manner of a multi-core system reset method provided by an embodiment of the present application;
fig. 2 is a schematic structural diagram of a multi-core system reset system provided in an embodiment of the present application;
fig. 3 is a flowchart illustrating a second implementation manner of a multi-core system resetting method according to an embodiment of the present application;
fig. 4 is a flowchart illustrating a third implementation manner of a multi-core system resetting method according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of a multi-core system resetting device provided in an embodiment of the present application;
fig. 6 is a schematic structural diagram of a computer device provided in an embodiment of the present application.
The implementation, functional features and advantages of the objectives of the present application will be further explained with reference to the accompanying drawings. With the above figures, there are shown specific embodiments of the present application, which will be described in more detail below. These drawings and written description are not intended to limit the scope of the inventive concepts in any manner, but rather to illustrate the inventive concepts to those skilled in the art by reference to specific embodiments.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the recitation of an element by the phrase "comprising an … …" does not exclude the presence of additional like elements in the process, method, article, or apparatus that comprises the element, and further, where similarly-named elements, features, or elements in different embodiments of the disclosure may have the same meaning, or may have different meanings, that particular meaning should be determined by their interpretation in the embodiment or further by context with the embodiment.
It should be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope herein. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context. Also, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes" and/or "including," when used in this specification, specify the presence of stated features, steps, operations, elements, components, items, species, and/or groups, but do not preclude the presence, or addition of one or more other features, steps, operations, elements, components, species, and/or groups thereof. The terms "or," "and/or," "including at least one of the following," and the like, as used herein, are to be construed as inclusive or mean any one or any combination. For example, "includes at least one of: A. b, C "means" any of the following: a; b; c; a and B; a and C; b and C; a and B and C ", again for example," A, B or C "or" A, B and/or C "means" any of the following: a; b; c; a and B; a and C; b and C; a and B and C'. An exception to this definition will occur only when a combination of elements, functions, steps or operations are inherently mutually exclusive in some way.
It should be understood that, although the steps in the flowcharts in the embodiments of the present application are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and may be performed in other orders unless explicitly stated herein. Moreover, at least some of the steps in the figures may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, in different orders, and may be performed alternately or partially with other steps or at least some of the sub-steps or stages of other steps.
The words "if", as used herein, may be interpreted as "at … …" or "at … …" or "in response to a determination" or "in response to a detection", depending on the context. Similarly, the phrases "if determined" or "if detected (a stated condition or event)" may be interpreted as "when determined" or "in response to a determination" or "when detected (a stated condition or event)" or "in response to a detection (a stated condition or event)", depending on the context.
It should be noted that step numbers such as S10 and S20 are used herein for the purpose of more clearly and briefly describing the corresponding contents, and do not constitute a substantial limitation on the sequence, and those skilled in the art may perform S20 first and then perform S10 in the specific implementation, which should be within the scope of the present application.
It should be understood that the specific embodiments described herein are merely illustrative of and not restrictive on the broad application.
In the following description, suffixes such as "module", "component", or "unit" used to denote elements are used only for the convenience of description of the present application, and have no specific meaning in themselves. Thus, "module", "component" or "unit" may be used mixedly.
First, an application scenario that can be provided by the present application is introduced, for example, a multi-core system reset method, apparatus, device, and readable storage medium are provided, which can perform reset detection and reset operation on each processor of a multi-core system, thereby improving stability and flexibility of the multi-core reset system.
Referring to fig. 1, fig. 1 is a schematic flowchart illustrating a first implementation manner of a multi-core system resetting method according to an embodiment of the present disclosure. The multi-core system resetting method may specifically include:
and S10, acquiring the reset information of the target processor after the multi-core system executes bus reset.
It should be noted that the multi-core system includes a plurality of cores, and each core is a processor, such as a CPU.
Specifically, for step S10, after the multi-core system performs the bus reset operation, the multi-core system resets all processors in the multi-core system again, and then collects the reset information of the target processor after the multi-core system performs the bus reset. In a specific embodiment, in addition to the reset operation of the multi-core system through the bus reset operation, the reset operation of the multi-core system may be performed in a power-on reset manner.
And S20, after the target processor is judged to be successfully reset according to the reset information, detecting whether all the rest processors of the multi-core system are successfully reset through the target processor.
Specifically, for the step S20, it is determined whether the reset of the target processor (the first processor arranged in the starting order) of the multi-core system is successful according to the reset information of the target processor acquired after the multi-core system performs the bus reset; if the target processor is judged to be successfully reset, reading reset/state registers of other processors through the successfully reset target processor, and thus detecting whether the rest processors of the multi-core system are successfully reset; if the target processor fails to be reset, returning to the bus resetting step, and continuing to reset the multi-core system until the target processor is successfully reset, namely when the first core arranged according to the starting sequence fails to be reset, resetting the bus again until the first core can normally operate. Therefore, the problem that the first BOOT of a core cannot be flexibly controlled when the system is started for the first time in the multi-core system resetting is solved, and the flexibility of multi-core resetting is further improved.
Optionally, in some embodiments, the detecting, by the target processor, in the step S20, whether all the remaining processors of the multi-core system are reset successfully may specifically include:
and reading the corresponding register of each residual processor through the target processor, and judging whether the residual processors are all reset successfully.
Specifically, the target processor after the successful reset reads the reset/status registers corresponding to the remaining processors in the multi-core system, so as to determine whether the remaining processors in the multi-core system are all successfully reset.
Optionally, in some embodiments, the target processor is a first processor in the multi-core system arranged according to a boot order, and the boot order is set according to the option byte. For example, the start-up sequence is set according to the size of the option byte.
In a specific embodiment, as shown in fig. 2, fig. 2 provides a schematic structural diagram of a multi-core system reset system, and in fig. 2, a processor is taken as a CPU for example to explain, and the CPU can reset itself through its POR or NRST or software watchdog, or can reset itself through each other. The reset/status register is used to feed back the status of the system operation. The target processor reset success flag register indicates the running state of the target processor, and in this embodiment, the starting sequence of the CPU may be controlled by an option byte, so as to ensure that the first processor runs normally, which aims to ensure that the first processor is available and can be used as a main core (main processor). When a multi-core system is powered on or a bus is reset, due to unstable factors of RCC clocks, a processor cannot be normally and successfully reset, whether all processors can operate successfully or not is judged by setting a first processor reset success flag and a system state register, if all processors do not successfully reset, other processors can reset a fault core, and the processor is determined to be a fault processor until a reset target processor is successfully reset or the reset target processor is not successfully reset for a preset number of times.
And S31, detecting that all the rest processors are successfully reset, and ending the multi-core reset.
Specifically, in step S31, when the reset/status registers of the other processors are read by the target processor, and it is detected that all the remaining processors of the multi-core system have been successfully reset, the multi-core reset of this time is successful, and the multi-core reset of the multi-core system of this time is ended.
And S32, detecting that any processor is not successfully reset, controlling the register corresponding to the processor which is not successfully reset to reset again through the target processor until all the rest processors of the multi-core system are successfully reset, and ending the multi-core reset.
Specifically, for the step S32, the target processor that has successfully reset reads the reset/status registers of the other processors, so as to detect whether all the remaining processors of the multi-core system have successfully reset, and when it is detected that all the remaining processors of the multi-core system have not successfully reset, that is, when any one processor has not successfully reset, the processor that has successfully reset controls the reset/status register corresponding to the processor that has not successfully reset to reset again until all the remaining processors of the multi-core system have successfully reset, and this multi-core reset is completed. The target processor which is successfully reset carries out reset detection and reset operation on the rest processors until all the processors of the multi-core system are successfully reset, so that the condition that the processors are idle due to accidental failure of the processors available for the multi-core system can be avoided. Meanwhile, each processor of the multi-core system in the embodiment can read and control registers of other processors, so that the bus error is avoided.
Optionally, in some embodiments, for the step S32, controlling, by the target processor, that the register corresponding to the processor that has not been successfully reset is reset again, the method may further include:
if the number of times of executing the reset operation on the processor which is not successfully reset is detected to be smaller than the first preset number of times, the target processor continues to perform the reset operation on the processor which is not successfully reset until the reset is successful or the number of times of executing the reset operation is larger than or equal to the first preset number of times.
Specifically, when it is detected that the number of times of the reset operation executed by the processor that has not been successfully reset is smaller than a first preset number of times, the target processor continues to perform the reset operation on the processor that has not been successfully reset until the reset target processor is successfully reset, or the number of times of the reset operation executed is greater than or equal to the first preset number of times, and the reset of the reset target processor is stopped. After the processor which is not successfully reset is reset, reading a reset/state register corresponding to a reset target processor, judging whether all the rest processors of the multi-core system are successfully reset, if so, ending the multi-core reset; if not, repeating the steps until all processors are successfully reset or all processors which are failed to be reset are shielded.
Optionally, in some embodiments, for the step S32, controlling, by the target processor, that the register corresponding to the processor that has not been successfully reset is reset again, the method may further include:
if the number of times of executing reset operation on the processor which is not successfully reset is detected to be larger than or equal to the first preset number of times and the processor is not successfully reset, the processor which is not successfully reset is judged to be a fault processor, and the fault processor is shielded.
Specifically, when it is detected that the number of times of the reset operation executed by the processor that has not been successfully reset is greater than or equal to a first preset number of times and the reset target processor has not been successfully reset, it is determined that the processor that has not been successfully reset is a faulty processor, and all the faulty processors are shielded in the multi-core reset at this time.
Optionally, in some embodiments, after ending the multi-core reset, the method further includes:
polling and reading registers of the rest processors by any processor of the multi-core system;
when any processor reads a processor with a fault in the rest processors, the register of the fault processor is controlled by the processor to reset the fault processor, and the running state of the fault processor is read.
Specifically, in this embodiment, after the ending of the multi-core reset, the method may further include: and when any processor reads that any other processor has a fault, the processor which is successfully reset controls the fault processor to carry out reset operation, and reads the reset/state register of the fault processor in real time, thereby judging the real-time running state of the fault processor.
Optionally, in some embodiments, after the resetting operation of the failing processor is performed by the register of the failing processor controlled by any one of the processors, the method further includes:
if the number of times of executing the reset operation on the fault processor is detected to be less than a second preset number of times, continuing the reset operation on the fault processor until the reset is successful or the number of times of executing the reset operation is greater than or equal to the second preset number of times;
and if the times of executing the reset operation on the fault processor are greater than or equal to a second preset time and the reset is not successful, shielding the fault processor.
Specifically, when the multi-core system normally operates, if the number of times of executing the reset operation by any fault processor detected by any processor with successful reset is less than a second preset number of times, the fault processor is continuously reset until the fault processor is successfully reset, or the number of times of the reset operation is greater than or equal to the second preset number of times; and when the number of times of resetting operation on the fault processor is greater than or equal to a second preset number of times and the fault processor is not successfully reset and does not normally operate, shielding the fault processor.
Referring to fig. 3, fig. 3 is a flowchart illustrating a multi-core system resetting method according to a second implementation manner of the present application. The flow of the multi-core system resetting method comprises the following steps:
and S101, executing bus reset.
S102, judging whether the first core is reset successfully.
In this step, it is determined whether the first core (i.e., the target processor) is successfully reset, and if the determination result is negative, the process returns to step S101; if yes, go to step S103;
s103, reading reset/state registers of other cores.
In this step, the reset state of the reset/state registers of the cores other than the first core is read.
And S104, judging whether all the cores are successfully reset or not.
In this step, it is determined whether all of the cores are successfully reset, and if yes, step S1041 is executed; if the determination result is negative, step S105 is executed.
And S1041, ending the multi-core reset.
S105, judging whether reset operation is executed on the fault core for preset times;
in this step, it is determined whether a reset operation is performed on the faulty core for a preset number of times, and if the determination result is yes, step S1051 is performed; if the determination result is negative, step S106 is executed.
S1051, shielding the core which fails to reset.
In this step, the core that failed to reset is masked.
And S106, executing reset operation on the fault core.
And S107, reading a reset/state register of the fault core.
In this step, the reset state of the reset/status register of the faulty core is read, and after step S107 is executed, the process returns to step S104.
In a specific implementation process, after the system executes bus reset, the system feeds back the state of the first reset core, if the first core fails to reset, the bus reset is performed again, if the first core succeeds in resetting, the first core reads the operating states of other cores through reset/state registers of the other cores, and when the operating states indicate that all cores work normally, the multi-core reset is finished. If the fault core exists, resetting operation is carried out on the fault core for preset times, the running state is read, and when the preset resetting times are executed, the fault core does not run normally, and the fault core is shielded.
Referring to fig. 4, fig. 4 is a flowchart illustrating a third implementation manner of a multi-core system resetting method according to an embodiment of the present application. The multi-core system resetting method comprises the following steps:
s201, reading a reset/state register.
S202, judging whether a fault core exists or not.
In this step, it is determined whether a faulty core exists, and if the determination result is no, the process returns to step S201; if yes, go to step S203.
S203, judging whether the reset operation of the fault core is executed for the preset times.
In this step, it is determined whether a reset operation is performed on the faulty core for a preset number of times, and if the determination result is yes, step S2031 is performed; if the determination result is negative, step S2032 is executed.
S2031, shielding the core which fails in reset.
In this step, the core that failed to reset is masked.
And S2032, resetting the fault core.
In this step, a reset operation is performed on the faulty core, and after step S2032 is performed, the process returns to step S201.
In a specific implementation process, when the multi-core system normally runs, each processor can read the reset/state registers of other processors in a polling manner, the running states of the other processors are fed back through the reset/state registers, when one core detects that any other processor cannot normally run, the reset/state registers of the other processors are controlled to perform reset operation on a target core, then whether the target processor normally works is judged through the reset/state registers, if the target processor does not normally work, the target processor continues to perform the above operation until the target processor normally works, or the target processor is considered to have a fault if the target processor does not normally work for a preset number of times.
In addition, in the running process of the multi-core system, due to factors such as external interference and the like, a certain processor may be failed and cannot generate reset, the system status register may be read in a polling manner, the failed processor is monitored in real time, and the failed processor is reset by other processors, and the processor is not determined to be damaged until the failed processor is successfully reset or the reset is not successful for a preset number of times.
From the above, the multi-core system resetting method provided in the embodiment of the present application includes: after the multi-core system executes bus reset, acquiring reset information of a target processor; after the target processor is judged to be successfully reset according to the reset information, whether all the rest processors of the multi-core system are successfully reset is detected through the target processor; if all the rest processors are detected to be successfully reset, ending the multi-core reset; and if any processor is detected to be unsuccessfully reset, controlling the register corresponding to the processor which is unsuccessfully reset to reset again through the target processor until all the rest processors of the multi-core system are successfully reset, and ending the multi-core reset. Therefore, according to the multi-core system resetting method provided by the embodiment of the application, the first processor (namely, the target processor) arranged in the multi-core system according to the starting sequence is reset and detected, so that the flexibility of the multi-core system is improved; then, the target processor which is successfully reset carries out reset detection and reset operation on the rest processors until all the processors of the multi-core system are successfully reset, so that the condition that the processors are idle due to accidental failure of the processors available for the multi-core system can be avoided, and when any processor is abnormal, the processor is timely reset to prevent application from being failed, and the stability and reliability of the multi-core system are further improved; in addition, each processor in the multi-core system can read and control registers of other processors, and the situation of bus errors is avoided.
Correspondingly, the present application further provides a multi-core system resetting device, please refer to fig. 5, where fig. 5 is a schematic structural diagram of the multi-core resetting device provided in the present application, and specifically, the device may include an obtaining module 100, a detecting module 200, and a resetting module 300.
The obtaining module 100 is configured to obtain reset information of a target processor after the multi-core system executes bus reset.
Specifically, for the obtaining module 100, after the multi-core system performs the bus reset operation, all processors in the multi-core system are reset again, and then the reset information of the target processor after the multi-core system performs the bus reset is collected.
And the detecting module 200 is configured to detect, by the target processor, whether all the remaining processors of the multi-core system are successfully reset after the target processor is judged to be successfully reset according to the reset information.
Optionally, in some embodiments, the detection module 200 may specifically include:
and the starting sequence unit is used for determining a target processor, the target processor is the first processor arranged according to a starting sequence in the multi-core system, and the starting sequence is set according to the option byte.
And the reset detection unit is used for reading the registers corresponding to the residual processors through the target processor and judging whether the residual processors are reset successfully or not.
Specifically, for the detection module 200, whether the target processor (the processor with the first start sequence) of the multi-core system is successfully reset is determined according to the reset information of the target processor obtained after the multi-core system executes bus reset; if the target processor is judged to be successfully reset, reading reset/state registers of other processors through the successfully reset target processor, and detecting whether the rest processors of the multi-core system are successfully reset; if the target processor fails to be reset, returning to the step of executing bus reset, and continuing to execute bus reset or power-on reset on the multi-core system until the target processor is successfully reset, namely when the first core fails to be reset, resetting the bus again until the first core can normally operate.
A reset module 300, configured to end multi-core reset if it is detected that all the remaining processors are successfully reset; and if any processor is detected to be unsuccessfully reset, controlling the register corresponding to the processor which is unsuccessfully reset to reset again through the target processor until all the rest processors of the multi-core system are successfully reset, and ending the multi-core reset.
Optionally, in some embodiments, the reset module 300 may specifically include:
the first reset unit is used for finishing multi-core reset if detecting that all the rest processors are successfully reset;
and the second resetting unit is used for controlling the register corresponding to the processor which is not successfully reset to reset again through the target processor if the condition that any processor is not successfully reset is detected, and ending the multi-core reset until all the rest processors of the multi-core system are successfully reset.
Specifically, for the reset module 300, when the reset/status registers of the other processors are read by the target processor, and after all the rest processors of the multi-core system are successfully reset, the multi-core reset of this time is indicated to be successful, and the multi-core reset of the multi-core system of this time is finished; when the target processor detects that all the rest processors of the multi-core system are not successfully reset, namely any processor is not successfully reset, the processor which is successfully reset controls the reset/state register corresponding to the processor which is not successfully reset to reset again until all the rest processors of the multi-core system are successfully reset, and the multi-core reset is finished.
Optionally, the multi-core system resetting device may specifically further include:
the polling module is used for polling and reading registers of the rest processors through any processor of the multi-core system; when any processor reads a processor with a fault in the rest processors, the register of the fault processor is controlled by the processor to reset the fault processor, and the running state of the fault processor is read.
Specifically, the polling module is configured to poll and read reset/status registers of other processors of the multi-core system through any one of the processors of the multi-core system, determine whether the other processors are faulty, control the faulty processor to perform a reset operation through any one of the processors that is successfully reset when any one of the processors reads that any one of the other processors is faulty, and read the reset/status registers of the faulty processor in real time, thereby determining a real-time operating state of the faulty processor.
To sum up, in the multi-core system reset device provided in the embodiment of the present application, the obtaining module 100 obtains the reset information of the target processor after the multi-core system executes bus reset; after judging that the target processor is successfully reset according to the reset information, the detection module 200 detects whether all the rest processors of the multi-core system are successfully reset through the target processor; the reset module 300 detects that all the rest processors are successfully reset, and then ends the multi-core reset; and if any processor is detected to be unsuccessfully reset, controlling the register corresponding to the processor which is unsuccessfully reset to reset again through the target processor until all the rest processors of the multi-core system are successfully reset, and ending the multi-core reset. Therefore, the multi-core system resetting device according to the embodiment of the application firstly performs resetting detection on the first processors (namely target processors) arranged in the multi-core system according to the starting sequence, so that the flexibility of the multi-core system is improved; then, the target processor which is successfully reset carries out reset detection and reset operation on the rest processors until all the processors of the multi-core system are successfully reset, so that the condition that the processors are idle due to accidental failure of the processors available for the multi-core system can be avoided, and when any processor is abnormal, the processor is timely reset to prevent application from being failed, and the stability and reliability of the multi-core system are further improved; in addition, each processor in the multi-core system can read and control registers of other processors, and the situation of bus errors is avoided.
The embodiment of the present application further provides a computer device, where the computer device may be a server, and a schematic structural diagram of the computer device is shown in fig. 6. The computer device includes a processor, a memory, a network interface, and a database connected by a system bus. Wherein the computer designed processor is used to provide computational and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used for storing data such as a multi-core system reset method and the like. The network interface of the computer device is used for communicating with an external terminal through a network connection.
The computer program is executed by a processor to implement a multi-core system reset method. The multi-core system resetting method comprises the following steps: firstly, after a multi-core system executes bus reset, acquiring reset information of a target processor; then after the target processor is judged to be successfully reset according to the reset information, whether all the rest processors of the multi-core system are successfully reset is detected through the target processor; if all the rest processors are detected to be successfully reset, ending the multi-core reset; and if any processor is detected to be unsuccessfully reset, controlling the register corresponding to the processor which is unsuccessfully reset to reset again through the target processor until all the rest processors of the multi-core system are successfully reset, and ending the multi-core reset.
An embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the computer program implements a multi-core system reset method, including the steps of: firstly, after a multi-core system executes bus reset, acquiring reset information of a target processor; then after the target processor is judged to be successfully reset according to the reset information, whether all the rest processors of the multi-core system are successfully reset is detected through the target processor; if all the rest processors are detected to be successfully reset, ending the multi-core reset; if any processor is detected to be unsuccessfully reset, the target processor controls the register corresponding to the processor which is unsuccessfully reset to be reset again until all the rest processors of the multi-core system are successfully reset, and the multi-core reset is finished.
In the above executed multi-core system reset method, in the embodiment of the present application, reset detection is performed on a first processor (i.e., a target processor) arranged in a multi-core system according to a starting sequence, so that the flexibility of the multi-core system is improved; then, the target processor which is successfully reset carries out reset detection and reset operation on the rest processors until all the processors of the multi-core system are successfully reset, so that the condition that the processors are idle due to accidental failure of the processors available for the multi-core system can be avoided, and when any processor is abnormal, the processor is timely reset to prevent application from being failed, and the stability and reliability of the multi-core system are further improved; in addition, each processor in the multi-core system can read and control registers of other processors, and the situation of bus errors is avoided.
It is to be understood that the foregoing scenarios are only examples, and do not constitute a limitation on application scenarios of the technical solutions provided in the embodiments of the present application, and the technical solutions of the present application may also be applied to other scenarios. For example, as can be known by those skilled in the art, with the evolution of system architecture and the emergence of new service scenarios, the technical solution provided in the embodiments of the present application is also applicable to similar technical problems.
The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments.
The steps in the method of the embodiment of the application can be sequentially adjusted, combined and deleted according to actual needs.
The units in the device in the embodiment of the application can be merged, divided and deleted according to actual needs.
In the present application, the same or similar term concepts, technical solutions and/or application scenario descriptions will be generally described only in detail at the first occurrence, and when the description is repeated later, the detailed description will not be repeated in general for brevity, and when understanding the technical solutions and the like of the present application, reference may be made to the related detailed description before the description for the same or similar term concepts, technical solutions and/or application scenario descriptions and the like which are not described in detail later.
In the present application, each embodiment is described with emphasis, and reference may be made to the description of other embodiments for parts that are not described or illustrated in any embodiment.
The technical features of the technical solution of the present application may be arbitrarily combined, and for brevity of description, all possible combinations of the technical features in the embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, the scope of the present application should be considered as being described in the present application.
Through the description of the foregoing embodiments, it is clear to those skilled in the art that the method of the foregoing embodiments may be implemented by software plus a necessary general hardware platform, and certainly may also be implemented by hardware, but in many cases, the former is a better implementation. Based on such understanding, the technical solutions of the present application may be embodied in the form of a software product, which is stored in a storage medium (e.g., ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal device (e.g., a mobile phone, a computer, a server, a controlled terminal, or a network device) to execute the method of each embodiment of the present application.
In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. The procedures or functions according to the embodiments of the present application are all or partially generated when the computer program instructions are loaded and executed on a computer. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored on a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire (e.g., coaxial cable, fiber optic, digital subscriber line) or wirelessly (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that incorporates one or more of the available media. The usable medium may be a magnetic medium (e.g., floppy Disk, memory Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., Solid State Disk (SSD)), among others.
The above description is only a preferred embodiment of the present application, and not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application, or which are directly or indirectly applied to other related technical fields, are included in the scope of the present application.
Claims (10)
1. A multi-core system reset method is characterized by comprising the following steps:
after the multi-core system executes bus reset, acquiring reset information of a target processor;
after the target processor is judged to be successfully reset according to the reset information, whether all the rest processors of the multi-core system are successfully reset is detected through the target processor;
if all the rest processors are detected to be successfully reset, ending the multi-core reset;
and if any processor is detected to be unsuccessfully reset, controlling the register corresponding to the processor which is unsuccessfully reset to reset again through the target processor until all the rest processors of the multi-core system are successfully reset, and ending the multi-core reset.
2. The multi-core system resetting method of claim 1, wherein the target processor is a first processor in the multi-core system arranged according to a boot sequence, and the boot sequence is set according to an option byte.
3. The multi-core system resetting method of claim 1, wherein the controlling, by the target processor, the register corresponding to the processor that has not been successfully reset to reset comprises:
if the number of times of executing the reset operation on the processor which is not successfully reset is detected to be smaller than a first preset number of times, continuing the reset operation on the processor which is not successfully reset through the target processor until the reset is successful or the number of times of executing the reset operation is larger than or equal to the first preset number of times.
4. The multi-core system resetting method according to claim 3, further comprising:
if the number of times of executing reset operation on the processor which is not successfully reset is detected to be larger than or equal to the first preset number of times and the processor is not successfully reset, the processor which is not successfully reset is judged to be a fault processor, and the fault processor is shielded.
5. The multi-core system resetting method of claim 1, wherein the detecting, by the target processor, whether all of the remaining processors of the multi-core system have been successfully reset comprises:
and reading the register corresponding to each residual processor through the target processor, and judging whether the residual processors are all reset successfully.
6. The multi-core system reset method of claim 1, wherein after the ending multi-core reset, the method further comprises:
polling and reading registers of the rest processors by any processor of the multi-core system;
when any processor reads a processor with a fault in the rest processors, the register of the fault processor is controlled by the processor to reset the fault processor, and the running state of the fault processor is read.
7. The multi-core system resetting method according to claim 6, wherein after the resetting operation of the failing processor is performed by the register controlling the failing processor by any processor, the method further comprises:
if the number of times of executing the reset operation on the fault processor is detected to be less than a second preset number of times, continuing the reset operation on the fault processor until the reset is successful or the number of times of executing the reset operation is greater than or equal to the second preset number of times;
and if the times of executing the reset operation on the fault processor are greater than or equal to a second preset time and the reset is not successful, shielding the fault processor.
8. A multi-core system reset apparatus, comprising:
the system comprises an acquisition module, a reset module and a control module, wherein the acquisition module is used for acquiring the reset information of a target processor after the multi-core system executes bus reset;
the detection module is used for detecting whether all the rest processors of the multi-core system are successfully reset or not through the target processor after the target processor is judged to be successfully reset according to the reset information;
the reset module is used for finishing multi-core reset if detecting that all the rest processors are successfully reset; and if any processor is detected to be unsuccessfully reset, controlling the register corresponding to the processor which is unsuccessfully reset to reset again through the target processor until all the rest processors of the multi-core system are successfully reset, and ending the multi-core reset.
9. A computer device comprising a memory and a processor, the memory storing a computer program, wherein the processor when executing the computer program implements the steps of the multi-core system reset method of any of claims 1 to 7.
10. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the multi-core system resetting method of any one of claims 1 to 7.
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