CN102981587A - Reset method suitable for multi-core processors - Google Patents
Reset method suitable for multi-core processors Download PDFInfo
- Publication number
- CN102981587A CN102981587A CN2012105794874A CN201210579487A CN102981587A CN 102981587 A CN102981587 A CN 102981587A CN 2012105794874 A CN2012105794874 A CN 2012105794874A CN 201210579487 A CN201210579487 A CN 201210579487A CN 102981587 A CN102981587 A CN 102981587A
- Authority
- CN
- China
- Prior art keywords
- processor
- reset
- counter
- detection module
- request
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Abstract
The invention discloses a reset method suitable for multi-core processors, and relates to a reset network design method for the multi-core processors in the field of an on-chip processor network system. Based on the existing related standard and technology of the on-chip processor system, the invention designs a more practical reset device. Any processor can initiate a reset request, and then a reset operation can be performed to a target processor through the shared reset device. The reset method has the advantages that a processor in a normal work state can initiate a reset request and then a target processor at failure is safely reset, so that reset operation is realized among the multi-core processors.
Description
Technical field
The present invention relates in the on-chip processor system field method of the reseting network design between the polycaryon processor.
Background technology
Along with the progress of science and technology, traditional single processor can't satisfy application requirements, and a lot of designs have all adopted the mode of polycaryon processor to realize.But after using polycaryon processor, the relation that resets between the multinuclear just becomes comparatively complicated.
When a processor is in indefinite state, need the normal processor of duty to carry out the unusual processor of duty is carried out reset operation.If directly reset, may cause the problem that Self-resetting etc. can't be expected after the feedback that can't reset, reset.
Summary of the invention
Technical matters to be solved by this invention just provides a kind of by the normal processor initiation of duty, and the processor that will be in abnormality carries out the method for reset operation.The invention enables random processor can carry out safe and effective reset operation, thereby guarantee the correctness of on-chip processor system works.
The object of the present invention is achieved like this, and a kind of repositioning method that is applicable to polycaryon processor comprises it is characterized in that detection module and the reset logic module of a plurality of processors and each processor working state may further comprise the steps:
When 1. a plurality of processors worked, duty detection module separately can carry out duty to processor and detect, and testing result is sent in the status register; When one of them processor working state was unusual, state detection module produced abnormal level; When processor was working properly, state detection module was with abnormal level set normal level;
2. that the abnormal level that produces is sent to reseting register is medium pending for detection module; Processor meeting poll reseting register working properly exists unusually when poll goes out reseting register, can produce reset request, and this reseting request signal can start a counter, and counter can be counted automatically;
3. counter is initiated the processor of reset request and can be initiated to cancel the reset request operation, with counter clear 0 when counting does not reach overflow value;
4. after counter reaches overflow value, will produce reset signal, give the reset signal group that is formed by each processor reset end, the target faults processor will be carried out reset operation.
Above-mentioned steps is finished reset operation.
The present invention the is the processor of the initiation reset operation described in the step 2., can determine to initiate the priority of reset operation according to putting in order.
The present invention the 4. counter described in the step presets maximal value, and the acquiescence initial value during for circuit design can be configured by random processor.
The present invention compares with background technology, has following advantage:
(1) reset operation of the present invention can be initiated by the normal processor of any duty.
(2) the present invention initiates reset operation, with the operation that finally resets successfully, between have certain time interval, in this time interval, can cancel reset operation.
Description of drawings
Fig. 1 is the functional-block diagram of the embodiment of the invention.The processor of initiating reset request among Fig. 1 is A1, and reseting request signal is A2, and the reset request cancelling signal is A2, reseting register is B1, and the reset request counter is B2, and the counter overflow decision device is B3, the reset signal group is B4, and the target processor that is reset is C.
Fig. 2 is the catenation principle block diagram of the embodiment of the invention.The normal processor of duty is 111,121,131 ..., the duty detection module of each processor is 111,121,131 ..., the processor that duty is unusual is 320, the duty detection module is 310.The condition indicative signal that detection module produces is connected to reseting register 210, the counter that the request signal that is reset activates is 220, the reset signal that produces after the counter overflow is connected to reset signal group 230, and the reset signal group is connected to the reset terminal of all processors.
Embodiment
With reference to Fig. 1, a kind of repositioning method that is applicable to polycaryon processor of the present invention comprises it is characterized in that detection module and the reset logic module of a plurality of processors and each processor working state may further comprise the steps:
When 1. a plurality of processors worked, duty detection module separately can carry out duty to processor and detect, and testing result is sent in the status register.When one of them processor working state was unusual, state detection module produced abnormal level; When processor was working properly, state detection module was with abnormal level set normal level;
2. that the abnormal level that produces is sent to reseting register is medium pending for detection module; Processor meeting poll reseting register working properly exists unusually when poll goes out reseting register, can produce reset request, and this reseting request signal can start a counter, and counter can be counted automatically;
3. counter is initiated the processor of reset request and can be initiated to cancel the reset request operation, with counter clear 0 when counting does not reach overflow value;
4. after counter reaches overflow value, will produce reset signal, give the reset signal group that is formed by each processor reset end, the target faults processor will be carried out reset operation.
Claims (3)
1. repositioning method that is applicable to polycaryon processor comprises it is characterized in that detection module and the reset logic module of a plurality of processors and each processor working state may further comprise the steps:
When 1. a plurality of processors worked, duty detection module separately can carry out duty to processor and detect, and testing result is sent in the status register; When one of them processor working state was unusual, state detection module produced abnormal level; When processor was working properly, state detection module was with abnormal level set normal level;
2. that the abnormal level that produces is sent to reseting register is medium pending for detection module; Processor meeting poll reseting register working properly exists unusually when poll goes out reseting register, can produce reset request, and this reseting request signal can start a counter, and counter can be counted automatically;
3. counter is initiated the processor of reset request and can be initiated to cancel the reset request operation, with counter clear 0 when counting does not reach overflow value;
4. after counter reaches overflow value, will produce reset signal, give the reset signal group that is formed by each processor reset end, the target faults processor will be carried out reset operation;
Above-mentioned steps is finished reset operation.
2. a kind of repositioning method that is applicable to polycaryon processor according to claim 1 is characterized in that: the processor that step is initiated reset operation in 2. can according to putting in order, determine to initiate the priority of reset operation.
3. a kind of repositioning method that is applicable to polycaryon processor according to claim 1 is characterized in that: the counter of step described in 4. presets maximal value, and the acquiescence initial value during for circuit design can be configured by random processor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012105794874A CN102981587A (en) | 2012-12-28 | 2012-12-28 | Reset method suitable for multi-core processors |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012105794874A CN102981587A (en) | 2012-12-28 | 2012-12-28 | Reset method suitable for multi-core processors |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102981587A true CN102981587A (en) | 2013-03-20 |
Family
ID=47855721
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012105794874A Pending CN102981587A (en) | 2012-12-28 | 2012-12-28 | Reset method suitable for multi-core processors |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102981587A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106844082A (en) * | 2017-01-18 | 2017-06-13 | 联想(北京)有限公司 | Processor predictive failure analysis method and device |
| CN108121630A (en) * | 2016-11-29 | 2018-06-05 | 株式会社理光 | Electronic device, method for restarting and recording medium |
| CN114527857A (en) * | 2022-02-15 | 2022-05-24 | 深圳市航顺芯片技术研发有限公司 | Multi-core system resetting method, device and equipment and readable storage medium |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101149636A (en) * | 2007-10-23 | 2008-03-26 | 华为技术有限公司 | Repositioning system and method |
| CN101297256A (en) * | 2005-10-25 | 2008-10-29 | Nxp股份有限公司 | Data processing arrangement comprising a reset facility |
| CN101324855A (en) * | 2008-08-12 | 2008-12-17 | 杭州华三通信技术有限公司 | Method, system, component and multi-CPU equipment for detecting auxiliary CPU operating status |
-
2012
- 2012-12-28 CN CN2012105794874A patent/CN102981587A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101297256A (en) * | 2005-10-25 | 2008-10-29 | Nxp股份有限公司 | Data processing arrangement comprising a reset facility |
| CN101149636A (en) * | 2007-10-23 | 2008-03-26 | 华为技术有限公司 | Repositioning system and method |
| CN101324855A (en) * | 2008-08-12 | 2008-12-17 | 杭州华三通信技术有限公司 | Method, system, component and multi-CPU equipment for detecting auxiliary CPU operating status |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108121630A (en) * | 2016-11-29 | 2018-06-05 | 株式会社理光 | Electronic device, method for restarting and recording medium |
| CN108121630B (en) * | 2016-11-29 | 2021-07-16 | 株式会社理光 | Electronic device, restart method, and recording medium |
| CN106844082A (en) * | 2017-01-18 | 2017-06-13 | 联想(北京)有限公司 | Processor predictive failure analysis method and device |
| CN114527857A (en) * | 2022-02-15 | 2022-05-24 | 深圳市航顺芯片技术研发有限公司 | Multi-core system resetting method, device and equipment and readable storage medium |
| CN114527857B (en) * | 2022-02-15 | 2024-04-19 | 深圳市航顺芯片技术研发有限公司 | Multi-core system reset method, device, equipment and readable storage medium |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103324546B (en) | A kind of method and device of watchdog service delay | |
| CN107704067B (en) | SoC chip resetting method and resetting system | |
| CN102981587A (en) | Reset method suitable for multi-core processors | |
| US9218259B2 (en) | Computing device and method for testing SOL function of a motherboard of the computing device | |
| CN107436414B (en) | Method and device for testing effectiveness of BBU in memory system | |
| EP3588661A1 (en) | Battery pack management system and control method thereof | |
| CN104502883B (en) | The abnormality detection and solution of computation chip | |
| CN103746890A (en) | Competition model RS-485 bus multimaster communication system and working method thereof | |
| CN107017678B (en) | Charging management device and method thereof | |
| CN110834541A (en) | Safety monitoring method and related device | |
| CN103529281B (en) | Voltage detecting circuit, electronic equipment and the automobile of the real-time OBD of a kind of all standing | |
| CN106502811A (en) | A kind of 1553B bus communications fault handling method | |
| CN106155826A (en) | For detecting and process the method and system of mistake in bus structures | |
| US9882400B2 (en) | Power cabinet management method and apparatus, and battery management system | |
| KR20130009086A (en) | Advanced watchdog apparatus and method thereof | |
| CN103729222A (en) | Loading device and method of configuration file | |
| WO2018192440A1 (en) | Charging control method, power adapter and mobile terminal | |
| US20140009166A1 (en) | Monitoring Circuit with a Signature Watchdog | |
| CN108561274B (en) | Fan yaw correction method and device, computer device and readable storage medium | |
| CN116192534A (en) | Train control data communication transmission method, device, equipment and storage medium | |
| CN102810840B (en) | Voltage protection system | |
| EP2988476A1 (en) | Method and apparatus for processing operation on endpoint peripheral | |
| CN103971058A (en) | Method and system for protection of multi-chip interconnection and interlocking | |
| CN104219012B (en) | The EMC test system of transponder transport module and method of testing | |
| JP2011227786A (en) | Microcomputer control system, charging device using the same and photovoltaic power supply system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20130320 |