CN103971058A - Method and system for protection of multi-chip interconnection and interlocking - Google Patents
Method and system for protection of multi-chip interconnection and interlocking Download PDFInfo
- Publication number
- CN103971058A CN103971058A CN201410204304.XA CN201410204304A CN103971058A CN 103971058 A CN103971058 A CN 103971058A CN 201410204304 A CN201410204304 A CN 201410204304A CN 103971058 A CN103971058 A CN 103971058A
- Authority
- CN
- China
- Prior art keywords
- control node
- normal
- soft
- hard
- node
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 22
- 239000004065 semiconductor Substances 0.000 claims abstract description 24
- GOLXNESZZPUPJE-UHFFFAOYSA-N spiromesifen Chemical compound CC1=CC(C)=CC(C)=C1C(C(O1)=O)=C(OC(=O)CC(C)(C)C)C11CCCC1 GOLXNESZZPUPJE-UHFFFAOYSA-N 0.000 claims description 19
- 238000007689 inspection Methods 0.000 claims description 16
- 238000000605 extraction Methods 0.000 claims description 9
- 230000003993 interaction Effects 0.000 claims description 6
- 230000000903 blocking effect Effects 0.000 claims description 3
- 238000001514 detection method Methods 0.000 abstract description 4
- 230000002159 abnormal effect Effects 0.000 description 6
- 230000001351 cycling effect Effects 0.000 description 2
- 230000003252 repetitive effect Effects 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000000977 initiatory effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
- G06F21/57—Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
- G06F21/572—Secure firmware programming, e.g. of basic input output system [BIOS]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- General Engineering & Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention relates to a method for protection of multi-chip interconnection and interlocking. The method is characterized by comprising the following steps that A, all functions of a software control node and a hardware control node are automatically detected; B, whether the function states of the software control node and the hardware control node are normal or not is judged; C, a firmware version feature code of the hardware control node is extracted and sent to the software control node, high resistance bus parallel operation is conducted, and driving of a power semiconductor is forbidden; D, whether a received firmware version is compatible with the hardware control node or not is judged; E, whether the hardware control node is compatible with all received node versions and the version of the hardware control node or not is judged, power is supplied, the system state is detected, and a system is protected in the failure state when a CPLD/FPGA is powered on or the version is not matched; after software of the CPLD/FPGA or an MCU/DSP is updated, a compatibility detection strategy is provided, and system failure caused by unmatched software is avoided.
Description
Technical field
The invention belongs to chip protection field, relate in particular to guard method and the system of the interconnected interlocking of a kind of multi-chip.
Background technology
In multi-chip solution, the microprocessors such as MCU/DSP cause program fleet extremely due to what software was carried out, may send out the driving of power semiconductor by mistake or cause it to drive abnormal, cause the infringement of power semiconductor.More seriously,, in parallel system, if the unit that occurs abnormal MCU/DSP place is not departed from away from parallel system, even can cause the collapse of parallel system.
The elementary cell of the topworks of CPLD/FPGA is trigger and logic gate combination, they there will not be the program exception race of the microprocessors such as MCU/DSP to fly substantially, so common scheme is to utilize CPLD/FPGA to monitor MCU/DSP, when initiating it when abnormal, block the driving of power semiconductor, and thrown off and being connected of various parallel operation buses.In this method, do not consider the problems such as CPLD/FPGA inefficacy.
Summary of the invention
The invention provides the guard method of the interconnected interlocking of a kind of multi-chip, be intended to solve the problem that Software match causes thrashing etc.
The present invention is achieved in that the guard method of the interconnected interlocking of a kind of multi-chip, said method comprising the steps of:
A, soft, firmly control node all functions and automatically detect;
B, judge soft, whether firmly control nodal function state normal, if functional status is normal, puts the normal position of hard control node state effectively and perform step C, soft control node execution step D, as undesired in functional status, circulation execution step A;
C, extract hard control node firmware version feature code and mail to soft control node, and high-impedance state parallel operation bus and forbid that power semiconductor drives;
D, judge that the compatibility of the hard control node firmware version receiving is whether compatible, as compatibility, extract firmware version condition code and mail to hard control node, and the self-inspection of soft control node finishes to enter normal work; As incompatible, perform step C;
E, the hard control of judgement node add to receiving the version of all nodes whether the version of self has compatibility; As there is compatibility, firmly control node self-inspection and finish to enter normal work; If not thering is compatibility, perform step D.
Further technical scheme of the present invention is: described steps A comprises the following steps:
A1, firmly control node self all functions is detected;
A2, soft control node forbid that power semiconductor drives and remove the passage of the interaction data of all and external control node;
A3, soft control node detect self all functions.
Further technical scheme of the present invention is: described step B comprises the following steps:
Whether B1, judgement firmly control nodal function state be normal, as normal in functional status, puts the normal significance bit of hard control node state and perform step C; As undesired in functional status, perform step A1;
B2, judge that whether soft control nodal function state is normal, as normal in functional status, perform step B3; As undesired in functional status, perform step A3.
In B3, judgment device unit, whether hard control node state is normal, as normally, just performing step C; As undesired, circulation step B3.
Further technical scheme of the present invention is: described step C comprises the following steps:
C1, mail to soft control node in hard control Node extraction firmware version condition code;
C2, by parallel operation bus high-impedance state and forbid power semiconductor drive.
Further technical scheme of the present invention is: the normal position of described hard control node all component SM set mode, bit stream coding is carried out in the normal position of mode bit.
Further technical scheme of the present invention is: each controls node firmware incompatible version, and software node does not all send and drives and bus data to hardware node.
Another object of the present invention is to provide the protection system of the interconnected interlocking of a kind of multi-chip, this protection system comprises:
Selftest module, for soft, firmly control node all functions and automatically detect;
Judge module, soft for judging, whether firmly control nodal function state normal, if functional status is normal, puts the normal position of hard control node state effectively and perform step C, soft control node execution step D, as undesired in functional status, circulation execution step A;
Extract stop module, mail to soft control node for extracting hard control node firmware version feature code, and high-impedance state parallel operation bus and forbid power semiconductor drive;
A compatibility determination module, whether compatible for judging the compatibility of hard control node firmware version of reception, as compatibility, extract firmware version condition code and mail to hard control node, and the self-inspection of soft control node finishes to enter normal work; As incompatible, perform step C;
Secondary compatibility determination module, for judging that hard control node adds to receiving the version of all nodes whether the version of self has compatibility; As there is compatibility, firmly control node self-inspection and finish to enter normal work; If not thering is compatibility, perform step D.
Further technical scheme of the present invention is: described selftest module comprises:
Hard control node self-test unit, detects self all functions for hard control node;
Forbid unit, forbid that for soft control node power semiconductor drives and remove the passage of the interaction data of all and external control node;
Soft control node self-test unit, detects self all functions for soft control node.
Further technical scheme of the present invention is: described judge module comprises:
Hard control nodal function judging unit, whether normal for judging hard control nodal function state, as normal in functional status, put the normal significance bit of hard control node state and perform step C; As undesired in functional status, perform step A1;
Soft control nodal function judging unit, whether normal for judging soft control nodal function state, as normal in functional status, perform step B3; As undesired in functional status, perform step A3;
Equipment state judging unit, whether normal for the hard control in judgment device unit node state, as normally, just performing step C; As undesired, circulation step B3.
Further technical scheme of the present invention is: described extraction stops module to comprise:
Extract output unit, for mailing to soft control node in hard control Node extraction firmware version condition code;
Blocking unit, for by parallel operation bus high-impedance state and forbid power semiconductor drive.
The invention has the beneficial effects as follows: system state is detected powering on, solved while there is failure state or compatibility issue when CPLD/FPGA powers on, to the protection of system; After CPLD/FPGA or MCU/DSP software upgrading, compatible detection strategy is provided, solve software and do not mated the thrashing causing.
Brief description of the drawings
Fig. 1 is soft control node overhaul flow chart in the guard method of the interconnected interlocking of multi-chip that provides of the embodiment of the present invention;
Fig. 2 is hard control node overhaul flow chart in the guard method of the interconnected interlocking of multi-chip that provides of the embodiment of the present invention;
Fig. 3 is the general frame figure of contact system in the guard method of the interconnected interlocking of multi-chip that provides of the embodiment of the present invention.
Embodiment
That Fig. 1,2 shows is soft in the guard method of the interconnected interlocking of multi-chip provided by the invention, firmly control node overhaul flow chart, and details are as follows for it:
The protection process of self-test of soft control node is wherein as follows:
In step S1, after device power, soft control node prepares self to carry out self-verifying.
In step S2, before soft control node starts that self is carried out to self-verifying and starts, soft control node forbids that power semiconductor drives and remove all and interaction data external control node; Be better for soft control node can complete when the self-inspection, soft control node drives semiconductor and all forbid with the passage of extraneous swap data, makes it complete automatic detection and be not subject to the impact of external data.
In step S3, the soft control node of equipment detects automatically to self function.
In step S4, judge that whether the functional status of soft control node is normal, if arbitration functions state is normal, perform step S5; If arbitration functions state is undesired, perform step S3, in this circulation S3, S4 step, until arbitration functions state could perform step S5. after normal in step S4
In step S5, normal when judgement all functions state in step S4 after, here whether the hard control node state in unit is normally judged, if it is normal firmly to control node, perform step S6; If it is undesired firmly to control node, repetitive cycling step S5, until firmly control node state, could perform step S6.
In step S6, whether the compatibility of the hard control node firmware version that judgement receives is compatible, if compatible, performs step S7; If incompatible, again accept feature and repeated execution of steps S6 that hard control node sends, until compatible normal position is at execution step S7.
In step S7, after having judged that hard control node diagnostic code compatibility is normal, the condition code of soft control Node extraction firmware version sends to hard control node.
In step S8, after all detections, all functions all can both be worked normally, and the now self-inspection of soft control node finishes to enter normal duty.
The protection process of self-test of wherein firmly controlling node is as follows:
In step S11, after device power, firmly control node and prepare self to carry out self-verifying.
In step S12, the hard control node of equipment detects automatically with all functions of self.
In step S13, normal when the functional status of the hard control node in judgment device, if functional status is normal, perform step S14; If functional status is undesired, perform step S13.
In step S14, in the time that the functional status of hard control node is normal, will firmly controls node state and be placed in normal active position.
In step S15,, firmly control the condition code that node can extract firmware version and mail to soft control node in active position at hard control node.
In step S16, the condition code of firmware version is mail to after soft control node, firmly controlling node can fall clean ice bus high-impedance state, and forbids the driving of all power semiconductors of firmly controlling node, and the communication of cutting off data with this, avoids occurring the interference of data.
In step S17, receive after the condition code of hard control node at soft control node, errorless by verifying, can send the condition code of soft control node to hard control node, receiving after condition code and firmly control node, the version of all nodes that receive is being added to the version of self does compatible inspection.
In step S18, firmly control node the information of the soft control node receiving is carried out to compatible judgement, if there is compatibility, perform step S19; If do not there is compatibility, repetitive cycling step S17, S18 step, until there is compatibility, at execution step S19.
In step S19, detect and have after compatibility at hard control node, firmly control node self-inspection and complete, enter normal duty.
In the present invention the equipment at a multi-chip control system place is referred to as to " unit ", the system being composed of multiple units is referred to as to " parallel system ".In unit, various control chips are referred to as " control node ", MCU/DSP are referred to as to " soft control node ", CPLD/FPGA are referred to as to " firmly controlling node ".For the general frame of realizing the object of the invention parallel system as shown in Figure 3.Wherein in unit, all soft control nodes are all directly connected on hard control node, and the internodal exchange of soft control can only be by hard control node; The information of the responsible all unit of hard control node and parallel operation bus is mutual simultaneously.Hard control node itself does not independently produce the driving of any power semiconductor and independently sends bus data, and all drivings and bus data all derive from soft control node.Due to the feature of chip, as long as external circuit is normal, firmly controlling node can be not abnormal suddenly in normal course of operation, just abnormal while only likely just having powered on.Soft control node, in the time powering on and in normal course of operation, all may occur abnormal.
When soft control node powers on, forbidden that all power semiconductors drive and bus data, firmly controlled its each (PCC) power of node self-inspection, while only having all component normal, bit stream coding is carried out to the normal position of state in the normal position of its state of ability set simultaneously.Suppose before firmly controlling node powers on extremely, so soft control node receives behind abnormality position, circular wait, and all like this drivings and bus signals are all invalid, cause that whole system lost efficacy extremely while so just having solved hard control node failure.
When each control node in unit needs firmware upgrade, if when the firmware version of certain node mistake leakage upgrading or each node is incompatible, because soft control node has added the firmware version inspection of hard control node, soft control node all can not send and drive and bus data to hard control node; Hard control node carries out compliance check to the firmware version of all control nodes in unit, if incompatible, still conductively-closed of the driving of whole unit, bus is great-great-grandfather's state still.So just solve the incompatible thrashing causing of firmware version.Need to carry out bit stream coding to firmware version number equally.
Another object of the present invention is to provide the protection system of the interconnected interlocking of a kind of multi-chip, this protection system comprises:
Selftest module, for soft, firmly control node all functions and automatically detect;
Judge module, soft for judging, whether firmly control nodal function state normal, if functional status is normal, puts the normal position of hard control node state effectively and perform step C, soft control node execution step D, as undesired in functional status, circulation execution step A;
Extract stop module, mail to soft control node for extracting hard control node firmware version feature code, and high-impedance state parallel operation bus and forbid power semiconductor drive;
A compatibility determination module, whether compatible for judging the compatibility of hard control node firmware version of reception, as compatibility, extract firmware version condition code and mail to hard control node, and the self-inspection of soft control node finishes to enter normal work; As incompatible, perform step C;
Secondary compatibility determination module, for judging that hard control node adds to receiving the version of all nodes whether the version of self has compatibility; As there is compatibility, firmly control node self-inspection and finish to enter normal work; If not thering is compatibility, perform step D.
Further technical scheme of the present invention is: described selftest module comprises:
Hard control node self-test unit, detects self all functions for hard control node;
Forbid unit, forbid that for soft control node power semiconductor drives and remove the passage of the interaction data of all and external control node;
Soft control node self-test unit, detects self all functions for soft control node.
Further technical scheme of the present invention is: described judge module comprises:
Hard control nodal function judging unit, whether normal for judging hard control nodal function state, as normal in functional status, put the normal significance bit of hard control node state and perform step C; As undesired in functional status, perform step A1;
Soft control nodal function judging unit, whether normal for judging soft control nodal function state, as normal in functional status, perform step B3; As undesired in functional status, perform step A3;
Equipment state judging unit, whether normal for the hard control in judgment device unit node state, as normally, just performing step C; As undesired, circulation step B3.
Further technical scheme of the present invention is: described extraction stops module to comprise:
Extract output unit, for mailing to soft control node in hard control Node extraction firmware version condition code;
Blocking unit, for by parallel operation bus high-impedance state and forbid power semiconductor drive.
The normal position of described hard control node all component SM set mode, carries out bit stream coding to the normal position of mode bit.
Each controls node firmware incompatible version, and software node does not all send and drives and bus data to hardware node.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments of doing within the spirit and principles in the present invention, be equal to and replace and improvement etc., within all should being included in protection scope of the present invention.
Claims (10)
1. a guard method for the interconnected interlocking of multi-chip, is characterized in that, said method comprising the steps of:
A, soft, firmly control node all functions and automatically detect;
B, judge soft, whether firmly control nodal function state normal, if functional status is normal, puts the normal position of hard control node state effectively and perform step C, soft control node execution step D, as undesired in functional status, circulation execution step A;
C, extract hard control node firmware version feature code and mail to soft control node, and high-impedance state parallel operation bus and forbid that power semiconductor drives;
D, judge that the compatibility of the hard control node firmware version receiving is whether compatible, as compatibility, extract firmware version condition code and mail to hard control node, and the self-inspection of soft control node finishes to enter normal work; As incompatible, perform step C;
E, the hard control of judgement node add to receiving the version of all nodes whether the version of self has compatibility; As there is compatibility, firmly control node self-inspection and finish to enter normal work; If not thering is compatibility, perform step D.
2. guard method according to claim 2, is characterized in that, described steps A comprises the following steps:
A1, firmly control node self all functions is detected;
A2, soft control node forbid that power semiconductor drives and remove all and interaction data external control node;
A3, soft control node detect self all functions.
3. guard method according to claim 2, is characterized in that, described step B comprises the following steps:
Whether B1, judgement firmly control nodal function state be normal, as normal in functional status, puts the normal significance bit of hard control node state and perform step C; As undesired in functional status, perform step A1;
B2, judge that whether soft control nodal function state is normal, as normal in functional status, perform step B3; As undesired in functional status, perform step A3;
In B3, judgment device unit, whether hard control node state is normal, as normally, just performing step C; As undesired, circulation step B3.
4. guard method according to claim 3, is characterized in that, described step C comprises the following steps:
C1, mail to soft control node in hard control Node extraction firmware version condition code;
C2, by parallel operation bus high-impedance state and forbid power semiconductor drive.
5. guard method according to claim 4, is characterized in that, bit stream coding is carried out to the normal position of mode bit in the normal position of described hard control node all component SM set mode.
6. guard method according to claim 5, is characterized in that, each controls node firmware incompatible version, and software node does not all send and drives and bus data to hardware node.
7. a protection system for the interconnected interlocking of multi-chip, is characterized in that, this protection system comprises:
Selftest module, for soft, firmly control node all functions and automatically detect;
Judge module, soft for judging, whether firmly control nodal function state normal, if functional status is normal, puts the normal position of hard control node state effectively and perform step C, soft control node execution step D, as undesired in functional status, circulation execution step A;
Extract stop module, mail to soft control node for extracting hard control node firmware version feature code, and high-impedance state parallel operation bus and forbid power semiconductor drive;
A compatibility determination module, whether compatible for judging the compatibility of hard control node firmware version of reception, as compatibility, extract firmware version condition code and mail to hard control node, and the self-inspection of soft control node finishes to enter normal work; As incompatible, perform step C;
Secondary compatibility determination module, for judging that hard control node adds to receiving the version of all nodes whether the version of self has compatibility; As there is compatibility, firmly control node self-inspection and finish to enter normal work; If not thering is compatibility, perform step D.
8. protection system according to claim 7, is characterized in that, described selftest module comprises:
Hard control node self-test unit, detects self all functions for hard control node;
Forbid unit, forbid that for soft control node power semiconductor drives and remove the passage of the interaction data of all and external control node;
Soft control node self-test unit, detects self all functions for soft control node.
9. protection system according to claim 8, is characterized in that, described judge module comprises:
Hard control nodal function judging unit, whether normal for judging hard control nodal function state, as normal in functional status, put the normal significance bit of hard control node state and perform step C; As undesired in functional status, perform step A1;
Soft control nodal function judging unit, whether normal for judging soft control nodal function state, as normal in functional status, perform step B3; As undesired in functional status, perform step A3;
Equipment state judging unit, whether normal for the hard control in judgment device unit node state, as normally, just performing step C; As undesired, circulation step B3.
10. protection system according to claim 9, is characterized in that, described extraction stops module to comprise:
Extract output unit, for mailing to soft control node in hard control Node extraction firmware version condition code;
Blocking unit, for by parallel operation bus high-impedance state and forbid power semiconductor drive.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410204304.XA CN103971058B (en) | 2014-05-14 | 2014-05-14 | A kind of guard method of multi-chip interconnection interlocking and system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410204304.XA CN103971058B (en) | 2014-05-14 | 2014-05-14 | A kind of guard method of multi-chip interconnection interlocking and system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103971058A true CN103971058A (en) | 2014-08-06 |
| CN103971058B CN103971058B (en) | 2017-03-15 |
Family
ID=51240540
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410204304.XA Active CN103971058B (en) | 2014-05-14 | 2014-05-14 | A kind of guard method of multi-chip interconnection interlocking and system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103971058B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104320279A (en) * | 2014-10-31 | 2015-01-28 | 杭州华三通信技术有限公司 | Service upgrading method and system |
| CN106028474A (en) * | 2016-06-24 | 2016-10-12 | 重庆小目科技有限责任公司 | Dual-control system communication terminal |
| CN117236263A (en) * | 2023-11-15 | 2023-12-15 | 之江实验室 | Multi-core interconnection simulation method and device, storage medium and electronic equipment |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1591329A (en) * | 2003-08-25 | 2005-03-09 | 联想(北京)有限公司 | Intelligent identifying and protecting method for software and hardware |
| CN102064958A (en) * | 2009-11-16 | 2011-05-18 | 库帕技术公司 | Methods and systems for identifying and configuring networked devices |
| US20130069667A1 (en) * | 2011-09-19 | 2013-03-21 | Mirza Akmal Beg | Fault detection for parallel inverters system |
-
2014
- 2014-05-14 CN CN201410204304.XA patent/CN103971058B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1591329A (en) * | 2003-08-25 | 2005-03-09 | 联想(北京)有限公司 | Intelligent identifying and protecting method for software and hardware |
| CN102064958A (en) * | 2009-11-16 | 2011-05-18 | 库帕技术公司 | Methods and systems for identifying and configuring networked devices |
| US20130069667A1 (en) * | 2011-09-19 | 2013-03-21 | Mirza Akmal Beg | Fault detection for parallel inverters system |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104320279A (en) * | 2014-10-31 | 2015-01-28 | 杭州华三通信技术有限公司 | Service upgrading method and system |
| CN104320279B (en) * | 2014-10-31 | 2017-12-15 | 新华三技术有限公司 | A kind of method and system of upgrading service |
| CN106028474A (en) * | 2016-06-24 | 2016-10-12 | 重庆小目科技有限责任公司 | Dual-control system communication terminal |
| CN106028474B (en) * | 2016-06-24 | 2019-06-25 | 重庆小目科技有限责任公司 | A kind of double-control system communication terminal |
| CN117236263A (en) * | 2023-11-15 | 2023-12-15 | 之江实验室 | Multi-core interconnection simulation method and device, storage medium and electronic equipment |
| CN117236263B (en) * | 2023-11-15 | 2024-02-06 | 之江实验室 | Multi-core interconnection simulation method and device, storage medium and electronic equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103971058B (en) | 2017-03-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100568191C (en) | The full-range dog-feeding method of embedded system | |
| EP2663038A1 (en) | Switch chip port management method, main control board, switch board, and system | |
| US9250690B2 (en) | Low-power modes of microcontroller operation with access to configurable input/output connectors | |
| US8732522B2 (en) | System on chip fault detection | |
| CN103809471A (en) | Novel automatic switchover emergency processing device and implementing method thereof | |
| CN101405666A (en) | Method and control and data transmission system for verifying the installation location of a secure communications component | |
| CN103971058A (en) | Method and system for protection of multi-chip interconnection and interlocking | |
| CN101542444A (en) | Security features in interconnect centric architectures | |
| CN104035536A (en) | Monitoring and reset control method of embedded system | |
| CN104010077B (en) | A kind of information processing method and electronic equipment | |
| CN105760241A (en) | Exporting method and system for memory data | |
| CN109301919A (en) | A kind of uninterruptible power supply bypass adapter tube control method | |
| CN108023762A (en) | The server data port study of data exchange unit | |
| CN103199036B (en) | The EFEM of Integrated dispatching system and dispatching method thereof | |
| CN110502369B (en) | Method and device for recovering equipment crash and storage medium | |
| CN102770851B (en) | Recover the stability of unstable bus | |
| EP3240233A1 (en) | Power fail safeguard method, device and system thereof | |
| CN101498971B (en) | Remote control network physical isolation apparatus and its control method | |
| CN101557307A (en) | Dispatch automation system application state management method | |
| CN104571098B (en) | Long-range self-diagnosing method based on Atom platforms | |
| CN103135728B (en) | Power supply start-up control method and system thereof | |
| CN103995759A (en) | High-availability computer system failure handling method and device based on core internal-external synergy | |
| CN108121632A (en) | A kind of guard method of one-board power supply and device | |
| CN104219012B (en) | The EMC test system of transponder transport module and method of testing | |
| CN112187937B (en) | Unpairing method and device, terminal equipment and storage medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20240401 Address after: 518000, Building 1, Software Park, Keji Middle Second Road, Yuehai Street, Nanshan District, Shenzhen City, Guangdong Province, China 402-1 Patentee after: Shenzhen KeSiDa Software Technology Co.,Ltd. Country or region after: China Address before: Floor 4, Building 1, Software Park, High tech Middle Second Road, Nanshan District, Shenzhen, Guangdong 518057 Patentee before: SHENZHEN KSTAR SCIENCE AND TECHNOLOGY Co.,Ltd. Country or region before: China |
|
| TR01 | Transfer of patent right |