CN114527857B - Multi-core system reset method, device, equipment and readable storage medium - Google Patents
Multi-core system reset method, device, equipment and readable storage medium Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
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- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4405—Initialisation of multiprocessor systems
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4406—Loading of operating system
- G06F9/441—Multiboot arrangements, i.e. selecting an operating system to be loaded
Abstract
The application provides a multi-core system resetting method, a device, equipment and a readable storage medium, wherein the method comprises the following steps: acquiring reset information of a target processor after the multi-core system executes bus reset; after judging that the reset of the target processor is successful, detecting whether all the rest processors of the multi-core system are reset successfully or not through the target processor; if yes, ending multi-core reset; if any processor is detected to be not reset successfully, the register corresponding to the processor which is not reset successfully is controlled to reset again through the target processor until all the rest processors of the multi-core system are reset successfully, and the multi-core reset is ended. According to the application, the reset detection and the reset operation are carried out on the rest processors through the target processors which are successfully reset, so that the condition that the processors are idle due to accidental failure of the available processors of the multi-core system can be avoided, and when any processor is abnormal, the reset is carried out in time to prevent the application from being failed, and the stability of the multi-core system is improved.
Description
Technical Field
The present application relates to the field of chip design technologies, and in particular, to a method, an apparatus, a device, and a readable storage medium for resetting a multi-core system.
Background
With the continuous development and improvement of science and technology, the functional requirement on the CPU is also higher and higher, and the functions of the common single-core system cannot meet the application requirements in some technical fields. The following birth has led to multi-core systems, which are increasingly favored by a wide range of users by virtue of their efficiency of execution. With the advent of multi-core systems, technical problems between systems have arisen, particularly about how to coordinate and manage the resetting of multiple cores, and only if the resetting of the CPU is managed, the systems and other components can be in a certain initial state, and normal operation can be started from the initial state.
In the course of conception and implementation of the present application, the inventors found that at least the following problems exist: at present, when all the multi-core CPU chips are not reset successfully, cores with reset failures are shielded, but the reset failures are not necessarily caused by faults of the cores, and temporary incapacity of working possibly caused by instability of clocks, so that accidental reset failures occur; meanwhile, the reset state of other cores is realized by accessing a shared register when the existing multi-core system is reset, so that bus errors are easy to occur when two or more cores operate the shared register at the same time; the existing multi-core system cannot flexibly switch the reset state of other cores after the reset is successful, so that software reset cannot be generated when external interference or artificial damage is caused; in addition, the existing multi-core system reset technology cannot flexibly control which core has priority to BOOT when the system is started for the first time, and has low flexibility.
The foregoing description is provided for general background information and does not necessarily constitute prior art.
Disclosure of Invention
In view of the above technical problems, the present application provides a method, an apparatus, a device, and a readable storage medium for resetting a multi-core system, where a target processor that is successfully reset performs a reset detection and a reset operation on the remaining processors, so as to avoid the idle condition of the processors caused by accidental failure of available processors of the multi-core system, and improve the stability of the multi-core system.
In order to solve the technical problems, the application provides a multi-core system resetting method, which comprises the following steps:
after the multi-core system executes bus reset, acquiring reset information of a target processor;
After judging that the reset of the target processor is successful according to the reset information, detecting whether all the rest processors of the multi-core system are reset successfully or not through the target processor;
if all the rest processors are detected to be successfully reset, ending the multi-core reset;
If any processor is detected to be not reset successfully, the register corresponding to the processor which is not reset successfully is controlled to reset again through the target processor until all the rest processors of the multi-core system are reset successfully, and the multi-core reset is ended.
Optionally, the target processor is a first processor in the multi-core system, where the first processor is arranged in a startup order, and the startup order is set according to an option byte.
Optionally, the resetting of the register corresponding to the processor which is not successfully reset is controlled by the target processor, specifically includes:
If the number of times of executing the reset operation on the unsuccessful reset processor is detected to be smaller than a first preset number of times, continuing to execute the reset operation on the unsuccessful reset processor through the target processor until the number of times of resetting success or executing the reset operation is larger than or equal to the first preset number of times.
Optionally, the multi-core system reset method further includes:
If the number of times of executing the reset operation on the unsuccessfully reset processor is detected to be greater than or equal to the first preset number of times and is unsuccessfully reset, judging that the unsuccessfully reset processor is a fault processor, and shielding the fault processor.
Optionally, the detecting, by the target processor, whether all the remaining processors of the multi-core system are reset successfully includes:
And reading the corresponding register of each residual processor through the target processor, and judging whether each residual processor is reset successfully or not.
Optionally, after the ending multi-core reset, the method further comprises:
Polling and reading registers of the rest processors by any processor of the multi-core system;
when any processor reads that the rest processors have fault processors, the registers of the fault processors are controlled by any processor to carry out reset operation on the fault processors, and the running states of the fault processors are read.
Optionally, after the resetting operation of the fault processor by the register of the fault processor controlled by the any processor, the method further includes:
If the times of executing the reset operation on the fault processor are detected to be smaller than the second preset times, continuing to execute the reset operation on the fault processor until the reset is successful or the times of executing the reset operation are larger than or equal to the second preset times;
and if the number of times of executing the reset operation on the fault processor is greater than or equal to a second preset number of times and the fault processor is not successfully reset, shielding the fault processor.
Correspondingly, the application also provides a multi-core system resetting device, which comprises:
the acquisition module is used for acquiring reset information of the target processor after the multi-core system executes bus reset;
the detection module is used for detecting whether all the rest processors of the multi-core system are successfully reset through the target processor after judging that the target processor is successfully reset according to the reset information;
the reset module is used for ending multi-core reset if all the rest processors are detected to be reset successfully; if any processor is detected to be not reset successfully, the register corresponding to the processor which is not reset successfully is controlled to reset again through the target processor until all the rest processors of the multi-core system are reset successfully, and the multi-core reset is ended.
The application also provides computer equipment, which comprises a memory and a processor, wherein the memory stores a computer program, and the processor realizes the steps of any multi-core system resetting method when executing the computer program.
The application also proposes a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the multi-core system reset method of any of the above.
The embodiment of the invention has the following beneficial effects:
As described above, the method, apparatus, device and readable storage medium for resetting a multi-core system provided by the present application, where the method includes: after the multi-core system executes bus reset, acquiring reset information of a target processor; after judging that the reset of the target processor is successful according to the reset information, detecting whether all the rest processors of the multi-core system are reset successfully or not through the target processor; if all the rest processors are detected to be successfully reset, ending the multi-core reset; if any processor is detected to be not reset successfully, the register corresponding to the processor which is not reset successfully is controlled to reset again through the target processor until all the rest processors of the multi-core system are reset successfully, and the multi-core reset is ended. According to the multi-core system resetting method, firstly, resetting detection is carried out on the first arranged target processors in the starting sequence of the multi-core system, so that the flexibility of the multi-core system is improved; then, carrying out reset detection and reset operation on the rest processors through the target processors which are successfully reset until all processors of the multi-core system are successfully reset, so that the condition that the processors are idle due to accidental failure of the available processors of the multi-core system can be avoided, and when any processor is abnormal, the reset of the processors is carried out in time to prevent the application from being failed, and the stability and the reliability of the multi-core system are further improved; in addition, each processor in the multi-core system can read and control registers of other processors, so that bus errors are avoided.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application. In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, and it will be obvious to those skilled in the art that other drawings can be obtained from these drawings without inventive effort.
FIG. 1 is a schematic flow chart of a first implementation of a method for resetting a multi-core system according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a multi-core system reset system according to an embodiment of the present application;
FIG. 3 is a flowchart illustrating a second implementation of a method for resetting a multi-core system according to an embodiment of the present application;
FIG. 4 is a flowchart illustrating a third implementation of a method for resetting a multi-core system according to an embodiment of the present application;
FIG. 5 is a schematic diagram of a multi-core system reset device according to an embodiment of the present application;
Fig. 6 is a schematic structural diagram of a computer device according to an embodiment of the present application.
The achievement of the objects, functional features and advantages of the present application will be further described with reference to the accompanying drawings, in conjunction with the embodiments. Specific embodiments of the present application have been shown by way of the above drawings and will be described in more detail below. The drawings and the written description are not intended to limit the scope of the inventive concepts in any way, but rather to illustrate the inventive concepts to those skilled in the art by reference to the specific embodiments.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application. Rather, they are merely examples of apparatus and methods consistent with aspects of the application as detailed in the accompanying claims.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the element defined by the phrase "comprising one … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element, and furthermore, elements having the same name in different embodiments of the application may have the same meaning or may have different meanings, the particular meaning of which is to be determined by its interpretation in this particular embodiment or by further combining the context of this particular embodiment.
It should be understood that although the terms first, second, third, etc. may be used herein to describe various information, these information should not be limited by these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope herein. The word "if" as used herein may be interpreted as "at … …" or "at … …" or "in response to a determination" depending on the context. Furthermore, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and/or "including" specify the presence of stated features, steps, operations, elements, components, items, categories, and/or groups, but do not preclude the presence, presence or addition of one or more other features, steps, operations, elements, components, items, categories, and/or groups. The terms "or", "and/or", "including at least one of", and the like, as used herein, may be construed as inclusive, or mean any one or any combination. For example, "including at least one of: A. b, C "means" any one of the following: a, A is as follows; b, a step of preparing a composite material; c, performing operation; a and B; a and C; b and C; a and B and C ", again as examples," A, B or C "or" A, B and/or C "means" any of the following: a, A is as follows; b, a step of preparing a composite material; c, performing operation; a and B; a and C; b and C; a and B and C). An exception to this definition will occur only when a combination of elements, functions, steps or operations are in some way inherently mutually exclusive.
It should be understood that, although the steps in the flowcharts in the embodiments of the present application are shown in order as indicated by the arrows, these steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited in order and may be performed in other orders, unless explicitly stated herein. Moreover, at least some of the steps in the figures may include multiple sub-steps or stages that are not necessarily performed at the same time, but may be performed at different times, the order of their execution not necessarily occurring in sequence, but may be performed alternately or alternately with other steps or at least a portion of the other steps or stages.
The words "if", as used herein, may be interpreted as "at … …" or "at … …" or "in response to a determination" or "in response to a detection", depending on the context. Similarly, the phrase "if determined" or "if detected (stated condition or event)" may be interpreted as "when determined" or "in response to determination" or "when detected (stated condition or event)" or "in response to detection (stated condition or event), depending on the context.
It should be noted that, in this document, step numbers such as S10 and S20 are adopted, and the purpose of the present application is to more clearly and briefly describe the corresponding content, and not to constitute a substantial limitation on the sequence, and those skilled in the art may execute S20 first and then execute S10 when implementing the present application, which is within the scope of protection of the present application.
It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
In the following description, suffixes such as "module", "part" or "unit" for representing elements are used only for facilitating the description of the present application, and have no specific meaning per se. Thus, "module," "component," or "unit" may be used in combination.
Firstly, the application scenario provided by the application is introduced, for example, a multi-core system resetting method, device, equipment and readable storage medium are provided, which can perform resetting detection and resetting operation on each processor of the multi-core system, and improve the stability and flexibility of the multi-core resetting system.
Referring to fig. 1, fig. 1 is a flowchart illustrating a first implementation of a multi-core system reset method according to an embodiment of the present application. The multi-core system reset method specifically comprises the following steps:
s10, after the multi-core system executes bus reset, acquiring reset information of the target processor.
It should be noted that, the multi-core system includes a plurality of cores, and each core is a processor, such as a CPU.
Specifically, for step S10, after the multi-core system performs the bus reset operation, all processors in the multi-core system are reset again, and then the reset information of the target processor after the multi-core system performs the bus reset is collected. In a specific embodiment, in addition to the reset operation of the multi-core system through the bus reset operation, the reset operation of the multi-core system can be performed through a power-on reset mode.
And S20, after judging that the reset of the target processor is successful according to the reset information, detecting whether all the rest processors of the multi-core system are reset successfully or not through the target processor.
Specifically, for step S20, whether the target processor (the first processor arranged according to the starting sequence) of the multi-core system is successfully reset is determined according to the reset information of the target processor obtained after the multi-core system executes the bus reset; if the target processor is judged to be successfully reset, the reset/state registers of other processors are read through the target processor which is successfully reset, so that whether all the remaining processors of the multi-core system are successfully reset is detected; if the target processor is judged to be in reset failure, returning to the step of executing bus reset, and continuing to execute bus reset on the multi-core system until the target processor is successfully reset, namely resetting the bus until the first core can normally run when the first core arranged according to the starting sequence fails to reset. Therefore, the problem that the prior multi-core system reset cannot flexibly control which core is BOOT first when the system is started for the first time is solved, and the flexibility of multi-core reset is further improved.
Optionally, in some embodiments, the detecting, by the target processor, whether all the remaining processors of the multi-core system are reset successfully in step S20 may specifically include:
And reading the corresponding register of each residual processor through the target processor, and judging whether each residual processor is reset successfully or not.
Specifically, the target processor after successful resetting reads the reset/state registers corresponding to the rest processors in the multi-core system, so as to judge whether the rest processors in the multi-core system are all reset successfully.
Optionally, in some embodiments, the target processor is a first processor in the multi-core system arranged in a boot order, the boot order being set according to the option bytes. For example, the start-up order is set according to the size of the option byte.
In a specific embodiment, as shown in fig. 2, fig. 2 provides a schematic structural diagram of a multi-core system reset system, where in fig. 2, a processor is illustrated as a CPU, and the CPU can reset itself through its POR or NRST or a software watchdog, etc., and also can reset itself through each other. The reset/status register is used to feedback the status of the system operation. The target processor reset success flag register indicates the running state of the target processor, and in this embodiment, the sequence of starting the CPU can be controlled by the option byte, so as to ensure that the first processor operates normally, and the purpose is to ensure that the first processor is available and can be used as a main core (main processor). When the multi-core system is powered on or the bus is reset, a certain processor cannot be normally and successfully reset due to the unstable factor of the RCC clock, whether all processors can be successfully operated is judged by setting a first processor reset success flag and a system state register, if all processors are not successfully reset, other processors can reset the fault core until the reset target processor is successfully reset or the preset times of failure resetting is reached, and the fault processor is identified.
S31, detecting that all the rest processors are reset successfully, and ending the multi-core reset.
Specifically, for step S31, when the reset/status registers of other processors are read by the target processor, after all the remaining processors of the multi-core system are detected to be reset successfully, the multi-core reset is indicated to be successful, and the multi-core reset of the multi-core system is ended.
S32, detecting that any processor is not reset successfully, and controlling a register corresponding to the processor which is not reset successfully to reset again through the target processor until all the rest processors of the multi-core system are reset successfully, and ending multi-core reset.
Specifically, for step S32, the reset/status registers of the other processors are read through the target processor that is successfully reset, so as to detect whether all the remaining processors of the multi-core system are successfully reset, and when the target processor detects that all the remaining processors of the multi-core system are not successfully reset, that is, any one processor is not successfully reset, the reset/status registers corresponding to the processors that are not successfully reset are controlled to be reset through the successfully reset processor to reset again until all the remaining processors of the multi-core system are successfully reset, so that the multi-core reset is ended. And carrying out reset detection and reset operation on the rest processors through the target processors which are successfully reset until all processors of the multi-core system are successfully reset, so that the condition that the processors are idle due to accidental failure of the available processors of the multi-core system can be avoided. Meanwhile, each processor of the multi-core system in the embodiment can read and control registers of other processors, so that bus errors are avoided.
Optionally, in some embodiments, resetting the register corresponding to the processor that is controlled by the target processor to be not reset successfully in step S32 may specifically further include:
If the number of times of executing the reset operation on the unsuccessfully reset processor is detected to be smaller than the first preset number of times, continuing to execute the reset operation on the unsuccessfully reset processor through the target processor until the reset is successful or the number of times of executing the reset operation is larger than or equal to the first preset number of times.
Specifically, when the number of times that the processor which is not successfully reset executes the reset operation is detected to be smaller than the first preset number of times, the reset operation is continuously performed on the processor which is not successfully reset through the target processor until the reset target processor is successfully reset, or the number of times that the reset operation is executed is larger than or equal to the first preset number of times, and the reset of the reset target processor is stopped. After resetting the unsuccessfully reset processor, reading a reset/state register corresponding to a reset target processor, judging whether all the rest processors of the multi-core system are reset successfully, and if yes, ending the multi-core reset; if not, repeating the steps until all processors are successfully reset or the processors which are failed in all reset are shielded.
Optionally, in some embodiments, resetting the register corresponding to the processor that is controlled by the target processor to be not reset successfully in step S32 may specifically further include:
If the number of times of executing the reset operation on the unsuccessfully reset processor is detected to be greater than or equal to the first preset number of times and is unsuccessfully reset, judging that the unsuccessfully reset processor is a fault processor, and shielding the fault processor.
Specifically, when the number of times that the processors which are not successfully reset execute the reset operation is detected to be greater than or equal to the first preset number of times, and the reset target processor is not successfully reset, the processors which are not successfully reset are judged to be fault processors, and all the fault processors are shielded in the multi-core reset.
Optionally, in some embodiments, after ending the multi-core reset, the method further comprises:
Polling and reading registers of the rest processors by any processor of the multi-core system;
when any processor reads that the rest processors have fault processors, the registers of the fault processors are controlled by any processor to carry out reset operation on the fault processors, and the running states of the fault processors are read.
Specifically, in this embodiment, after the multi-core reset is finished, the method specifically may further include: and when any processor of the multi-core system reads that any other processor fails, the fault processor is controlled to perform reset operation by any successfully reset processor, and the reset/state register of the fault processor is read in real time, so that the real-time running state of the fault processor is judged.
Optionally, in some embodiments, after the resetting operation of the fault processor by the registers of the fault processor controlled by the any processor, the method further comprises:
If the times of executing the reset operation on the fault processor are detected to be smaller than the second preset times, continuing to execute the reset operation on the fault processor until the reset is successful or the times of executing the reset operation are larger than or equal to the second preset times;
and if the number of times of executing the reset operation on the fault processor is greater than or equal to a second preset number of times and the fault processor is not successfully reset, shielding the fault processor.
Specifically, when the multi-core system operates normally, if any one of the processors that is successfully reset detects that the number of times that any fault processor executes the reset operation is smaller than the second preset number of times, the reset operation is continued on the fault processor until the fault processor is successfully reset, or the number of times of the reset operation is larger than or equal to the second preset number of times; and when the number of the reset operations on the fault processor is greater than or equal to the second preset number and the fault processor is not successfully reset, shielding the fault processor if the fault processor does not normally operate.
Referring to fig. 3, fig. 3 is a flowchart illustrating a second implementation of the multi-core system reset method according to an embodiment of the present application. The multi-core system reset method comprises the following steps:
s101, performing bus reset.
S102, judging whether the first core is successfully reset.
In this step, whether the first core (i.e. the target processor) is reset successfully is determined, if not, the step S101 is returned to; if yes, executing step S103;
s103, reading reset/state registers of other cores.
In this step, the reset state of the reset/state registers of the other cores than the first core is read.
S104, judging whether all the cores are successfully reset.
In this step, it is determined whether all of the cores are successfully reset, and if yes, step S1041 is executed; if the determination result is no, step S105 is performed.
S1041, ending the multi-core reset.
S105, judging whether reset operation of preset times is executed on the fault core or not;
in the step, it is determined whether a reset operation is performed for the fault core for a preset number of times, and if yes, step S1051 is performed; if the determination result is no, step S106 is executed.
S1051, shielding the core with the reset failure.
In this step, cores that fail to reset are masked.
S106, resetting operation is carried out on the fault core.
S107, reading a reset/state register of the fault core.
In this step, the reset state of the reset/state register of the faulty core is read, and after step S107 is executed, the process returns to step S104.
In a specific implementation process, after the system executes the bus reset, the system feeds back the state of the first reset core, if the first core fails to reset, the bus reset is performed again, if the first core is successfully reset, the first core reads the running states of other cores through the reset/state registers of the other cores, and when the running states indicate that all cores work normally, the multi-core reset is finished. If the fault core exists, resetting operation of the preset times is carried out on the fault core, the running state is read, and when the preset resetting times are executed, the fault core does not normally run, and the fault core is shielded.
Referring to fig. 4, fig. 4 is a flowchart illustrating a third implementation of the multi-core system reset method according to an embodiment of the present application. The multi-core system reset method comprises the following steps:
S201, reading the reset/status register.
S202, judging whether a fault core exists.
In the step, judging whether a fault core exists, if not, returning to the step S201; if yes, step S203 is executed.
S203, judging whether reset operation of the preset times is executed on the fault core.
In this step, it is determined whether a reset operation is performed on the failed core for a preset number of times, and if yes, step S2031 is performed; if the determination result is negative, step S2032 is executed.
S2031, the core that failed the reset is masked.
In this step, cores that fail to reset are masked.
S2032, a reset operation is performed on the failed core.
In this step, a reset operation is performed on the failed core, and after step S2032 is performed, the flow returns to step S201.
In a specific implementation process, when the multi-core system operates normally, each processor can read the reset/state registers of other processors in a polling way, the operation states of the other processors are fed back through the reset/state registers, when one core detects that any other processor cannot operate normally, the reset/state registers of the other processors are controlled to execute the reset operation on the target core, then whether the target processor operates normally is judged through the reset/state registers, if the target processor does not operate normally, the operation is continuously executed on the target processor until the target processor operates normally, or the target processor is considered to be faulty if the preset times of normal operation does not exist.
In addition, in the running process of the multi-core system, due to factors such as external interference and the like, a certain processor may fail and cannot generate reset, a system state register can be read in a polling mode, the fault processor is monitored in real time, and the fault processor is reset through other processors until the fault processor is successfully reset or the preset times are reached, and the processor is not successfully reset, so that the damage is determined.
As can be seen from the above, the multi-core system reset method provided by the embodiment of the present application includes: after the multi-core system executes bus reset, acquiring reset information of a target processor; after judging that the reset of the target processor is successful according to the reset information, detecting whether all the rest processors of the multi-core system are reset successfully or not through the target processor; if all the rest processors are detected to be successfully reset, ending the multi-core reset; if any processor is detected to be not reset successfully, the register corresponding to the processor which is not reset successfully is controlled to reset again through the target processor until all the rest processors of the multi-core system are reset successfully, and the multi-core reset is ended. Therefore, in the multi-core system resetting method provided by the embodiment of the application, the first processor (namely the target processor) arranged according to the starting sequence in the multi-core system is firstly subjected to resetting detection, so that the flexibility of the multi-core system is improved; then, carrying out reset detection and reset operation on the rest processors through the target processors which are successfully reset until all processors of the multi-core system are successfully reset, so that the condition that the processors are idle due to accidental failure of the available processors of the multi-core system can be avoided, and when any processor is abnormal, the reset of the processors is carried out in time to prevent the application from being failed, and the stability and the reliability of the multi-core system are further improved; in addition, each processor in the multi-core system can read and control registers of other processors, so that bus errors are avoided.
Correspondingly, the application also provides a multi-core system resetting device, referring to fig. 5, fig. 5 is a schematic structural diagram of the multi-core system resetting device provided by the application, and specifically may include an obtaining module 100, a detecting module 200 and a resetting module 300.
The acquiring module 100 is configured to acquire reset information of the target processor after the multi-core system performs bus reset.
Specifically, for the obtaining module 100, after the multi-core system performs the bus reset operation, all processors in the multi-core system are reset again, and then the reset information of the target processor after the multi-core system performs the bus reset is collected.
And the detection module 200 is configured to detect, by the target processor, whether all the remaining processors of the multi-core system are successfully reset after the target processor is successfully reset according to the reset information.
Optionally, in some embodiments, the detection module 200 may specifically include:
and the starting sequence unit is used for determining a target processor, wherein the target processor is the first processor in the multi-core system, and the first processor is arranged according to the starting sequence, and the starting sequence is set according to the option bytes.
And the reset detection unit is used for reading the registers corresponding to the residual processors through the target processor and judging whether the residual processors are reset successfully or not.
Specifically, for the detection module 200, whether the target processor (the processor with the first starting sequence) of the multi-core system is successfully reset is judged according to the reset information of the target processor obtained after the multi-core system executes bus reset; if the target processor is judged to be successfully reset, the reset/state registers of other processors are read through the target processor which is successfully reset, so that whether all the remaining processors of the multi-core system are successfully reset is detected; if the target processor is judged to be in reset failure, returning to the step of executing bus reset, and continuing to execute bus reset or power-on reset on the multi-core system until the target processor is successfully reset, namely resetting the bus until the first core can normally run when the first core is in reset failure.
The reset module 300 is configured to end multi-core reset if all the remaining processors are detected to be reset successfully; if any processor is detected to be not reset successfully, the register corresponding to the processor which is not reset successfully is controlled to reset again through the target processor until all the rest processors of the multi-core system are reset successfully, and the multi-core reset is ended.
Optionally, in some embodiments, the reset module 300 may specifically include:
the first reset unit is used for ending multi-core reset if all the rest processors are detected to be successfully reset;
And the second resetting unit is used for controlling the register corresponding to the processor which is not successfully reset to be reset through the target processor if any one processor is detected to be not successfully reset, until all the rest processors of the multi-core system are successfully reset, and ending the multi-core resetting.
Specifically, for the reset module 300, when the reset/status registers of other processors are read through the target processor, after all the rest processors of the multi-core system are detected to be reset successfully, the multi-core reset is indicated to be successful, and the multi-core reset of the multi-core system is finished; when the target processor detects that all the rest processors of the multi-core system are not reset successfully, namely that any processor is not reset successfully, the reset/state register corresponding to the processor which is not reset successfully is controlled to reset again by the processor which is reset successfully until all the rest processors of the multi-core system are reset successfully, and the multi-core reset is finished.
Optionally, the multi-core system reset device specifically may further include:
The polling module is used for polling and reading registers of the rest processors through any processor of the multi-core system; when any processor reads that the rest processors have fault processors, the registers of the fault processors are controlled by any processor to carry out reset operation on the fault processors, and the running states of the fault processors are read.
Specifically, for the polling module, the polling module is configured to poll and read the reset/status registers of other processors in the multi-core system through any processor in the multi-core system, determine whether the other processors have faults, and when any processor reads that any other processor has faults, control the fault processor to perform a reset operation through any successfully reset processor, and read the reset/status registers of the fault processor in real time, so as to determine the real-time running state of the fault processor.
In summary, in the multi-core system reset device provided by the embodiment of the present application, the obtaining module 100 obtains the reset information of the target processor after the multi-core system performs bus reset; after judging that the reset of the target processor is successful according to the reset information, the detection module 200 detects whether all the rest processors of the multi-core system are reset successfully through the target processor; the reset module 300 ends the multi-core reset after detecting that all the rest processors are reset successfully; if any processor is detected to be not reset successfully, the register corresponding to the processor which is not reset successfully is controlled to reset again through the target processor until all the rest processors of the multi-core system are reset successfully, and the multi-core reset is ended. Therefore, the resetting device of the multi-core system firstly carries out resetting detection on the first processor (namely the target processor) arranged according to the starting sequence in the multi-core system, so that the flexibility of the multi-core system is improved; then, carrying out reset detection and reset operation on the rest processors through the target processors which are successfully reset until all processors of the multi-core system are successfully reset, so that the condition that the processors are idle due to accidental failure of the available processors of the multi-core system can be avoided, and when any processor is abnormal, the reset of the processors is carried out in time to prevent the application from being failed, and the stability and the reliability of the multi-core system are further improved; in addition, each processor in the multi-core system can read and control registers of other processors, so that bus errors are avoided.
The embodiment of the application also provides a computer device, which can be a server, and the structure schematic diagram of the computer device is shown in fig. 6. The computer device includes a processor, a memory, a network interface, and a database connected by a system bus. Wherein the computer is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The database of the computer equipment is used for storing data such as a multi-core system reset method and the like. The network interface of the computer device is used for communicating with an external terminal through a network connection.
The computer program, when executed by a processor, implements a multi-core system reset method. The multi-core system resetting method comprises the following steps: firstly, after a multi-core system executes bus reset, acquiring reset information of a target processor; then after judging that the reset of the target processor is successful according to the reset information, detecting whether all the rest processors of the multi-core system are reset successfully or not through the target processor; if all the rest processors are detected to be successfully reset, ending the multi-core reset; if any processor is detected to be not reset successfully, the register corresponding to the processor which is not reset successfully is controlled to reset again through the target processor until all the rest processors of the multi-core system are reset successfully, and the multi-core reset is ended.
An embodiment of the present application further provides a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements a multi-core system reset method, including the steps of: firstly, after a multi-core system executes bus reset, acquiring reset information of a target processor; then after judging that the reset of the target processor is successful according to the reset information, detecting whether all the rest processors of the multi-core system are reset successfully or not through the target processor; if all the rest processors are detected to be successfully reset, ending the multi-core reset; if any processor is detected to be not reset successfully, the register corresponding to the processor which is not reset successfully is controlled to reset again through the target processor until all the rest processors of the multi-core system are reset successfully, and the multi-core reset is ended.
According to the executed multi-core system resetting method, the first processor (namely the target processor) arranged according to the starting sequence in the multi-core system is reset and detected, so that the flexibility of the multi-core system is improved; then, carrying out reset detection and reset operation on the rest processors through the target processors which are successfully reset until all processors of the multi-core system are successfully reset, so that the condition that the processors are idle due to accidental failure of the available processors of the multi-core system can be avoided, and when any processor is abnormal, the reset of the processors is carried out in time to prevent the application from being failed, and the stability and the reliability of the multi-core system are further improved; in addition, each processor in the multi-core system can read and control registers of other processors, so that bus errors are avoided.
It can be understood that the above scenario is merely an example, and does not constitute a limitation on the application scenario of the technical solution provided by the embodiment of the present application, and the technical solution of the present application may also be applied to other scenarios. For example, as one of ordinary skill in the art can know, with the evolution of the system architecture and the appearance of new service scenarios, the technical solution provided by the embodiment of the present application is also applicable to similar technical problems.
The foregoing embodiment numbers of the present application are merely for the purpose of description, and do not represent the advantages or disadvantages of the embodiments.
The steps in the method of the embodiment of the application can be sequentially adjusted, combined and deleted according to actual needs.
The units in the device of the embodiment of the application can be combined, divided and deleted according to actual needs.
In the present application, the same or similar term concept, technical solution and/or application scenario description will be generally described in detail only when first appearing and then repeatedly appearing, and for brevity, the description will not be repeated generally, and in understanding the present application technical solution and the like, reference may be made to the previous related detailed description thereof for the same or similar term concept, technical solution and/or application scenario description and the like which are not described in detail later.
In the present application, the descriptions of the embodiments are emphasized, and the details or descriptions of the other embodiments may be referred to.
The technical features of the technical scheme of the application can be arbitrarily combined, and all possible combinations of the technical features in the above embodiment are not described for the sake of brevity, however, as long as there is no contradiction between the combinations of the technical features, the application shall be considered as the scope of the description of the application.
From the above description of the embodiments, it will be clear to those skilled in the art that the above-described embodiment method may be implemented by means of software plus a necessary general hardware platform, but of course may also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (e.g. ROM/RAM, magnetic disk, optical disk) as above, comprising instructions for causing a terminal device (which may be a mobile phone, a computer, a server, a controlled terminal, or a network device, etc.) to perform the method of each embodiment of the present application.
In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions in accordance with embodiments of the present application are produced in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable devices. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line), or wireless (e.g., infrared, wireless, microwave, etc.). Computer readable storage media can be any available media that can be accessed by a computer or data storage devices, such as servers, data centers, etc., that contain an integration of one or more available media. Usable media may be magnetic media (e.g., floppy disks, storage disks, magnetic tape), optical media (e.g., DVD), or semiconductor media (e.g., solid state storage disk Solid STATE DISK (SSD)), etc.
The foregoing description is only of the preferred embodiments of the present application, and is not intended to limit the scope of the application, but rather is intended to cover any equivalents of the structures or equivalent processes disclosed herein or in the alternative, which may be employed directly or indirectly in other related arts.
Claims (8)
1. The multi-core system resetting method is characterized by comprising the following steps of:
after the multi-core system executes bus reset, acquiring reset information of a target processor;
After judging that the reset of the target processor is successful according to the reset information, detecting whether all the rest processors of the multi-core system are reset successfully or not through the target processor;
if all the rest processors are detected to be successfully reset, ending the multi-core reset;
If any processor is detected to be not reset successfully, resetting the register corresponding to the processor which is not reset successfully is controlled by the target processor until all the rest processors of the multi-core system are reset successfully, and ending multi-core reset;
After the multi-core reset is finished, any processor of the multi-core system polls and reads the registers of the rest processors, and when any processor reads that the rest processors have fault processors, the any processor controls the registers of the fault processors to reset the fault processors and reads the running states of the fault processors; if the times of executing the reset operation on the fault processor are detected to be smaller than the second preset times, continuing to execute the reset operation on the fault processor until the reset is successful or the times of executing the reset operation are larger than or equal to the second preset times; and if the number of times of executing the reset operation on the fault processor is greater than or equal to a second preset number of times and the fault processor is not successfully reset, shielding the fault processor.
2. The method for resetting a multi-core system as recited in claim 1, wherein the target processor is a first processor in the multi-core system arranged in a boot sequence, the boot sequence being set according to an option byte.
3. The method for resetting a multi-core system according to claim 1, wherein the controlling, by the target processor, resetting the register corresponding to the processor that has not been successfully reset comprises:
If the number of times of executing the reset operation on the unsuccessful reset processor is detected to be smaller than a first preset number of times, continuing to execute the reset operation on the unsuccessful reset processor through the target processor until the number of times of resetting success or executing the reset operation is larger than or equal to the first preset number of times.
4. The multi-core system reset method of claim 3, further comprising:
And if the times of executing the reset operation on the unsuccessfully reset processor is detected to be greater than or equal to the first preset times and is unsuccessfully reset, judging that the unsuccessfully reset processor is a fault processor.
5. The multi-core system reset method of claim 1, wherein the detecting, by the target processor, whether all of the remaining processors of the multi-core system have been reset successfully comprises:
And reading the corresponding register of each residual processor through the target processor, and judging whether each residual processor is reset successfully or not.
6. A multi-core system reset device, comprising:
the acquisition module is used for acquiring reset information of the target processor after the multi-core system executes bus reset;
the detection module is used for detecting whether all the rest processors of the multi-core system are successfully reset through the target processor after judging that the target processor is successfully reset according to the reset information;
the reset module is used for ending multi-core reset if all the rest processors are detected to be reset successfully; if any processor is detected to be not reset successfully, resetting the register corresponding to the processor which is not reset successfully is controlled by the target processor until all the rest processors of the multi-core system are reset successfully, and ending multi-core reset;
The reset module is also used for polling and reading the registers of the remaining processors through any processor of the multi-core system, and when any processor reads that the remaining processors have fault processors, the any processor controls the registers of the fault processors to reset the fault processors and reads the running states of the fault processors; if the times of executing the reset operation on the fault processor are detected to be smaller than the second preset times, continuing to execute the reset operation on the fault processor until the reset is successful or the times of executing the reset operation are larger than or equal to the second preset times; and if the number of times of executing the reset operation on the fault processor is greater than or equal to a second preset number of times and the fault processor is not successfully reset, shielding the fault processor.
7. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor implements the steps of the multi-core system reset method of any one of claims 1 to 5 when the computer program is executed.
8. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the multi-core system reset method of any one of claims 1 to 5.
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| CN115167651B (en) * | 2022-09-05 | 2022-11-25 | 北京紫光芯能科技有限公司 | Multi-core SOC reset load balancing circuit and system |
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