CN210038710U - Power supply switching circuit and server - Google Patents
Power supply switching circuit and server Download PDFInfo
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- CN210038710U CN210038710U CN201921337137.0U CN201921337137U CN210038710U CN 210038710 U CN210038710 U CN 210038710U CN 201921337137 U CN201921337137 U CN 201921337137U CN 210038710 U CN210038710 U CN 210038710U
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- 230000002093 peripheral effect Effects 0.000 claims description 4
- 238000000034 method Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000004590 computer program Methods 0.000 description 1
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- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
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Abstract
The utility model provides a power supply switching circuit and server, this circuit includes: the grid electrode of the first MOS tube is connected to the switching signal, and the source electrode of the first MOS tube is grounded; the first power supply is connected to the drain electrode of the first MOS transistor through a first resistor; the grid electrode of the second MOS tube is connected between the first resistor and the drain electrode of the first MOS tube, the drain electrode is connected to the first power supply through the second resistor, and the source electrode is grounded; the grid electrode of the third MOS tube is connected to the drain electrode of the first MOS tube and the grid electrode of the second MOS tube, and the source electrode of the third MOS tube is connected to the output end; the second power supply is connected to the drain electrode of the third MOS tube; the grid electrode of the fourth MOS tube is connected between the drain electrode of the second MOS tube and the second resistor, and the source electrode of the fourth MOS tube is connected to the output end; and the third power supply is connected to the drain electrode of the fourth MOS tube. Through using the utility model discloses a circuit can reduce platform integrated control ware power switching circuit design complexity, reduces product cost.
Description
Technical Field
The utility model relates to a computer field to more specifically relate to a power supply switching circuit and server.
Background
An LPC (low pin count bus) bus or an eSPI (enhanced serial peripheral interface) bus may be used for communication between a pci (platform integrated controller) south bridge chip of Intel and modules such as a BMC (baseboard management controller) and a TPM (trusted platform module). The two buses are multiplexed, using a common pin at the PCH terminal and a common power supply. However, the working voltage of the LPC bus is 3.3V and the working voltage of the eSPI bus is 1.8V, which requires that the power supply can be switched between 3.3V and 1.8V according to different bus working modes. At present, in the design of a server, a special chip is used for power supply switching, the cost is high, and the design of related circuits is complex.
The MOS transistor is a metal oxide semiconductor (semiconductor) field effect transistor, or is referred to as a metal-insulator semiconductor (insulator). The MOS tube is a voltage-controlled element, can be conducted as long as the voltage required by the voltage-controlled element is added, and is conducted like a triode in a saturation state, and the voltage drop of a conducting junction is minimum. This is often referred to classically as a switching action.
SUMMERY OF THE UTILITY MODEL
In view of this, an object of the embodiments of the present invention is to provide a power supply switching circuit, which can realize power switching between an eSPI bus and an LPC bus, and can reduce the complexity of the design of the power switching circuit of a platform integrated controller and reduce the product cost.
Based on the above object, an aspect of the embodiments of the present invention provides a power supply switching circuit, including:
the grid electrode of the first MOS tube is connected to the switching signal, and the source electrode of the first MOS tube is grounded;
the first power supply is connected to the drain electrode of the first MOS transistor through a first resistor;
the grid electrode of the second MOS tube is connected between the first resistor and the drain electrode of the first MOS tube, the drain electrode is connected to the first power supply through the second resistor, and the source electrode is grounded;
the grid electrode of the third MOS tube is connected to the drain electrode of the first MOS tube and the grid electrode of the second MOS tube, and the source electrode of the third MOS tube is connected to the output end;
the second power supply is connected to the drain electrode of the third MOS tube;
the grid electrode of the fourth MOS tube is connected between the drain electrode of the second MOS tube and the second resistor, and the source electrode of the fourth MOS tube is connected to the output end;
and the third power supply is connected to the drain electrode of the fourth MOS tube.
According to the utility model discloses an embodiment, switching signal is the signal source of output high level or low level.
According to the utility model discloses an embodiment, first MOS pipe is constructed and is made first MOS pipe source electrode and drain-source resistance switch on receiving under the high level state, makes first MOS pipe source electrode and drain-source resistance switch off receiving under the low level state.
According to an embodiment of the invention, the first power supply is a 12V power supply.
According to an embodiment of the present invention, the second power supply is a 1.8V power supply and the third power supply is a 3.3V power supply; or the second power supply is a 3.3V power supply and the third power supply is a 1.8V power supply.
According to an embodiment of the present invention, the 3.3V power supply is the voltage provided by the low pin count bus.
According to the utility model discloses an embodiment, the voltage that the 1.8V power provided for the enhancement mode serial peripheral interface bus.
According to an embodiment of the present invention, the output is connected to the platform integrated controller.
According to an embodiment of the present invention, the second, third and fourth mos transistors are configured to turn on the source and drain electrodes when the gate receives a high voltage state, and turn off the source and drain electrodes when the gate receives a low voltage state.
In another aspect of the embodiments of the present invention, there is also provided a server, including the apparatus of any one of the above.
The utility model discloses following beneficial technological effect has: the embodiment of the utility model provides a power supply switching circuit, through setting up first MOS pipe, first MOS pipe grid is connected to switching signal, source ground connection; the first power supply is connected to the drain electrode of the first MOS transistor through a first resistor; the grid electrode of the second MOS tube is connected between the first resistor and the drain electrode of the first MOS tube, the drain electrode is connected to the first power supply through the second resistor, and the source electrode is grounded; the grid electrode of the third MOS tube is connected to the drain electrode of the first MOS tube and the grid electrode of the second MOS tube, and the source electrode of the third MOS tube is connected to the output end; the second power supply is connected to the drain electrode of the third MOS tube; the grid electrode of the fourth MOS tube is connected between the drain electrode of the second MOS tube and the second resistor, and the source electrode of the fourth MOS tube is connected to the output end; the third power supply is connected to the drain electrode of the fourth MOS tube, so that the power supply switching of the eSPI bus and the LPC bus can be realized, the design complexity of a power supply switching circuit of the platform integrated controller can be reduced, and the product cost can be reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other embodiments can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic diagram of a power supply switching circuit according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the embodiments of the present invention are further described in detail below with reference to the accompanying drawings.
In view of the above, according to a first aspect of embodiments of the present invention, an embodiment of a power supply switching circuit is provided. Fig. 1 shows a schematic diagram of the circuit.
As shown in fig. 1, the circuit may include:
the grid electrode of the first MOS tube is connected to the switching signal, and the source electrode of the first MOS tube is grounded;
the first power supply is connected to the drain electrode of the first MOS transistor through a first resistor;
the grid electrode of the second MOS tube is connected between the first resistor and the drain electrode of the first MOS tube, the drain electrode is connected to the first power supply through the second resistor, and the source electrode is grounded;
the grid electrode of the third MOS tube is connected to the drain electrode of the first MOS tube and the grid electrode of the second MOS tube, and the source electrode of the third MOS tube is connected to the output end;
the second power supply is connected to the drain electrode of the third MOS tube;
the grid electrode of the fourth MOS tube is connected between the drain electrode of the second MOS tube and the second resistor, and the source electrode of the fourth MOS tube is connected to the output end;
and the third power supply is connected to the drain electrode of the fourth MOS tube.
The utility model provides a circuit does not use extra integrated circuit chip, only uses 4 MOS pipes and 2 resistance to realize the used 3.3V power supply of LPC and the used 1.8V power supply of eSPI and switches, can save the cost, simplifies circuit design.
Through the technical scheme, the power supply switching of the eSIP bus and the LPC bus can be realized, the design complexity of a power supply switching circuit of the platform integrated controller can be reduced, and the product cost is reduced.
In a preferred embodiment of the present invention, the switching signal is a signal source that outputs a high level or a low level. The switch signal can be triggered by BMC, CPLD or Jumper added, manually.
In a preferred embodiment of the present invention, the first MOS transistor is configured such that when the switching signal output is high, vgs (th) >0, the source and the drain of the first MOS transistor are turned on, and when the switching signal output is low, vgs (th) ≦ 0, the source and the drain of the first MOS transistor are turned off.
In a preferred embodiment of the present invention, the first power supply is a 12V power supply.
In a preferred embodiment of the present invention, the second power source is a 1.8V power source and the third power source is a 3.3V power source or the second power source is a 3.3V power source and the third power source is a 1.8V power source.
In a preferred embodiment of the present invention, the 3.3V power supply is the voltage provided by the low pin count bus, which is the existing power supply on the motherboard. An additional 3.3V power supply may be used to provide the voltage, but an additional external power supply is required.
In a preferred embodiment of the present invention, the 1.8V power supply is the voltage provided by the enhanced serial peripheral interface bus, which is the existing power supply on the motherboard. An additional 1.8V power supply can be used to provide the voltage, but an additional external power supply is required.
In a preferred embodiment of the present invention, the output is connected to the platform integrated controller.
In a preferred embodiment of the present invention, the second, third and fourth mos transistors are configured such that vgs (th) >0 when the gate is at a high voltage, the source and drain are on, and vgs (th) ≦ 0 when the gate is at a low voltage, the source and drain are off.
In view of the above object, according to a second aspect of the embodiments of the present invention, there is provided a server including the apparatus of any one of the above.
Examples
The utility model discloses a logic circuit is constituteed to 4 MOS pipes, uses 2 resistance realization circuit current-limiting, and 1 control signal through the input controls the break-make of a plurality of cascades MOS, makes the power supply source of PCH automatic switch-over between 3.3V and 1.8V. The LPC bus and the eSPI bus are multiplexed, a common pin is used at the PCH end, and a common power supply is used. However, the working voltage of the LPC bus is 3.3V and the working voltage of the eSPI bus is 1.8V, which requires that the power supply can be switched between 3.3V and 1.8V according to different bus working modes. In LPC mode, the PCH related pin must be powered by 3.3V level, and in eSPI mode, the PCH related pin must be powered by 1.8V. The level of the signal must be consistent with the power supply of the pin of the PCH, otherwise the board card is easily damaged, and the normal operation cannot be performed.
The specific design scheme is shown as a circuit in fig. 1:
12V _ Power, 3.3V _ Power and 1.8V _ Power are the existing Power supply on the mainboard, PCH _ Power is the Power supply of final input to PCH, the purpose of the utility model discloses circuit design is to be connected 3.3V _ Power or 1.8V _ Power to PCH _ Power, and the two are not connected simultaneously;
when the input control signal is in a high level, Vgs (th) >0, the MOS transistor Q1 is conducted, and after the conduction, a D pole (drain) is connected with an S pole (source) so that the voltage of the point A is low; meanwhile, the point A is the G pole (grid) of the MOS tube Q2 and Q3, when the voltage at the point A is low, Vgs (th) is less than or equal to 0, and the MOS tube Q2 and Q3 are both in a cut-off state. Then, the voltage at point B is influenced by the pull-up and is high level, meanwhile, point B is the G pole of the MOS transistor Q4, when the voltage at point B is high, vgs (th) is greater than 0, the MOS transistor Q4 is turned on, 3.3V _ Power is turned on with PCH _ Power, that is, the PCH is powered at this time by 3.3V;
when the input control signal is low level, vgs (th) is less than or equal to 0, MOS transistor Q1 is cut off, then the voltage at point a is affected by pull-up and is high level, at the same time point a is the G pole of MOS transistors Q2 and Q3, when the voltage at point a is high, vgs (th) is greater than 0, MOS transistors Q2 and Q3 are turned on, the D pole and S pole of Q2 are connected so that the voltage at point B is low, at the same time point B is the G pole of MOS transistor Q4, when the voltage at point B is low, vgs (th) is less than or equal to 0, MOS transistor Q4 is cut off, at this time 1.8V _ Power is turned on with PCH _ Power through Q3, i.e. PCH supplies 1.8V;
through the technical scheme, the power supply switching of the eSIP bus and the LPC bus can be realized, the design complexity of a power supply switching circuit of the platform integrated controller can be reduced, and the product cost is reduced.
It should be particularly noted that the embodiment of the system described above employs the embodiment of the method described above to specifically describe the working process of each module, and those skilled in the art can easily think that the modules are applied to other embodiments of the method described above.
Further, the above-described method steps and system elements or modules may also be implemented using a controller and a computer-readable storage medium for storing a computer program for causing the controller to implement the functions of the above-described steps or elements or modules.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
The above-described embodiments, particularly any "preferred" embodiments, are possible examples of implementations, and are presented merely for a clear understanding of the principles of the invention. Many variations and modifications may be made to the above-described embodiments without departing from the spirit and principles of the technology described herein. All such modifications are intended to be included within the scope of this disclosure and protected by the following claims.
Claims (10)
1. A power supply switching circuit, comprising:
the grid electrode of the first MOS tube is connected to a switching signal, and the source electrode of the first MOS tube is grounded;
the first power supply is connected to the drain electrode of the first MOS transistor through a first resistor;
the grid electrode of the second MOS tube is connected between the first resistor and the drain electrode of the first MOS tube, the drain electrode is connected to the first power supply through a second resistor, and the source electrode of the second MOS tube is grounded;
a grid electrode of the third MOS tube is connected to a drain electrode of the first MOS tube and a grid electrode of the second MOS tube, and a source electrode of the third MOS tube is connected to an output end;
the second power supply is connected to the drain electrode of the third MOS tube;
a grid electrode of the fourth MOS tube is connected between a drain electrode of the second MOS tube and the second resistor, and a source electrode of the fourth MOS tube is connected to an output end;
and the third power supply is connected to the drain electrode of the fourth MOS tube.
2. The circuit of claim 1, wherein the switching signal is a signal source outputting a high level or a low level.
3. The circuit of claim 2, wherein the first MOS transistor is configured to turn on the source and drain of the first MOS transistor when receiving a high state and turn off the source and drain of the first MOS transistor when receiving a low state.
4. The circuit of claim 3, wherein the first power supply is a 12V power supply.
5. The circuit of claim 1, wherein the second power supply is a 1.8V power supply and the third power supply is a 3.3V power supply; or the second power supply is a 3.3V power supply and the third power supply is a 1.8V power supply.
6. The circuit of claim 5, wherein the 3.3V power supply is a voltage provided by a low pin count bus.
7. The circuit of claim 5, wherein the 1.8V power supply is a voltage provided by an enhanced serial peripheral interface bus.
8. The circuit of claim 1, wherein the output is connected to a platform integrated controller.
9. The circuit of claim 1, wherein the second, third, and fourth mos transistors are configured to turn on the source and drain when the gate receives a high voltage condition and to turn off the source and drain when the gate receives a low voltage condition.
10. A server, characterized in that it comprises a circuit according to any one of claims 1-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921337137.0U CN210038710U (en) | 2019-08-16 | 2019-08-16 | Power supply switching circuit and server |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921337137.0U CN210038710U (en) | 2019-08-16 | 2019-08-16 | Power supply switching circuit and server |
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| Publication Number | Publication Date |
|---|---|
| CN210038710U true CN210038710U (en) | 2020-02-07 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201921337137.0U Expired - Fee Related CN210038710U (en) | 2019-08-16 | 2019-08-16 | Power supply switching circuit and server |
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| CN (1) | CN210038710U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113360449A (en) * | 2021-04-29 | 2021-09-07 | 山东英信计算机技术有限公司 | Server protection circuit and server |
| CN113448420A (en) * | 2021-05-23 | 2021-09-28 | 山东英信计算机技术有限公司 | Server power supply switching circuit and server |
-
2019
- 2019-08-16 CN CN201921337137.0U patent/CN210038710U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113360449A (en) * | 2021-04-29 | 2021-09-07 | 山东英信计算机技术有限公司 | Server protection circuit and server |
| CN113448420A (en) * | 2021-05-23 | 2021-09-28 | 山东英信计算机技术有限公司 | Server power supply switching circuit and server |
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| GR01 | Patent grant | ||
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Granted publication date: 20200207 Termination date: 20200816 |