CN110618954B - Switch control circuit and electronic device using same - Google Patents
Switch control circuit and electronic device using same Download PDFInfo
- Publication number
- CN110618954B CN110618954B CN201810639206.7A CN201810639206A CN110618954B CN 110618954 B CN110618954 B CN 110618954B CN 201810639206 A CN201810639206 A CN 201810639206A CN 110618954 B CN110618954 B CN 110618954B
- Authority
- CN
- China
- Prior art keywords
- switch
- communication chip
- electronic switch
- electronic
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Logic Circuits (AREA)
- Electronic Switches (AREA)
Abstract
A switch control circuit is connected between a first communication chip and a second communication chip in an electronic device and comprises a first switch unit and a second switch unit, wherein the first switch unit is connected between the first communication chip and the second communication chip and is used for controlling the communication connection between the first communication chip and the second communication chip; the second switch unit is connected between the first communication chip and the first switch unit, the second switch unit is used for receiving the power good signal output by the first communication chip and outputting a corresponding switch signal according to the received power good signal, and the switch unit controls the first switch unit to be switched on or switched off. The invention also provides an electronic device applying the switch control circuit. Therefore, when the first communication chip does not need to be connected with the second communication chip, the connection between the first communication chip and the second communication chip can be disconnected, and the power consumption of the system can be reduced.
Description
Technical Field
The invention relates to a switch control circuit and an electronic device using the same.
Background
Generally, in a server or a computer system, a Platform Controller Hub (PCH) communicates with a memory chip through an I2C (Inter-Integrated Circuit) bus.
Generally, when the platform hub controller does not need to communicate with the memory chip, the memory chip still transmits data to the platform hub controller, which is inconvenient for resource management of the system and also generates unnecessary power consumption waste.
Disclosure of Invention
Accordingly, there is a need for a switch control circuit and an electronic device using the same.
A switch control circuit connected between a first communication chip and a second communication chip in an electronic device, the switch control circuit comprising:
the first switch unit is connected between the first communication chip and the second communication chip and used for controlling communication connection between the first communication chip and the second communication chip; and
the second switch unit is connected between the first communication chip and the first switch unit, is used for receiving the power good signal output by the first communication chip and outputting a corresponding switch signal according to the received power good signal, and controls the first switch unit to be switched on or switched off;
in a first state, the first communication chip outputs a power good signal with a first level to control the second switch unit to output a switch signal with the first level, and the switch signal with the first level controls the first switch unit to be switched off to disconnect the communication connection between the first communication chip and the second communication chip;
in a second state, the first communication chip outputs a power good signal with a second level to control the second switch unit to output a switch signal with the second level, and the switch signal with the second level controls the first switch unit to be conducted to realize communication connection between the first communication chip and the second communication chip.
Further, the first level is a low level, and the second level is a high level.
Further, the first switch unit includes a first electronic switch, a second electronic switch, and first to fifth resistors, a first end of the first electronic switch is connected to a first end of the second electronic switch, a second end of the first electronic switch is connected to the data bus pin of the first communication chip and is connected to the first power supply through the first resistor, and a third end of the first electronic switch is connected to the data bus pin of the second communication chip and is connected to the second power supply through the second resistor; the second end of the second electronic switch is connected to the clock bus pin of the first communication chip and is connected to the first power supply through the third resistor, the third end of the second electronic switch is connected to the clock bus pin of the second communication chip and is connected to the second power supply through the fourth resistor, and a first node between the first end of the first electronic switch and the first end of the second electronic switch is connected to the third power supply through the fifth resistor.
Furthermore, the second switch unit includes a third electronic switch, a fourth electronic switch, a sixth resistor and a seventh resistor, a first end of the third electronic switch is connected to the power good signal pin of the first communication chip through the sixth resistor, a second end of the third electronic switch is connected to a second node between the first power supply and the first end of the fourth electronic switch and is connected to the first power supply through the seventh resistor, and a third end of the third electronic switch is grounded; a second terminal of the fourth electronic switch is connected to the second node.
Furthermore, the first electronic switch to the fourth electronic switch are all N-channel enhancement type field effect transistors.
Furthermore, the first terminals of the first electronic switch to the fourth electronic switch correspond to the gates of the N-channel enhancement type field effect transistors, the second terminals of the first electronic switch to the fourth electronic switch correspond to the drains of the N-channel enhancement type field effect transistors, and the third terminals of the first electronic switch to the fourth electronic switch correspond to the sources of the N-channel enhancement type field effect transistors.
Further, the first power supply outputs 3.3V dc voltage in both the first state and the second state, the second power supply outputs 3.3V dc voltage in the second state, and the third power supply outputs 12V dc voltage in the second state.
An electronic device comprises a first communication chip, a second communication chip and a switch control circuit, wherein the switch control circuit is connected between the first communication chip and the second communication chip in the electronic device, and the switch control circuit comprises:
the first switch unit is connected between the first communication chip and the second communication chip and used for controlling communication connection between the first communication chip and the second communication chip; and
the second switch unit is connected between the first communication chip and the first switch unit, is used for receiving the power good signal output by the first communication chip and outputting a corresponding switch signal according to the received power good signal, and controls the first switch unit to be switched on or switched off;
in a first state, the first communication chip outputs a power good signal with a first level to control the second switch unit to output a switch signal with the first level, and the switch signal with the first level controls the first switch unit to be switched off to disconnect the communication connection between the first communication chip and the second communication chip;
in a second state, the first communication chip outputs a power good signal with a second level to control the second switch unit to output a switch signal with the second level, and the switch signal with the second level controls the first switch unit to be conducted to realize communication connection between the first communication chip and the second communication chip.
Further, the first switch unit includes a first electronic switch, a second electronic switch, and first to fourth resistors, a first end of the first electronic switch is connected to a first end of the second electronic switch, a second end of the first electronic switch is connected to the data bus pin of the first communication chip and is connected to the first power supply through the first resistor, and a third end of the first electronic switch is connected to the data bus pin of the second communication chip and is connected to the second power supply through the second resistor; the second end of the second electronic switch is connected to the clock bus pin of the first communication chip and is connected to the first power supply through the third resistor, the third end of the second electronic switch is connected to the clock bus pin of the second communication chip and is connected to the second power supply through the fourth resistor, and a first node between the first end of the first electronic switch and the first end of the second electronic switch is connected to the third power supply through the fifth resistor.
Furthermore, the second switch unit includes a third electronic switch, a fourth electronic switch, a sixth resistor and a seventh resistor, a first end of the third electronic switch is connected to the power good signal pin of the first communication chip through the sixth resistor, a second end of the third electronic switch is connected to a first node between the first power supply and the first end of the fourth electronic switch and is connected to the first power supply through the seventh resistor, and a third end of the third electronic switch is grounded; a second end of the fourth electronic switch is connected to the second node; the first level is a low level and the second level is a high level.
In the switch control circuit and the electronic device using the switch control circuit, the first communication chip outputs a power good signal to the second switch unit to control the on or off of the first switch unit, so as to control the communication state between the first communication chip and the second communication chip. Therefore, under the condition that the first communication chip does not need to transmit data with the second communication chip, the connection between the first communication chip and the second communication chip is disconnected, so that the electronic device is more stable, and the power consumption is reduced.
Drawings
FIG. 1 is a block diagram of a preferred embodiment of an electronic device.
FIG. 2 is another block diagram of the preferred embodiment of the electronic device.
FIG. 3 is a circuit diagram of a preferred embodiment of an electronic device.
Description of the main elements
| Electronic device with a |
100 |
| |
10 |
| |
12 |
| |
14 |
| |
20 |
| |
30 |
| Resistance (RC) | R1-R7 |
| Electronic switch | Q1-Q4 |
| Power supply | V1-V3 |
| Node point | P1、P2 |
The following detailed description will further illustrate the invention in conjunction with the above-described figures.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention.
In order to make the objects, technical solutions and advantages of the present invention more clearly apparent, the following will describe and explain in further detail the switch control circuit and the electronic device using the switch control circuit in the present invention with reference to the accompanying drawings and embodiments.
Referring to fig. 1 and fig. 2, an electronic device 100 includes a switch control circuit 10, a first communication chip 20 and a second communication chip 30. The switch control circuit 10 is connected between the first communication chip 20 and the second communication chip 30 to control the communication connection between the first communication chip 20 and the second communication chip. In a preferred embodiment, the electronic device 100 is a server, the first communication chip 20 is a Platform Controller Hub (PCH), and the second communication chip 30 is a memory chip.
The switch control circuit 10 includes a first switch unit 12 and a second switch unit 14.
The first switch unit 12 is connected between the first communication chip 20 and the second communication chip 30, and the first switch unit 12 is used for controlling the communication connection between the first communication chip 20 and the second communication chip 30.
The second switch unit 14 is connected between the first communication chip 20 and the first switch unit 12, the second switch unit 14 is configured to receive a power good signal output by the first communication chip 20, and output a corresponding switch signal according to the received power good signal, where the switch signal is used to control on or off of the first switch unit 12.
In a first state (e.g., S5 state of the computer motherboard), the first communication chip 20 outputs a power good signal with a first level to control the second switch unit 14 to output a switch signal with the first level, and the switch signal with the first level controls the first switch unit 12 to be turned off to disconnect the communication connection between the first communication chip 20 and the second communication chip 30.
In a second state (e.g., S0 state of the computer motherboard), the first communication chip 20 outputs a power good signal with a second level to control the second switch unit 14 to output a switch signal with the second level, and the switch signal with the second level controls the first switch unit 12 to be turned on, so as to implement the communication connection between the first communication chip 20 and the second communication chip 30.
The first level is a low level state, and the second level is a high level state.
In this way, when the electronic device 100 is in the S5 state, that is, when the first communication chip 20 does not need to communicate with the second communication chip 30, the first communication chip 20 outputs a low-level power good signal to control the first switch unit 12 to output a low-level switch signal, and at this time, the second switch unit 14 is in the off state to disconnect the communication connection between the first communication chip 20 and the second communication chip 30, so that power consumption is saved.
Referring to fig. 3, in a preferred embodiment, the first communication chip 20 may include a data bus pin SMBDATA _1, a clock bus pin SMBCLK _1, and a power good signal pin PWRGD, and the second communication chip 30 may include a data bus pin SMBDATA _2 and a clock bus pin SMBCLK _2.
The first switch unit 12 may further include two electronic switches Q1 and Q2 and resistors R1 to R4 and R7.
A first end of the electronic switch Q1 is connected to a first end of the electronic switch Q2, and a second end of the electronic switch Q1 is connected to a data bus pin SMBDATA _1 of the first communication chip 20, and is connected to a power supply V1 through the resistor R1. The third end of the electronic switch Q1 is connected to the data bus pin SMBDATA _2 of the second communication chip 30, and is connected to a power supply V2 through the resistor R2. The second terminal of the electronic switch Q2 is further connected to a clock bus pin SMBCLK _1 of the first communication chip 20, and is connected to the power supply V1 through the resistor R3. The third terminal of the electronic switch Q2 is connected to the clock bus pin SMBCLK _2 of the second communication chip 30, and is connected to the power supply V2 through the resistor R4. A node P2 between the first terminal of the electronic switch Q1 and the first terminal of the electronic switch Q2 is connected to a power source V3 through the resistor R7.
The second switch unit 14 may further include two electronic switches Q3 and Q4 and resistors R5 to R6.
A first end of the electronic switch Q3 is connected to the power good signal pin PWRGD of the first communication chip 20 through the resistor R5 to receive the power good signal output by the first communication chip 20. The second terminal of the electronic switch Q3 is connected to a node P1 between the power supply V1 and the first terminal of the electronic switch Q4, and is connected to the power supply V1 through the resistor R6, and the third terminal of the electronic switch Q3 is grounded. A second terminal of the electronic switch Q4 is connected to the node P2.
In a preferred embodiment, the electronic switches Q1-Q4 are all N-channel enhancement mode fets. The first end, the second end and the third end of the electronic switches Q1-Q4 respectively correspond to the grid electrode, the drain electrode and the source electrode of the N-channel enhancement type field effect transistor.
Further, the power supply V1 can output a dc voltage of 3.3V in both the S5 state and the S0 state. The power supply V2 can output 3.3V direct current voltage in the S0 state, and the power supply V3 can output 12V direct current voltage in the S0 state.
The operation of the electronic device 100 will be described as follows:
when the electronic device 100 is in the S5 state, i.e., when no communication is required between the first communication chip 20 and the second communication chip 30. The power good signal pin PWRGD of the first communication chip 20 outputs a low-level power good signal to the first terminal of the electronic switch Q3 to control the electronic switch Q3 to be turned off. At this time, the electronic switch Q4 is controlled to be turned on by a 3.3V voltage signal output by the power supply V1, and the first terminals of the electronic switches Q1 and Q2 are both pulled down to a low level. In this way, the electronic switches Q1 and Q2 are both in the off state to disconnect the communication connection between the first communication chip 20 and the second communication chip 30.
When the electronic device 100 is in the S0 state, i.e. when communication is required between the first communication chip 20 and the second communication chip 30. The power good signal pin PWRGD of the first communication chip 20 outputs a high-level power good signal to the first terminal of the electronic switch Q3 to control the electronic switch Q3 to be turned on. At this time, the first terminal of the electronic switch Q4 is pulled down to a low level, and the electronic switch Q4 is in an off state. Thus, the 12V voltage signal outputted by the power source V3 can control the electronic switches Q1 and Q2 to be in the conducting state. In this way, normal communication between the first communication chip 20 and the second communication chip 30 is realized.
In the switch control circuit 10 and the electronic device 100 using the switch control circuit 10, the first communication chip 20 outputs a power good signal to the first switch unit 12 to control the on/off of the second switch unit 14, so as to control the communication state between the first communication chip 20 and the second communication chip 30. In this way, the first communication chip 20 and the second communication chip 30 can be disconnected without the first communication chip 20 transmitting materials with the second communication chip 30, so that the electronic device is more stable and the power consumption is reduced.
Finally, it should be noted that the above embodiments are only used for illustrating the technical solutions of the present invention and not for limiting, and although the present invention is described in detail with reference to the preferred embodiments.
It will be understood by those skilled in the art that various modifications and equivalent arrangements can be made without departing from the spirit and scope of the present invention. Moreover, based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without any creative effort will fall within the protection scope of the present invention.
Claims (10)
1. A switch control circuit connected between a first communication chip and a second communication chip in an electronic device, the switch control circuit comprising:
the first switch unit is connected between the first communication chip and the second communication chip and is used for controlling the communication connection between the first communication chip and the second communication chip; and
the second switch unit is connected between the first communication chip and the first switch unit, and is used for receiving the power good signal output by the first communication chip and outputting a corresponding switch signal according to the received power good signal, wherein the switch signal controls the on or off of the first switch unit;
in a first state, the first communication chip outputs a power good signal with a first level to control the second switch unit to output a switch signal with the first level, and the switch signal with the first level controls the first switch unit to be switched off to disconnect the communication connection between the first communication chip and the second communication chip;
in a second state, the first communication chip outputs a power good signal with a second level to control the second switch unit to output a switch signal with the second level, and the switch signal with the second level controls the first switch unit to be conducted to realize communication connection between the first communication chip and the second communication chip;
the first switch unit comprises a first electronic switch and a second electronic switch, the second switch unit comprises a third electronic switch and a fourth electronic switch, a first end of the first electronic switch is connected to a first end of the second electronic switch, a second end of the first electronic switch is connected to a data bus pin of the first communication chip and connected to a first power supply, and a third end of the first electronic switch is connected to a data bus pin of the second communication chip and connected to a second power supply; the second end of the second electronic switch is connected to the clock bus pin of the first communication chip and connected to the first power supply, the third end of the second electronic switch is connected to the clock bus pin of the second communication chip and connected to the second power supply, a first node between the first end of the first electronic switch and the first end of the second electronic switch is connected to the third power supply, and the first node receives the switching signal.
2. The switch control circuit of claim 1, wherein the first level is a low level and the second level is a high level.
3. The switch control circuit according to claim 2, wherein the first switching unit further includes first to fifth resistors, the second terminal of the first electronic switch is further connected to the first power supply through the first resistor, and the third terminal of the first electronic switch is further connected to the second power supply through the second resistor; the second end of the second electronic switch is further connected to the first power supply through the third resistor, the third end of the second electronic switch is further connected to the second power supply through the fourth resistor, and a first node between the first end of the first electronic switch and the first end of the second electronic switch is further connected to the third power supply through the fifth resistor.
4. The switch control circuit according to claim 3, wherein the second switch unit comprises a third electronic switch, a fourth electronic switch, a sixth resistor and a seventh resistor, a first terminal of the third electronic switch is connected to the power good signal pin of the first communication chip through the sixth resistor, a second terminal of the third electronic switch is connected to a second node between the first power supply and the first terminal of the fourth electronic switch and is connected to the first power supply through the seventh resistor, and a third terminal of the third electronic switch is grounded; a second terminal of the fourth electronic switch is connected to the second node.
5. The switch-control circuit of claim 4, wherein the first electronic switch through the fourth electronic switch are N-channel enhancement mode field effect transistors.
6. The switch control circuit of claim 5, wherein first terminals of the first through fourth electronic switches each correspond to a gate of an N-channel enhancement mode FET, second terminals of the first through fourth electronic switches each correspond to a drain of an N-channel enhancement mode FET, and third terminals of the first through fourth electronic switches each correspond to a source of an N-channel enhancement mode FET.
7. The switch control circuit of claim 6, wherein the first power supply outputs a 3.3V DC voltage in both the first state and the second state, the second power supply outputs a 3.3V DC voltage in the second state, and the third power supply outputs a 12V DC voltage in the second state.
8. An electronic device, includes first communication chip, second communication chip and switch control circuit, switch control circuit connects between first communication chip and second communication chip in electronic device, its characterized in that, switch control circuit includes:
the first switch unit is connected between the first communication chip and the second communication chip and used for controlling communication connection between the first communication chip and the second communication chip; and
the second switch unit is connected between the first communication chip and the first switch unit, and is used for receiving the power good signal output by the first communication chip and outputting a corresponding switch signal according to the received power good signal, wherein the switch signal controls the on or off of the first switch unit;
in a first state, the first communication chip outputs a power good signal with a first level to control the second switch unit to output a switch signal with the first level, and the switch signal with the first level controls the first switch unit to be switched off to disconnect the communication connection between the first communication chip and the second communication chip;
in a second state, the first communication chip outputs a power good signal with a second level to control the second switch unit to output a switch signal with the second level, and the switch signal with the second level controls the first switch unit to be conducted to realize communication connection between the first communication chip and the second communication chip;
the first switch unit comprises a first electronic switch and a second electronic switch, the second switch unit comprises a third electronic switch and a fourth electronic switch, the first end of the first electronic switch is connected to the first end of the second electronic switch, the second end of the first electronic switch is connected to the data bus pin of the first communication chip and is connected to a first power supply, and the third end of the first electronic switch is connected to the data bus pin of the second communication chip and is connected to a second power supply; the second end of the second electronic switch is connected to the clock bus pin of the first communication chip and connected to the first power supply, the third end of the second electronic switch is connected to the clock bus pin of the second communication chip and connected to the second power supply, a first node between the first end of the first electronic switch and the first end of the second electronic switch is connected to the third power supply, and the first node receives the switching signal.
9. The electronic device according to claim 8, wherein the first switch unit further comprises first to fifth resistors, the second terminal of the first electronic switch is further connected to the first power supply through the first resistor, and the third terminal of the first electronic switch is further connected to the second power supply through the second resistor; the second end of the second electronic switch is further connected to the first power supply through the third resistor, the third end of the second electronic switch is further connected to the second power supply through the fourth resistor, and a first node between the first end of the first electronic switch and the first end of the second electronic switch is further connected to the third power supply through the fifth resistor.
10. The electronic device according to claim 9, wherein the second switch unit includes a third electronic switch, a fourth electronic switch, a sixth resistor, and a seventh resistor, a first terminal of the third electronic switch is connected to the power good signal pin of the first communication chip through the sixth resistor, a second terminal of the third electronic switch is connected to a second node between the first power supply and the first terminal of the fourth electronic switch and is connected to the first power supply through the seventh resistor, and a third terminal of the third electronic switch is grounded; a second end of the fourth electronic switch is connected to the second node; the first level is a low level and the second level is a high level.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810639206.7A CN110618954B (en) | 2018-06-20 | 2018-06-20 | Switch control circuit and electronic device using same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810639206.7A CN110618954B (en) | 2018-06-20 | 2018-06-20 | Switch control circuit and electronic device using same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110618954A CN110618954A (en) | 2019-12-27 |
| CN110618954B true CN110618954B (en) | 2022-11-18 |
Family
ID=68920764
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810639206.7A Active CN110618954B (en) | 2018-06-20 | 2018-06-20 | Switch control circuit and electronic device using same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110618954B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9419618B1 (en) * | 2015-05-28 | 2016-08-16 | Hong Fu Jin Precision Industry (Shenzhen) Co., Ltd. | Interface circuit and electronic system using the same |
| CN206270872U (en) * | 2016-10-13 | 2017-06-20 | 潍坊歌尔电子有限公司 | A kind of circuit and electronic equipment of control I2C communications |
| US10009029B1 (en) * | 2017-03-22 | 2018-06-26 | Hong Fu Jin Precision Industry (Wuhan) Co., Ltd. | Interface control circuit to match voltage levels between USB devices upon connection |
-
2018
- 2018-06-20 CN CN201810639206.7A patent/CN110618954B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9419618B1 (en) * | 2015-05-28 | 2016-08-16 | Hong Fu Jin Precision Industry (Shenzhen) Co., Ltd. | Interface circuit and electronic system using the same |
| CN206270872U (en) * | 2016-10-13 | 2017-06-20 | 潍坊歌尔电子有限公司 | A kind of circuit and electronic equipment of control I2C communications |
| US10009029B1 (en) * | 2017-03-22 | 2018-06-26 | Hong Fu Jin Precision Industry (Wuhan) Co., Ltd. | Interface control circuit to match voltage levels between USB devices upon connection |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110618954A (en) | 2019-12-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20090300375A1 (en) | Power supply control circuit | |
| US7286005B2 (en) | Supply voltage switching circuit | |
| US8201003B2 (en) | Circuit for preventing computer power down sequence failure | |
| US20140354258A1 (en) | Supply voltage circuit | |
| US10224721B2 (en) | Switch control circuit and electronic device using the same | |
| US11128121B2 (en) | Protection circuit for decoupling a low voltage circuitry from a high voltage circuitry | |
| TWI585567B (en) | Voltage adjust apparatus for electronic device | |
| CN210038710U (en) | Power supply switching circuit and server | |
| CN110618954B (en) | Switch control circuit and electronic device using same | |
| CN110096382B (en) | Mainboard and electronic device applying same | |
| US11128126B2 (en) | Internal voltage-canceling circuit and USB device using the same | |
| US5831453A (en) | Method and apparatus for low power data transmission | |
| CN112578890B (en) | Server device capable of remotely controlling node power supply | |
| US5446320A (en) | Circuit for clamping power output to ground while the computer is deactivated | |
| JP2000307413A (en) | Current converting circuit and communication network | |
| US10181684B1 (en) | Power connector | |
| CN111984103B (en) | Power supply control circuit and electronic device applying same | |
| JPH11353066A (en) | Output buffer | |
| CN109871111B (en) | Display and electronic device using same | |
| CN110120702B (en) | Power supply control circuit | |
| CN112148101A (en) | Power supply protection circuit and mainboard applying same | |
| CN215646340U (en) | Power-off protection circuit and electronic equipment | |
| CN218006532U (en) | Circuit for determining master-slave device connection | |
| CN113326157B (en) | Circuit and server for upgrading FPGA (field programmable Gate array) firmware | |
| CN114817112B (en) | Slave machine equipment and master-slave machine communication system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |