CN109871111B - Display and electronic device using same - Google Patents
Display and electronic device using same Download PDFInfo
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- CN109871111B CN109871111B CN201711271200.0A CN201711271200A CN109871111B CN 109871111 B CN109871111 B CN 109871111B CN 201711271200 A CN201711271200 A CN 201711271200A CN 109871111 B CN109871111 B CN 109871111B
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Abstract
A display is connected with a mainboard to establish communication connection and comprises a first interface and a display unit. The mainboard comprises a second interface, the second interface is electrically connected with the first interface through a cable, and a leakage protection circuit is arranged between the first interface and the display unit so as to detect whether the cable between the first interface and the second interface meets the VESA standard. The invention also provides an electronic device applying the display. Therefore, the display and the mainboard can not leak electricity, the normal power supply time sequence is ensured, and the risk that the mainboard can not return to the operating system from shutdown or sleep is avoided.
Description
Technical Field
The invention relates to a display and an electronic device using the same.
Background
The main board and the Display are connected through a Display Port (DP) cable, however, when the DP cable does not conform to the Video Electronics Standards Association (VESA) standard, a leakage current will occur between the Display and the main board, which may interfere with a normal power timing and may not return to the operating system after waking up from a power-off or sleep.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a display and an electronic device using the same.
A display comprises a first interface and a display unit, wherein the first interface is connected with a second interface of a mainboard through a cable, the first interface comprises a first idle pin, the second interface comprises a second idle pin connected with a first power supply, the display further comprises a leakage protection circuit, and the leakage protection circuit comprises:
the power supply control chip is used for receiving a control signal and switching on or off the connection between the first idle pin and the second power supply according to the control signal;
the switch unit is used for receiving a switch signal output by a common end point between the first idle pin and the power control chip and outputting a corresponding trigger signal according to the switch signal; and
the processing chip is used for outputting a control signal with a first level within preset time, receiving the trigger signal and judging whether to switch the level state of the control signal after the preset time according to the trigger signal;
when the cable does not accord with the VESA standard, the first idle pin is electrically connected with the second idle pin, the processing chip outputs the control signal with the first level within a preset time to control the disconnection between the first idle pin and the second power supply, the common terminal outputs a first switch signal to control the switch unit to output a first trigger signal, and the processing chip continuously outputs the control signal with the first level after the preset time according to the first trigger signal to disconnect the first idle pin and the second power supply.
Further, when the cable meets the VESA standard, the first idle pin is disconnected from the second idle pin, the processing chip outputs a control signal having a first level within a preset time to control disconnection between the first idle pin and the second power supply, the common terminal outputs a second switch signal to control the switch unit to output a second trigger signal, and the processing chip switches the control signal from the first level to the second level after the preset time according to the second trigger signal to turn on the connection between the first idle pin and the second power supply.
Further, when the processing chip receives the first trigger signal, the processing chip outputs an alarm signal to the display unit to control the display unit to output alarm information.
Furthermore, the switch unit comprises an electronic switch, a first resistor and a second resistor, wherein a first end of the electronic switch is connected to the first idle pin of the first interface through the first resistor, a second end of the electronic switch is grounded, a third end of the electronic switch is connected to the second power supply through the second resistor, and the third end of the electronic switch is also connected to the processing chip.
Furthermore, the power control chip comprises a power output pin, a power input pin, a ground pin and an enable pin, the power output pin of the power control chip is connected to the first idle pin of the first interface, the power input pin of the power control chip is connected to the second power supply through the first inductor, the power input pin of the power control chip is grounded through the first capacitor, and the enable pin of the power control chip is connected to the processing chip.
Furthermore, the processing chip comprises a signal output pin, a detection pin, a control pin and a signal input pin, the signal output pin of the processing chip is connected with the enable pin of the power control chip, the detection pin and the control pin of the processing chip are both connected to the display unit, and the signal input pin of the processing chip is connected to the third end of the electronic switch.
Furthermore, the electronic switch is an N-type field effect transistor, a first end of the electronic switch corresponds to a gate of the N-type field effect transistor, a second end of the electronic switch corresponds to a source of the N-type field effect transistor, and a third end of the electronic switch corresponds to a drain of the N-type field effect transistor.
Further, the control signal with the first level is a low level signal, and the control signal with the second level is a high level signal.
Further, the first interface and the second interface are both a DP interface, and the processing chip is an SOC chip.
An electronic device comprises a mainboard, a display and a cable, wherein the display comprises a first interface and a display unit, the mainboard comprises a second interface, the first interface is connected with the second interface through the cable, the first interface comprises a first idle pin, the second interface comprises a second idle pin connected with a first power supply, the display further comprises a leakage protection circuit, and the leakage protection circuit comprises:
the power supply control chip is used for receiving a control signal and switching on or off the connection between the first idle pin and the second power supply according to the control signal;
the switch unit is used for receiving a switch signal output by a common end point between the first idle pin and the power control chip and outputting a corresponding trigger signal according to the switch signal; and
the processing chip is used for outputting a control signal with a first level within preset time, receiving the trigger signal and judging whether to switch the level state of the control signal after the preset time according to the trigger signal;
when the cable does not meet the VESA standard, the first idle pin is electrically connected with the second idle pin, the processing chip outputs the control signal with the first level within a preset time to control the disconnection between the first idle pin and the second power supply, the common terminal outputs a first switch signal to control the switch unit to output a first trigger signal, and the processing chip continues to output the control signal with the first level after the preset time according to the first trigger signal to disconnect the first idle pin and the second power supply.
The display and the electronic device applying the display are provided with the leakage protection circuit between the first interface and the display unit to detect whether a cable between the first interface and the second interface meets the VESA standard or not. Therefore, the display and the mainboard can not leak electricity, the normal power supply time sequence is ensured, and the risk that the mainboard can not return to the operating system from shutdown or sleep is avoided.
Drawings
FIG. 1 is a block diagram of an electronic device according to a preferred embodiment of the present invention.
FIG. 2 is a circuit diagram of the electronic device of FIG. 1 according to a preferred embodiment.
Description of the main elements
Switch unit 40
Power supplies V1, V2
Power control chip U1
Processing chip U2
Electronic switch Q1
Resistors R1 and R2
Capacitors C1, C2
Inductances L1, L2
The following detailed description will further illustrate the invention in conjunction with the above-described figures.
Detailed Description
Referring to fig. 1 and fig. 2, in a preferred embodiment, an electronic device 100 includes a display 10 and a motherboard 20, and the display 10 is connected to the motherboard 20 to establish a communication connection.
The display 10 includes a first interface 12, a leakage protection circuit 14, and a display unit 16. The leakage protection circuit 14 is connected between the first interface 12 and the display unit 16. In the present embodiment, the display unit 16 is a display screen.
The motherboard 20 includes a second interface 22, and the second interface 22 is electrically connected to the first interface 12 through a cable 30.
The first interface 12 and the second interface 22 each include an idle pin P20, and the second interface 22 is connected to a power source V1. The earth leakage protection circuit 14 includes a power control chip U1, a processing chip U2, and a switch unit 40.
The power control chip U1 is connected between the idle pin P20 of the first interface 12 and a power supply V2, and is configured to receive the control signal output by the processing chip U2, and turn on or turn off the connection between the idle pin P20 of the first interface 12 and the power supply V2 according to the control signal.
The switch unit 40 is configured to receive a switch signal output from a common node P between the idle pin P20 of the first interface 12 and the power control chip U1, and output a corresponding trigger signal according to the switch signal.
The processing chip U2 is configured to output a control signal having a first level within a preset time (e.g., 10ms), and the processing chip U2 receives the trigger signal and determines whether to switch the level state of the control signal after the preset time according to the trigger signal.
When the cable 30 does not meet the VESA standard, the idle pin P20 of the first interface 12 is electrically connected to the idle pin P20 of the second interface 22, the processing chip U2 outputs the control signal with the first level within a preset time to control the idle pin P20 of the first interface 12 and the power V2 to be disconnected, the common node P outputs a switch signal to control the switch unit 40 to output a first trigger signal, and the processing chip U2 continues to output the control signal with the first level after a preset time according to the first trigger signal to disconnect the idle pin P20 of the first interface 12 and the power V2.
When the cable 30 meets the VESA standard, the idle pin P20 of the first interface 12 is disconnected from the idle pin P20 of the second interface 22, the processing chip U2 outputs the control signal with the first level within a preset time to control the idle pin P20 of the first interface 12 and the power supply V2 to be disconnected, the common node P outputs a switch signal to control the switch unit 40 to output a second trigger signal, and the processing chip U2 switches the control signal from the first level to the second level after the preset time according to the second trigger signal to conduct the connection between the idle pin P20 of the first interface 12 and the power supply V2.
In one embodiment, the control signal having the first level is a low level signal and the control signal having the second level is a high level signal.
IN one embodiment, the power control chip U1 includes a power output pin OUT, a power input pin IN, a ground pin GND, and an enable pin EN. The processing chip U2 includes a Power _ EN signal output pin, a Detect pin, a Display control pin, and an Alert _ N signal input pin.
The power output pin OUT of the power control chip U1 is connected to the idle pin P20 of the first interface 12, the power input pin IN of the power control chip U1 is connected to the first power source V1 through an inductor L1, and the power input pin IN of the power control chip U1 is also connected to ground through a capacitor C1. The ground pin GND of the power control chip U1 is grounded, and the enable pin EN of the power control chip U1 is connected to the processing chip U2.
The Power _ EN signal output pin of the processing chip U2 is connected to the EN enable pin of the Power control chip U1, and the Detect pin Detect _ EN and the control pin Display of the processing chip U2 are both connected to the Display unit 16.
The switch unit 40 includes an electronic switch Q1, a resistor R1, and a resistor R2, a first end of the electronic switch Q1 is connected to the idle pin P20 of the first interface 12 through the resistor R1, a second end of the electronic switch Q1 is grounded, a third end of the electronic switch Q1 is connected to the power supply V1 through the resistor R2, and a third end of the electronic switch Q1 is further connected to the signal input pin Alert _ N of the processing chip U2.
The idle pin P20 of the second interface 22 is connected to a second power source V2 through an inductor L2, and is grounded through a capacitor C2.
In one embodiment, the electronic switch Q1 is an N-type fet. The first terminal of the electronic switch Q1 corresponds to the gate of the nfet, the second terminal of the electronic switch Q1 corresponds to the source of the nfet, and the third terminal of the electronic switch Q1 corresponds to the drain of the nfet.
In one embodiment, the first interface 12 and the second interface 22 are both DP interfaces. The processing Chip U2 is a SOC (System-on-a-Chip) Chip. The power supply V1 and the power supply V2 are both used for outputting 3.3V voltage.
In one embodiment, the first interface 12 further comprises a plurality of signal pins (not shown), and the second interface 22 further comprises a plurality of signal pins (not shown), wherein the plurality of signal pins of the first interface 12 are correspondingly connected to the plurality of signal pins of the second interface 22 via the cable 30.
When the first interface 12 is connected to the second interface 22 through the cable 30, if the cable 30 does not meet the VESA standard, the idle pin P20 of the first interface 12 is electrically connected to the idle pin P20 of the second interface 22; if the cable 30 meets the VESA standard, the idle pin P20 of the first interface 12 is disconnected from the idle pin P20 of the second interface 22.
In use, the electronic device 100 is connected to an ac Power source (not shown), the main board 20 is powered on, the Detect pin Detect _ EN of the processing chip U2 receives a low-level Detect signal from the display unit 16, and the signal output pin Power _ EN of the processing chip U2 outputs a low-level control signal to the enable pin EN of the Power control chip U1 within a predetermined time, so that the Power control chip U1 is in an off state. At this time, the idle pin P20 of the first interface 12 is disconnected from the power source V2.
When the cable 30 meets the VESA standard, the idle pin P20 of the first interface 12 is disconnected from the idle pin P20 of the second interface 22. The voltage at the first terminal of the electronic switch Q1 changes from 3.3V to 0V, and the electronic switch Q1 turns off. The signal input pin Alert _ N of the processing chip U2 receives the high-level trigger signal output from the power source V2, and the processing chip U2 can determine that the cable 30 meets the VESA standard according to the received high-level trigger signal. After a predetermined time, the processing chip U2 outputs a high-level control signal to the enable pin EN of the power control chip U1, and the power control chip U1 is turned on, so that the idle pin P20 of the first interface 12 and the power supply V2 are normally connected. At this time, the display 10 and the main board 20 communicate normally.
When the cable 30 does not meet the VESA standard, the idle pin P20 of the first interface 12 is electrically connected to the idle pin P20 of the second interface 22, the 3.3V output by the power source V1 is transmitted to the common node P through the idle pin P20 of the first interface 12 and the idle pin P20 of the second interface 22, the electronic switch Q1 receives the switch signal output by the common node P, the electronic switch Q1 is turned on, the signal input pin Alert _ N of the processing chip U2 is grounded and receives the low-level trigger signal output by the switch unit 40, and the processing chip U2 can determine that the cable 30 does not meet the VESA standard according to the received low-level trigger signal. After a predetermined time, the processing chip U2 outputs a low-level control signal to the enable pin EN of the power control chip U1, so that the power control chip U1 is turned off, and the idle pin P20 of the first interface 12 and the power supply V2 are disconnected, so that the voltage output by the power supply V2 does not flow to the motherboard 20.
Meanwhile, the Display pin of the processing chip U2 outputs an alarm signal to the Display unit 16. The display unit 16 outputs warning information (e.g., displays a section of warning text) according to the received warning signal, so as to prompt the user to replace the cable 30 that does not meet the VESA standard in time.
The leakage protection circuit 14 is disposed between the first interface 12 and the display unit 16, so as to detect whether the cable between the first interface 12 and the second interface 22 meets the VESA standard or not in the display 10 and the electronic device 100 using the display 10. Therefore, the display 10 and the mainboard 20 cannot leak electricity, the normal power supply time sequence is ensured, and the risk that the mainboard cannot return to the operating system from shutdown or sleep is avoided.
Finally, it should be noted that the above embodiments are only used for illustrating the technical solutions of the present invention and are not limited. It will be understood by those skilled in the art that various modifications and equivalent arrangements can be made without departing from the spirit and scope of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Claims (10)
1. The utility model provides a display, includes first interface and display element, and this first interface passes through the cable and links to each other with the second interface of mainboard, and this first interface includes first idle pin, and this second interface is including the idle pin of second of connecting first power, its characterized in that, this display still includes earth leakage protection circuit, and this earth leakage protection circuit includes:
the power supply control chip is used for receiving a control signal and switching on or off the connection between the first idle pin and the second power supply according to the control signal;
the switch unit is used for receiving a switch signal output by a common end point between the first idle pin and the power control chip and outputting a corresponding trigger signal according to the switch signal; and
the processing chip is used for outputting a control signal with a first level within preset time, receiving the trigger signal and judging whether to switch the level state of the control signal after the preset time according to the trigger signal;
when the cable does not meet the VESA standard, the first idle pin is electrically connected with the second idle pin, the processing chip outputs the control signal with the first level within a preset time to control the disconnection between the first idle pin and the second power supply, the common terminal outputs a first switch signal to control the switch unit to output a first trigger signal, and the processing chip continues to output the control signal with the first level after the preset time according to the first trigger signal to disconnect the first idle pin and the second power supply.
2. The display as claimed in claim 1, wherein when the cable complies with the VESA standard, the first idle pin is disconnected from the second idle pin, the processing chip outputs a control signal having a first level within a predetermined time to control the disconnection between the first idle pin and the second power supply, the common node outputs a second switching signal to control the switching unit to output a second trigger signal, and the processing chip switches the control signal from the first level to the second level after the predetermined time according to the second trigger signal to turn on the connection between the first idle pin and the second power supply.
3. The display as claimed in claim 1, wherein when the processing chip receives the first trigger signal, the processing chip outputs a warning signal to the display unit to control the display unit to output warning information.
4. The display as claimed in claim 3, wherein the switch unit comprises an electronic switch, a first resistor and a second resistor, a first terminal of the electronic switch is connected to the first idle pin of the first interface through the first resistor, a second terminal of the electronic switch is grounded, a third terminal of the electronic switch is connected to the second power supply through the second resistor, and the third terminal of the electronic switch is further connected to the processing chip.
5. The display as claimed in claim 4, wherein the power control chip comprises a power output pin, a power input pin, a ground pin, and an enable pin, the power output pin of the power control chip is connected to the first idle pin of the first interface, the power input pin of the power control chip is connected to the second power source through a first inductor, the power input pin of the power control chip is further grounded through a first capacitor, the ground pin of the power control chip is grounded, and the enable pin of the power control chip is connected to the processing chip.
6. The display as claimed in claim 5, wherein the processing chip comprises a signal output pin, a detection pin, a control pin, and a signal input pin, the signal output pin of the processing chip is connected to the enable pin of the power control chip, the detection pin and the control pin of the processing chip are both connected to the display unit, and the signal input pin of the processing chip is connected to the third terminal of the electronic switch.
7. The display as claimed in claim 4, wherein the electronic switch is an N-type field effect transistor, a first terminal of the electronic switch corresponds to a gate of the N-type field effect transistor, a second terminal of the electronic switch corresponds to a source of the N-type field effect transistor, and a third terminal of the electronic switch corresponds to a drain of the N-type field effect transistor.
8. The display as claimed in claim 2, wherein the control signal having the first level is a low level signal and the control signal having the second level is a high level signal.
9. The display of claim 1, wherein the first interface and the second interface are both a DP interface and the processing chip is an SOC chip.
10. An electronic device, includes mainboard, display and cable, and this display includes first interface and display element, and this mainboard includes the second interface, and this first interface links to each other with this second interface through this cable, and this first interface includes a first idle pin, and this second interface is including the idle pin of second of connecting first power, its characterized in that, this display still includes earth leakage protection circuit, and this earth leakage protection circuit includes:
the power supply control chip is used for receiving a control signal and switching on or off the connection between the first idle pin and the second power supply according to the control signal;
the switch unit is used for receiving a switch signal output by a common end point between the first idle pin and the power control chip and outputting a corresponding trigger signal according to the switch signal; and
the processing chip is used for outputting a control signal with a first level within preset time, receiving the trigger signal and judging whether to switch the level state of the control signal after the preset time according to the trigger signal;
when the cable does not meet the VESA standard, the first idle pin is electrically connected with the second idle pin, the processing chip outputs the control signal with the first level within a preset time to control the disconnection between the first idle pin and the second power supply, the common terminal outputs a first switch signal to control the switch unit to output a first trigger signal, and the processing chip continues to output the control signal with the first level after the preset time according to the first trigger signal to disconnect the first idle pin and the second power supply.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711271200.0A CN109871111B (en) | 2017-12-05 | 2017-12-05 | Display and electronic device using same |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711271200.0A CN109871111B (en) | 2017-12-05 | 2017-12-05 | Display and electronic device using same |
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| Publication Number | Publication Date |
|---|---|
| CN109871111A CN109871111A (en) | 2019-06-11 |
| CN109871111B true CN109871111B (en) | 2022-07-05 |
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| CN201711271200.0A Active CN109871111B (en) | 2017-12-05 | 2017-12-05 | Display and electronic device using same |
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Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113163140B (en) * | 2020-01-22 | 2023-05-09 | 海信视像科技股份有限公司 | Display device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103901996A (en) * | 2012-12-28 | 2014-07-02 | 鸿富锦精密工业（深圳）有限公司 | Computer system |
| CN105098406A (en) * | 2014-04-30 | 2015-11-25 | 鸿富锦精密工业(武汉)有限公司 | Wire end connector |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7737964B2 (en) * | 2006-04-05 | 2010-06-15 | Aten International Co., Ltd. | On-screen display system |
| CN102147635A (en) * | 2010-02-04 | 2011-08-10 | 鸿富锦精密工业（深圳）有限公司 | Time sequence control circuit |
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2017
- 2017-12-05 CN CN201711271200.0A patent/CN109871111B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103901996A (en) * | 2012-12-28 | 2014-07-02 | 鸿富锦精密工业（深圳）有限公司 | Computer system |
| CN105098406A (en) * | 2014-04-30 | 2015-11-25 | 鸿富锦精密工业(武汉)有限公司 | Wire end connector |
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