CN216851277U - Anti-misoperation circuit for relay protection device and relay protection device - Google Patents
Anti-misoperation circuit for relay protection device and relay protection device Download PDFInfo
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Abstract
The utility model provides a prevent malfunction circuit and overload protection device for overload protection device prevents the malfunction circuit and includes: the system comprises a microprocessor monitoring chip, a NAND gate logic chip, a first optocoupler, a second optocoupler, a first relay sub-circuit and a second relay sub-circuit; the WDO pin of the microprocessor monitoring chip is connected with the input end of the tenth pin of the NAND gate logic chip, the RESET pin of the microprocessor monitoring chip is connected with the input end of the first pin and the input end of the fifth pin of the NAND gate logic chip, the output end of the sixth pin of the NAND gate logic chip is connected with the input end of the first optocoupler, the output end of the first optocoupler is connected with the first relay sub-circuit, and the external microprocessor is connected with the microprocessor monitoring chip and the NAND gate logic chip. The utility model discloses can effectively prevent relay protection device's hardware and software unusual in work, go up the electricity, fall the electric and reset the in-process and the malfunction appears.
Description
Technical Field
The utility model relates to an electron field especially relates to a prevent malfunction circuit and relay protection device for relay protection device.
Background
With the rapid development of the power industry in China, the application of the relay protection technology is more and more extensive, and the relay protection device plays an important role in rapidly removing faults and reducing the accident range in a power system and is an indispensable important component of the power system. However, as the operation time of the equipment increases, various performance indexes of the equipment gradually decrease, and electronic components are easy to work unstably, so that the phenomena of signal error sending, no response when action is needed and the like are caused, and therefore, the protection misoperation condition of the power protection device is caused, and the safe operation of the power supply system is seriously influenced.
Therefore, when software and hardware of the relay protection device work abnormally, effective protective measures are taken to quickly lock the output of a tripping signal relay of the relay protection device, so that the device is prevented from being mistakenly operated, the safe operation of protected equipment is ensured, and the power failure accident caused by the misoperation of the relay protection device is avoided.
SUMMERY OF THE UTILITY MODEL
Based on above problem, the utility model provides a prevent malfunction circuit and overload protection device for overload protection device can prevent effectively that overload protection device's hardware and software from work unusual, go up the electricity, fall the electricity and reset the in-process malfunction appears to improve overload protection device's reliability in power supply system, ensure power system's safe operation.
The utility model provides a prevent malfunction circuit for relay protection device, include:
the system comprises a microprocessor monitoring chip, a NAND gate logic chip, a first optocoupler, a second optocoupler, a first relay sub-circuit and a second relay sub-circuit;
the WDO pin of the microprocessor monitoring chip is connected with the input end of the tenth pin of the NAND gate logic chip, the RESET pin of the microprocessor monitoring chip is connected with the input end of the first pin and the input end of the fifth pin of the NAND gate logic chip, the output end of the sixth pin of the NAND gate logic chip is connected with the input end of the first optocoupler, the output end of the first optocoupler is connected with the first relay sub-circuit, the output end of the third pin of the NAND gate logic chip is connected with the input end of the second optocoupler, the output end of the second optocoupler is connected with the second relay sub-circuit, and the external microprocessor is connected with the microprocessor monitoring chip and the NAND gate logic chip.
In addition, the connection of the external microprocessor with the microprocessor monitoring chip and the NAND gate logic chip comprises:
the ZZ _ ERR of the microprocessor is connected with the input end of a ninth pin of the NAND gate logic chip, the KC _ QD of the microprocessor is connected with the input end of a second pin of the NAND gate logic chip, and the WD I of the microprocessor is connected with the WD I pin of the microprocessor monitoring chip.
In addition, after the microprocessor judges that the protection is started in the running process, the microprocessor controls a KC _ QD end to output a high level, otherwise, the microprocessor controls the KC _ QD end to output a low level;
the microprocessor controls the WD I state to be changed continuously in the operation process;
and after detecting the abnormal fault, the microprocessor controls ZZ _ ERR to be at a low level, and if the hardware is judged to be normal, the microprocessor controls ZZ _ ERR to be at a high level.
Further, the first relay sub-circuit includes: the first relay and the first diode are connected in parallel.
Further, the second relay sub-circuit includes: a second relay and a second diode connected in parallel.
The utility model discloses still provide an adopt relay protection device's the relay protection device who prevents the malfunction circuit, include:
the microprocessor and the anti-misoperation circuit of the relay protection device;
the malfunction prevention circuit of the relay protection device includes:
the system comprises a microprocessor monitoring chip, a NAND gate logic chip, a first optocoupler, a second optocoupler, a first relay sub-circuit and a second relay sub-circuit;
the WDO pin of the microprocessor monitoring chip is connected with the input end of the tenth pin of the NAND gate logic chip, the RESET pin of the microprocessor monitoring chip is connected with the input end of the first pin and the input end of the fifth pin of the NAND gate logic chip, the output end of the sixth pin of the NAND gate logic chip is connected with the input end of the first optocoupler, the output end of the first optocoupler is connected with the first relay sub-circuit, the output end of the third pin of the NAND gate logic chip is connected with the input end of the second optocoupler, the output end of the second optocoupler is connected with the second relay sub-circuit, and the microprocessor is connected with the microprocessor monitoring chip and the NAND gate logic chip.
In addition, the microprocessor is connected with the microprocessor monitoring chip and the NAND gate logic chip and comprises:
the ZZ _ ERR of the microprocessor is connected with the input end of a ninth pin of the NAND gate logic chip, the KC _ QD of the microprocessor is connected with the input end of a second pin of the NAND gate logic chip, and the WD I of the microprocessor is connected with the WD I pin of the microprocessor monitoring chip.
In addition, after the microprocessor judges that the protection is started in the running process, the microprocessor controls a KC _ QD end to output a high level, otherwise, the microprocessor controls the KC _ QD end to output a low level;
the microprocessor controls the WD I state to be changed continuously in the operation process;
and after detecting the abnormal fault, the microprocessor controls ZZ _ ERR to be at a low level, and if the hardware is judged to be normal, the microprocessor controls ZZ _ ERR to be at a high level.
Further, the first relay sub-circuit comprises: the first relay and the first diode are connected in parallel.
Further, the second relay sub-circuit includes: a second relay and a second diode connected in parallel.
The utility model discloses can prevent effectively that relay protection device's hardware and software from working unusually, going up the electricity, falling the electric action of operation and in-process appearance that resets to improve relay protection device's reliability in power supply system, ensure electric power system's safe operation.
Drawings
Fig. 1 is a schematic diagram of a malfunction prevention circuit for a relay protection device according to an embodiment of the present invention.
Detailed Description
The present invention is described in further detail below with reference to specific embodiments and the attached drawings. It is intended that the present invention not be limited to the particular embodiments disclosed, but that the present invention will include all embodiments falling within the scope of the appended claims.
Referring to fig. 1, the utility model provides a prevent malfunction circuit for relay protection device, include:
the device comprises a microprocessor monitoring chip U1, a NAND gate logic chip U2, a first optocoupler B1, a second optocoupler B2, a first relay sub circuit and a second relay sub circuit;
the WDO pin of the microprocessor monitoring chip U1 is connected with the tenth pin input end (pin 10 of U2C) of the NAND gate logic chip U2, the RESET pin of the microprocessor monitoring chip U1 is connected with the first pin input end (pin 1 of U2A) and the fifth pin input end (pin 5 of U2B) of the NAND gate logic chip U2, an output end (pin 6 of U2B) of a sixth pin of the NAND gate logic chip U2 is connected with an input end (pin 2) of a first optocoupler B1, an output end (pin 4) of the first optocoupler B1 is connected with a first relay sub-circuit, the output end (pin 3 of U2A) of the third pin of the NAND gate logic chip U2 is connected with the input end (pin 2) of the second optical coupler B2, the output end (pin 4) of the second optical coupler B2 is connected with the second relay sub-circuit, and an external microprocessor is connected with the microprocessor monitoring chip U1 and the NAND gate logic chip U2.
Optionally, the model of the microprocessor monitoring chip U1 is MAX706, the model of the nand gate logic chip U2 is SN74ALS00, and the models of the optocouplers B1 and B2 are TLP 127.
Different signals are input to the pins of the microprocessor monitoring chip U1 according to different states of the microprocessor, the output of the NAND gate logic chip U2 is controlled, and finally the first relay sub circuit and the second relay sub circuit are cut off or normally conducted, so that the purpose of misoperation is achieved.
The circuit is an outlet power supply control circuit of the relay protection device, and can effectively control the relay protection device to prevent tripping relay misoperation under the conditions of power-on, power-off, reset, hardware abnormity and software abnormity of the device.
The utility model discloses can effectively prevent relay protection device's hardware and software unusual at work, go up the electricity, fall the electricity and reset the in-process malfunction appears to improve relay protection device's reliability in power supply system, ensure electric power system's safe operation.
In one embodiment, the connection of the external microprocessor to the microprocessor monitor chip U1 and the nand gate logic chip U2 includes:
ZZ _ ERR of the microprocessor is connected with a ninth pin input end (pin 9 of U2C) of the NAND gate logic chip U2, KC _ QD of the microprocessor is connected with a second pin input end (pin 2 of U2A) of the NAND gate logic chip U2, and WD I of the microprocessor is connected with WD I pin of the microprocessor monitoring chip U1.
The microprocessor is connected with the pins of the microprocessor monitoring chip U1 and the NOT gate logic chip U2, so that the output high level or low level is transmitted to the microprocessor monitoring chip U1 and the NOT gate logic chip U2, and the microprocessor monitoring chip U1 and the NOT gate logic chip U2 operate.
In one embodiment, after the microprocessor judges that the protection is started in the running process, the microprocessor controls a KC _ QD end to output a high level, otherwise, the microprocessor controls the KC _ QD end to output a low level;
the microprocessor controls the WD I state to be changed continuously in the operation process;
and after detecting the abnormal fault, the microprocessor controls ZZ _ ERR to be at a low level, and if the hardware is judged to be normal, the microprocessor controls ZZ _ ERR to be at a high level.
The microprocessor outputs different level signals under different operation states.
In one embodiment thereof, the first relay sub-circuit comprises: a first relay K1 and a first diode D1 connected in parallel. Optionally, the relay K1 is of the model number DSP1-DC 5V.
In one embodiment thereof, the second relay sub-circuit comprises: a second relay K2 and a second diode D2 connected in parallel.
Optionally, the model of the relay K2 is DSP2A-DC5V, the resistors R1, R2 and R3 are RJ-1/4W-10K Ω, the resistors R4 and R5 are RJ-1/4W-510 Ω, and the diodes D1 and D2 are 1N 4007.
Referring to fig. 1, in one example of implementation, the WDO pin of the microprocessor monitoring chip U1 is connected to the tenth pin input (pin 10 of U2C) of the nand gate logic chip U2, the RESET pin of the microprocessor monitoring chip U1 is connected to the first pin input (pin 1 of U2A) and the fifth pin input (pin 5 of U2B) of the nand gate logic chip U2, the sixth pin output (pin 6 of U2B) of the nand gate logic chip U2 is connected to the input (pin 2) of the first optocoupler B1, the output (pin 4) of the first optocoupler B1 is connected to the first relay sub-circuit, the third pin output (pin 3 of U2A) of the nand gate logic chip U2 is connected to the input (pin 2) of the second optocoupler B2, the output (pin 4) of the second optocoupler B2 is connected to the second relay sub-circuit, and the ZZ _ ERR nand gate logic chip U2 of the microprocessor is connected to the ninth pin 9 (pin 92) of the U2 input terminal of the U C), the KC _ QD of the microprocessor is connected with the second pin input end (pin 2 of U2A) of the NAND gate logic chip U2, and the WD I of the microprocessor is connected with the WD I pin of the microprocessor monitoring chip U1. The first relay sub-circuit includes: a first relay K1 and a first diode D1 connected in parallel. The second relay sub-circuit includes: a second relay K2 and a second diode D2 connected in parallel.
When the microprocessor detects that the hardware of the device is abnormal, the ZZ _ ERR is controlled to be at a low level, the relay K1 acts, the K1-2 contact is opened, the relay power supply of the outlet of the relay protection device is cut off, and the misoperation of the outlet of the device is prevented.
When the state of the WD I signal at the pin 6 of the microprocessor monitoring chip U1 is not changed within 1.6 seconds due to abnormal microprocessor programs, the pin 8 of the microprocessor monitoring chip U1 outputs a low level, the relay K1 acts, the K1-2 contact is opened, the power supply of the relay at the outlet of the relay protection device is cut off, and the misoperation of the outlet of the relay protection device is prevented.
When the microprocessor detects that the hardware of the relay protection device is normal and the program of the device is normal, the ZZ _ ERR is controlled to be at a high level, the relay K1 does not act, the K1-2 contact is closed, if the K2-2 contact is in a closed condition, a power supply is provided for an outlet relay of the relay protection device, and the relay protection device can control the outlet relay of the relay to act and return, such as tripping and closing.
When the protection is judged not to be started, the microprocessor controls KC _ QD to be at a low level, the relay K2 does not act, the K2-2 contact is disconnected, the relay power supply at the outlet of the relay protection device is cut off, and the relay protection device is prevented from being mistakenly operated at the outlet.
When the relay protection device judges that the protection is started, the microprocessor controls the KC _ QD to be at a high level, the K2 acts, the K2-2 contact is closed, if the K1-2 contact is under the closed condition, a power supply is provided for an outlet relay of the relay protection device, and the relay protection device can control the outlet action and the return of the relay such as tripping and closing.
When the microprocessor detects that the relay protection device has abnormalities such as EEPROM, RAM, sampling AD and the like, the relay protection device can send out wrong control commands to damage the system, the microprocessor controls ZZ _ ERR to be low level after detecting the failure, and if the microprocessor judges that the hardware normally controls ZZ _ ERR to be high level.
The microprocessor controls WD I to change state continuously during operation.
And the microprocessor judges that the protection is started in the running process and controls the KC _ QD to output a high level, otherwise, the microprocessor controls the KC _ QD to output a low level.
When the state of the signal at the pin 6 of the microprocessor monitor chip U1 does not change within 1.6 seconds, the pin 8 of the microprocessor monitor chip U1 outputs low level, otherwise the pin 8 of the U1 outputs high level.
Referring to fig. 1, the utility model also provides an adopt relay protection device's the relay protection device who prevents the malfunction circuit, include:
the microprocessor and the anti-misoperation circuit of the relay protection device;
the malfunction prevention circuit of the relay protection device includes:
the microprocessor monitoring chip U1, the NAND gate logic chip U2, a first optical coupler B1, a second optical coupler B2, a first relay sub-circuit and a second relay sub-circuit;
the WDO pin of the microprocessor monitor chip U1 is connected to the tenth pin input (pin 10 of U2C) of the NAND gate logic chip U2, the RESET pin of the microprocessor monitor chip U1 is connected to the first pin input (pin 1 of U2A) and the fifth pin input (pin 5 of U2B) of the NAND gate logic chip U2, an output end (pin 6 of U2B) of a sixth pin of the NAND gate logic chip U2 is connected with an input end (pin 2) of a first optocoupler B1, an output end (pin 4) of the first optocoupler B1 is connected with a first relay sub-circuit, the output end (pin 3 of U2A) of the third pin of the NAND gate logic chip U2 is connected with the input end (pin 2) of the second optical coupler B2, the output end (pin 4) of the second optical coupler B2 is connected with the second relay sub-circuit, and an external microprocessor is connected with the microprocessor monitoring chip U1 and the NAND gate logic chip U2.
Optionally, the model of the microprocessor monitoring chip U1 is MAX706, the model of the nand gate logic chip U2 is SN74ALS00, and the models of the optocouplers B1 and B2 are TLP 127.
Different signals are input to the pins of the microprocessor monitoring chip U1 according to different states of the microprocessor, the output of the NAND gate logic chip U2 is controlled, and finally the first relay sub circuit and the second relay sub circuit are cut off or normally conducted, so that the purpose of misoperation is achieved.
The circuit is a relay protection device outlet power supply control circuit, and can effectively control the relay protection device to prevent tripping relay misoperation under the conditions of power-on, power-off, reset, hardware abnormity and software abnormity.
The utility model discloses can prevent effectively that relay protection device's hardware and software from working unusually, going up the electricity, falling the electric action of operation and in-process appearance that resets to improve relay protection device's reliability in power supply system, ensure electric power system's safe operation.
In one embodiment, the connection of the external microprocessor to the microprocessor monitor chip U1 and the nand gate logic chip U2 includes:
ZZ _ ERR of the microprocessor is connected with a ninth pin input end (pin 9 of U2C) of the NAND gate logic chip U2, KC _ QD of the microprocessor is connected with a second pin input end (pin 2 of U2A) of the NAND gate logic chip U2, and WD I of the microprocessor is connected with WD I pin of the microprocessor monitoring chip U1.
The microprocessor is connected with pins of the microprocessor monitoring chip U1 and the NOT gate logic chip U2, so that the high level or the low level of the output is transmitted to the microprocessor monitoring chip U1 and the NOT gate logic chip U2, and the microprocessor monitoring chip U1 and the NOT gate logic chip U2 operate.
In one embodiment, after the microprocessor judges that the protection is started in the running process, the microprocessor controls a KC _ QD end to output a high level, otherwise, the microprocessor controls the KC _ QD end to output a low level;
the microprocessor controls the WD I state to be changed continuously in the operation process;
after detecting the abnormal fault, the microprocessor controls ZZ _ ERR to be in low level, and if the hardware is judged to be normal, the microprocessor controls ZZ _ ERR to be in high level.
The microprocessor outputs different level signals under different operation states.
In one embodiment thereof, the first relay sub-circuit comprises: a first relay K1 and a first diode D1 connected in parallel. Optionally, the relay K1 is of a model number DSP1-DC 5V.
In one embodiment thereof, the second relay sub-circuit comprises: a second relay K2 and a second diode D2 connected in parallel.
Optionally, the model of the relay K2 is DSP2A-DC5V, the resistors R1, R2 and R3 are RJ-1/4W-10K Ω, the resistors R4 and R5 are RJ-1/4W-510 Ω, and the diodes D1 and D2 are 1N 4007.
Referring to fig. 1, in one example of implementation, the WDO pin of the microprocessor monitoring chip U1 is connected to the tenth pin input (pin 10 of U2C) of the nand gate logic chip U2, the RESET pin of the microprocessor monitoring chip U1 is connected to the first pin input (pin 1 of U2A) and the fifth pin input (pin 5 of U2B) of the nand gate logic chip U2, the sixth pin output (pin 6 of U2B) of the nand gate logic chip U2 is connected to the input (pin 2) of the first optocoupler B1, the output (pin 4) of the first optocoupler B1 is connected to the first relay sub-circuit, the third pin output (pin 3 of U2A) of the nand gate logic chip U2 is connected to the input (pin 2) of the second optocoupler B2, the output (pin 4) of the second optocoupler B2 is connected to the second relay sub-circuit, and the ZZ _ ERR nand gate logic chip U2 of the microprocessor is connected to the ninth pin 9 (pin 92) of the U2 input terminal of the U C), the KC _ QD of the microprocessor is connected with the second pin input end (pin 2 of U2A) of the NAND gate logic chip U2, and the WD I of the microprocessor is connected with the WD I pin of the microprocessor monitoring chip U1. The first relay sub-circuit includes: a first relay K1 and a first diode D1 connected in parallel. The second relay sub-circuit includes: a second relay K2 and a second diode D2 connected in parallel.
When the microprocessor detects that the hardware of the device is abnormal, the ZZ _ ERR is controlled to be at a low level, the relay K1 acts, the K1-2 contact is opened, the relay power supply at the outlet of the relay protection device is cut off, and the misoperation of the outlet of the relay protection device is prevented.
When the WDI signal state of the pin 6 of the microprocessor monitoring chip U1 is not changed within 1.6 seconds due to abnormal microprocessor programs, the pin 8 of the microprocessor monitoring chip U1 outputs low level, the relay K1 acts, the K1-2 contact is opened, the relay power supply of the outlet of the relay protection device is cut off, and the misoperation of the outlet of the relay protection device is prevented.
When the microprocessor detects that the hardware of the relay protection device is normal and the program of the device is normal, the microprocessor controls ZZ _ ERR to be a high level, the relay K1 does not act, the K1-2 contact is closed, if the K2-2 contact is in a closed condition, a power supply is provided for an outlet relay of the relay protection device, and the relay protection device can control the outlet action and the return of the relay such as tripping and closing.
When the relay protection device judges that the protection is not started, the microprocessor controls KC _ QD to be at a low level, the relay K2 does not act, the K2-2 contact is disconnected, the power supply of the relay at the outlet of the relay protection device is cut off, and misoperation of the outlet of the relay protection device is prevented.
When the relay protection device judges that the protection is started, the microprocessor controls the KC _ QD to be at a high level, the K2 acts, the K2-2 contact is closed, if the K1-2 contact is under the closed condition, a power supply is provided for an outlet relay of the relay protection device, and the relay protection device can control the outlet action and the return of the relay such as tripping and closing.
When the microprocessor detects that the relay protection device has abnormalities such as EEPROM, RAM, sampling AD and the like, the relay protection device can send out wrong control commands to damage the system, the microprocessor controls ZZ _ ERR to be low level after detecting the failure, and if the microprocessor judges that the hardware normally controls ZZ _ ERR to be high level.
The microprocessor controls the WD I state to change continuously during operation.
And the microprocessor judges that the protection is started in the running process and controls the KC _ QD to output a high level, otherwise, the microprocessor controls the KC _ QD to output a low level.
When the state of the signal at the pin 6 of the microprocessor monitor chip U1 does not change within 1.6 seconds, the pin 8 of the microprocessor monitor chip U1 outputs low level, otherwise the pin 8 of the U1 outputs high level.
The embodiment effectively prevents the misoperation problem of the relay protection device caused by the working abnormality, power-on, power-off and reset processes of hardware or software of the device. The reliable operation of the power supply equipment is ensured, and personal injury and economic loss caused by power failure accidents of a power supply system are avoided.
What has been described above is merely the principles and preferred embodiments of the present invention. It should be noted that, for those skilled in the art, on the basis of the principle of the present invention, several other modifications can be made, and the protection scope of the present invention should be considered.
Claims (10)
1. An anti-malfunction circuit for a relay protection device, comprising:
the device comprises a microprocessor monitoring chip, a NAND gate logic chip, a first optocoupler, a second optocoupler, a first relay sub-circuit and a second relay sub-circuit;
the WDO pin of the microprocessor monitoring chip is connected with the input end of the tenth pin of the NAND gate logic chip, the RESET pin of the microprocessor monitoring chip is connected with the input end of the first pin and the input end of the fifth pin of the NAND gate logic chip, the output end of the sixth pin of the NAND gate logic chip is connected with the input end of the first optocoupler, the output end of the first optocoupler is connected with the first relay sub-circuit, the output end of the third pin of the NAND gate logic chip is connected with the input end of the second optocoupler, the output end of the second optocoupler is connected with the second relay sub-circuit, and the external microprocessor is connected with the microprocessor monitoring chip and the NAND gate logic chip.
2. The malfunction prevention circuit for a relay protection device according to claim 1,
the connection of the external microprocessor, the microprocessor monitoring chip and the NAND gate logic chip comprises:
the ZZ _ ERR end of the microprocessor is connected with the input end of the ninth pin of the NAND gate logic chip, the KC _ QD end of the microprocessor is connected with the input end of the second pin of the NAND gate logic chip, and the WDI end of the microprocessor is connected with the WDI pin of the microprocessor monitoring chip.
3. The malfunction prevention circuit for a relay protection device according to claim 1,
after judging the protection start in the operation process, the microprocessor controls a KC _ QD end to output a high level, otherwise, controls the KC _ QD end to output a low level;
the microprocessor controls the WDI state to be changed continuously in the running process;
and after detecting the abnormal fault, the microprocessor controls ZZ _ ERR to be at a low level, and if the hardware is judged to be normal, the microprocessor controls ZZ _ ERR to be at a high level.
4. The malfunction prevention circuit for a relay protection device according to claim 1,
the first relay sub-circuit includes: the first relay and the first diode are connected in parallel.
5. The malfunction prevention circuit for a relay protection device according to any one of claims 1 to 4,
the second relay sub-circuit includes: a second relay and a second diode connected in parallel.
6. A relay protection device using a malfunction prevention circuit of the relay protection device, comprising:
the microprocessor and the anti-misoperation circuit of the relay protection device;
the malfunction prevention circuit of the relay protection device includes:
the system comprises a microprocessor monitoring chip, a NAND gate logic chip, a first optocoupler, a second optocoupler, a first relay sub-circuit and a second relay sub-circuit;
the WDO pin of the microprocessor monitoring chip is connected with the input end of the tenth pin of the NAND gate logic chip, the RESET pin of the microprocessor monitoring chip is connected with the input end of the first pin and the input end of the fifth pin of the NAND gate logic chip, the output end of the sixth pin of the NAND gate logic chip is connected with the input end of the first optocoupler, the output end of the first optocoupler is connected with the first relay sub-circuit, the output end of the third pin of the NAND gate logic chip is connected with the input end of the second optocoupler, the output end of the second optocoupler is connected with the second relay sub-circuit, and the microprocessor is connected with the microprocessor monitoring chip and the NAND gate logic chip.
7. The relay protection device according to claim 6, wherein the relay protection device further comprises a malfunction prevention circuit,
the microprocessor is connected with the microprocessor monitoring chip and the NAND gate logic chip and comprises:
ZZ _ ERR of the microprocessor is connected with the input end of a ninth pin of the NAND gate logic chip, KC _ QD of the microprocessor is connected with the input end of a second pin of the NAND gate logic chip, and WD I of the microprocessor is connected with WD I of the microprocessor monitoring chip.
8. The relay protection device according to claim 6, wherein the relay protection device further comprises a malfunction prevention circuit,
after judging the protection start in the operation process, the microprocessor controls a KC _ QD end to output a high level, otherwise, controls the KC _ QD end to output a low level;
the microprocessor controls the WDI state to be changed continuously in the running process;
and after detecting the abnormal fault, the microprocessor controls ZZ _ ERR to be at a low level, and if the hardware is judged to be normal, the microprocessor controls ZZ _ ERR to be at a high level.
9. The relay protection device according to claim 6, wherein the relay protection device further comprises a malfunction prevention circuit,
the first relay sub-circuit includes: the first relay and the first diode are connected in parallel.
10. The relay protection device using a malfunction prevention circuit of a relay protection device according to any one of claims 6 to 9,
the second relay sub-circuit includes: a second relay and a second diode connected in parallel.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116488626A (en) * | 2023-04-17 | 2023-07-25 | 基康仪器股份有限公司 | Monitoring switch circuit, method and device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116488626A (en) * | 2023-04-17 | 2023-07-25 | 基康仪器股份有限公司 | Monitoring switch circuit, method and device |
| CN116488626B (en) * | 2023-04-17 | 2024-01-30 | 基康仪器股份有限公司 | Monitoring switch circuit, method and device |
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