CN111831498A - Power failure test method, device and equipment - Google Patents
Power failure test method, device and equipment Download PDFInfo
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- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
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- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a power-off test method, and in the application, considering that a BMC and a CPLD are still in a power-on state after a server is powered off, a processor in the application can control the server to be powered off and turn over an enabling level of an enabling end of a standby power conversion chip of the server for a preset time length, so that the BMC and the CPLD can be completely powered off, the same power-off effect as the alternating current power-off effect is achieved, the power is powered on again after the preset time length is over, the operation is circulated until the preset test times are reached, manual repeated disconnection and connection work of an alternating current power supply is not needed, the working efficiency is improved, and the labor cost is reduced. The invention also discloses a power failure testing device and equipment, which have the same beneficial effects as the power failure testing method.
Description
Technical Field
The invention relates to the field of servers, in particular to a power failure testing method, and further relates to a power failure testing device and equipment.
Background
Considering that the server is inevitably subjected to some abnormal power failure conditions in the use process, before the server leaves a factory, the server needs to be subjected to multiple power failure tests to verify the reliability of each device in the server, but in the prior art, when the server is subjected to the alternating current power failure test, a worker needs to repeatedly and manually disconnect and connect an alternating current power supply, so that the working efficiency is low, and the labor cost is high.
Therefore, how to provide a solution to the above technical problem is a problem that needs to be solved by those skilled in the art.
Disclosure of Invention
The invention aims to provide a power failure testing method, which does not need to manually and repeatedly disconnect and connect an alternating current power supply, improves the working efficiency and reduces the labor cost; another object of the present invention is to provide a power failure testing apparatus and device, which do not need to manually and repeatedly disconnect and connect the ac power supply, thereby improving the working efficiency and reducing the labor cost.
In order to solve the above technical problem, the present invention provides a power-off testing method applied to a processor, including:
s11: controlling the server to be powered off and turning over the enabling level of the enabling end of the standby power conversion chip of the server for a preset time so that the server is powered off for the preset time and powered on again;
s12: after the server is powered on, adding the tested times together to judge whether the tested times reach a preset test time, if not, returning to S11, and if so, executing S13;
s13: the test is ended.
Preferably, the turning over the enable level of the enable end of the standby power conversion chip of the server for the preset time period specifically includes:
and sending a trigger pulse to a monostable delay circuit so that the monostable delay circuit can overturn the enabling level sent to the enabling end of the standby power supply conversion chip in a steady state for a preset time.
Preferably, the monostable delay circuit comprises a first controllable switch, a second controllable switch, a power supply, a monostable delay chip and a peripheral circuit;
the control end of the first controllable switch is connected with the processor, the first end of the first controllable switch is respectively connected with the power supply and the input end of the monostable delay chip, the first end of the first controllable switch is grounded, the power supply is connected with the power supply interface of the monostable delay chip, the output end of the monostable delay chip is connected with the control end of the second controllable switch, the first end of the second controllable switch is connected with the enable end of the standby power supply conversion chip, and the second end of the second controllable switch is grounded;
the peripheral circuit is used for setting the preset duration of the transient state of the monostable delay chip through the peripheral circuit;
wherein the enable level is a high level and the trigger pulse is a high level.
Preferably, the controlling the server to shut down and the turning over the enable level of the enable end of the standby power conversion chip of the server for the preset duration specifically includes:
responding to the alternating current power-off test instruction, controlling the server to shut down and turning over the enabling level of the enabling end of the standby power conversion chip of the server for a preset time;
the power-off test method further includes:
responding to a direct current power-off test instruction, and controlling the server to be powered on after being powered off for a preset time;
after the mainboard is powered on, adding the accumulated test times of the direct current power failure and judging whether the accumulated test times of the direct current power failure reach the preset direct current test times;
if not, returning to respond to the direct current power-off test instruction, and controlling the server to be powered on after being powered off for a preset time;
the tested times are AC outage accumulated test times, and the preset test times are preset AC test times.
Preferably, after the cumulative test number of the ac power outage is increased by one after the BMC is powered on, the power outage test method further includes:
controlling a prompter to prompt the AC outage accumulated test times;
after the accumulated test times of the direct current power failure is increased by one after the mainboard is powered on, the power failure test method further comprises the following steps:
and the control prompter prompts the accumulated test times of the direct current power failure.
Preferably, the power outage test method further comprises:
and acquiring the preset alternating current test times or the preset direct current test times sent by the human-computer interaction module in advance.
Preferably, the processor is a baseboard management controller BMC of the server.
In order to solve the above technical problem, the present invention further provides a power failure testing apparatus, applied to a processor, including:
the control module is used for controlling the shutdown of the server and overturning the enabling level of the enabling end of the standby power conversion chip of the server for a preset time so that the server is powered off for the preset time and powered on again;
the judging module is used for adding the tested times together to judge whether the tested times reach the preset testing times after the server is powered on, if not, the control module is triggered, and if so, the ending module is triggered;
and the ending module is used for ending the test.
Preferably, the turning over the enable level of the enable end of the standby power conversion chip of the server for the preset time period specifically includes:
and sending a trigger pulse to a monostable delay circuit so that the monostable delay circuit can overturn the enabling level sent to the enabling end of the standby power supply conversion chip in a steady state for a preset time.
In order to solve the above technical problem, the present invention further provides a power failure testing apparatus, including:
a memory for storing a computer program;
a processor for implementing the steps of the power outage testing method as described in any one of the above when executing the computer program.
The invention provides a power-off test method, and in the application, considering that a BMC and a CPLD are still in a power-on state after a server is powered off, a processor in the application can control the server to be powered off and turn over an enabling level of an enabling end of a standby power conversion chip of the server for a preset time length, so that the BMC and the CPLD can be completely powered off, the same power-off effect as the alternating current power-off effect is achieved, the power is powered on again after the preset time length is over, the operation is circulated until the preset test times are reached, manual repeated disconnection and connection work of the alternating current power supply is not needed, the working efficiency is improved, and the labor cost is reduced.
The invention also provides a power failure testing device and equipment, which have the same beneficial effects as the power failure testing method.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed in the prior art and the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
FIG. 1 is a schematic flow chart of a power-off test method according to the present invention;
fig. 2 is a schematic structural diagram of a server power supply system according to the present invention;
FIG. 3 is a schematic structural diagram of a power-off test apparatus according to the present invention;
FIG. 4 is a schematic structural diagram of a power-off testing apparatus according to the present invention;
FIG. 5 is a schematic structural diagram of another power-off test apparatus provided in the present invention.
Detailed Description
The core of the invention is to provide a power-off test method, which does not need to manually and repeatedly disconnect and connect the alternating current power supply, improves the working efficiency and reduces the labor cost; another object of the present invention is to provide a power failure testing apparatus and device, which do not need to manually and repeatedly disconnect and connect the ac power supply, thereby improving the working efficiency and reducing the labor cost.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a schematic flow chart of a power-off testing method provided by the present invention, the power-off testing method includes:
s11: controlling the server to shut down and turning over the enabling level of the enabling end of the standby power conversion chip of the server for a preset time so that the server is powered off for the preset time and powered on again;
to better explain the embodiment of the present invention, please refer to fig. 2, fig. 2 is a schematic structural diagram of a server power supply system provided by the present invention, specifically, a core characteristic of ac power outage is that a server is powered off and standby portions (BMC (Baseboard Management Controller) and CPLD (complex programmable Logic Device)) in the server are powered off, but when the server is controlled to be powered off without disconnecting the ac power supply, the standby power supply in the server is powered on and keeps the power-on states of the BMC and the CPLD, so in the embodiment of the present invention, in order to automatically simulate the ac power outage state, the enable level of the enable end of the standby power conversion chip in the server may be reversed for a preset duration after the server is controlled to be powered off, so that the server is completely powered off (ac power outage is simulated) and due to the reversed preset duration, after the preset duration is over, the enable level is restored, the standby power conversion chip outputs electric energy again to enable the BMC and the CPLD to be powered on, and then the BMC can control the server to be started.
Specifically, in fig. 2, the motherboard of the server may adopt a power supply scheme as shown in fig. 2, and the alternating current AC outputs 12V _ STBY direct current and 12V _ mainpower direct current after passing through the power supply PSU. The 12V _ STBY generates other STBY electricity through corresponding circuits, such as 3V3_ STBY or 5V _ STBY, and the like, the STBY electricity is used for supplying power to the CPLD and the BMC, and the BMC notifies the CPLD and the CPLD to control the time sequence power-on and time sequence power-off of 12V _ mainpower and other mainpower supplies by sending a power-on or power-off instruction to the BMC. Functionally, STBY power is the most basic power for ensuring the normal power-on of the motherboard from the standby state, and mainpower power is used for ensuring the normal operation of the devices on the motherboard except for CPLD and BMC.
The general DC power failure means that the mainpower is cut off, and the STBY power is not broken. The AC power failure is to cut off the external AC power, so that the mainpower and STBY power output by the PSU are cut off together, therefore, the idea of the invention is to cut off the mainpower and STBY power on the right side of the PSU instead of the AC power on the left side of the PSU. From the previous paragraph, if the STBY power is cut off, the CPLD and the BMC cannot work, and therefore the mainpower cannot be powered on, that is, the mainpower depends on the STBY power, and the effect of replacing the external AC power on and power off can be achieved by controlling the on and off of the STBY power.
Specifically, the power of the server motherboard 12V _ STBY is controlled by the power conversion chip VR to be output 12V _ STBY from the 12V power output by the PSU, and the power chips all have an EN pin for controlling the on-off of the 12V _ STBY. In the existing scheme, the input level of the pin is 12V _ PSU, and the input level is controlled by a normally high level obtained by dividing a resistor, so that the EN is ensured to be normally high as long as the PSU is plugged.
The preset time can be set autonomously, and the standby power conversion chip can not output electric energy within the preset time, so that the BMC and the CPLD can complete the power-off process.
S12: after the server is powered on, adding the tested times, judging whether the tested times reach the preset testing times, if not, returning to S11, and if so, executing S13;
specifically, after the server is powered on, it may be considered that a test of ac power outage is completed once, because the purpose of the ac power outage test is to test that the server is not abnormal under a condition of multiple ac power outages, the ac power outage test generally has a preset test frequency, and the test may be ended after the test frequency reaches the preset test frequency, so that the step S11 may be returned when the preset test frequency is not reached, and the step S13 is executed when the preset test frequency is reached, so as to end the test.
The preset number of times of testing may be set autonomously, for example, may be 100 times, and the embodiment of the present invention is not limited herein.
Specifically, after the server is powered on, a worker may perform detection on the server to determine whether the server is abnormal due to ac outage, which may be performed according to an original detection process.
S13: the test is ended.
Specifically, the ending of the test refers to ending of the ac power failure test, and then the server can restore the original normal state.
Of course, the server may send a prompt to end the test through the prompter, so that the staff can learn the prompt, and the embodiment of the present invention is not limited herein.
On the basis of the above-described embodiment:
as a preferred embodiment, the turning over the enable level of the enable end of the standby power conversion chip of the server for the preset duration specifically includes:
and sending a trigger pulse to the monostable delay circuit so that the monostable delay circuit overturns the enabling level sent to the enabling end of the standby power supply conversion chip in a steady state for a preset time.
Specifically, the monostable delay circuit is in a steady state when the trigger pulse is not received, the monostable delay circuit can send an enable level to the enable end of the standby power conversion chip, the level does not interfere with the original level state of the enable end of the standby power conversion chip, namely, the enable state of the enable end of the standby power conversion chip is kept, after the trigger pulse is received, the monostable delay circuit enters a transient state, namely, the output level of the monostable delay circuit is overturned for a preset time, and the function of controlling the preset time for the incapability of the standby power conversion chip is achieved.
The monostable delay circuit has the advantages of strong stability, long service life, low price and the like.
Of course, besides the monostable delay circuit, the control of turning over the enable level of the enable end of the standby power conversion chip of the server for the preset time may also be implemented by other circuits, and the embodiment of the present invention is not limited herein.
For better explaining the embodiment of the present invention, please refer to fig. 3, fig. 3 is a schematic structural diagram of a power-off test device provided by the present invention, and as a preferred embodiment, the monostable delay circuit includes a first controllable switch T1, a second controllable switch T2, a power supply, a monostable delay chip 555, and a peripheral circuit;
the control end of the first controllable switch T1 is connected with the processor, the first end of the first controllable switch T1 is respectively connected with the power supply and the input end of the monostable delay chip 555, the first end of the first controllable switch T1 is grounded, the power supply is connected with the power interface of the monostable delay chip 555, the output end of the monostable delay chip 555 is connected with the control end of the second controllable switch T2, the first end of the second controllable switch T2 is connected with the enable end of the standby power supply conversion chip, and the second end of the second controllable switch T2 is grounded;
the peripheral circuit is used for setting the preset time length of the transient state of the monostable delay chip 555;
wherein, the enabling level is high level, and the trigger pulse is high level.
Specifically, in fig. 3, as shown in the right side of fig. 3, which is composed of 12V _ PSU, R2, R3 and 12V _ STBY modules, R2 may be about 3 times of R3, so that the divided 3V is high, so as to ensure that the EN of the standby power conversion chip VR can be normally high as long as the PSU is plugged in, where R2 may be selected as 42.2K, R3 may be selected as 8.45K, and the obtained voltage is about 3.3V, and different VRs require different high levels of EN, so as to adjust the corresponding resistance values of the resistors.
Specifically, the basic idea in the embodiment of the present invention is to form a monostable delay circuit by using a 555 chip to control the delayed on-off of the VR chip EN pin, and the specific composition may be as follows:
the BMC and the CPLD chip which are arranged on the mainboard are utilized to form a basic logic control unit, and the BMC informs whether the CPLD is powered off or not and informs whether the CPLD is powered off or not. When the CPLD judges that normal shutdown (DC shutdown) is performed, executing the original time sequence power-down logic; when the CPLD determines that the execution is AC power down, and executes to turn off the last mainpower according to the original power down sequence, the CPLD outputs a high level to the 555 unit through a General-purpose input/output (GPIO) pin. As shown in fig. 3, the CPLD outputs a GPIO pin to the G (gate) pole of T1, the S (source) pole of T1 is grounded, and the D (drain) pole is connected to a 5V _ RTC power supply through a pull-up resistor R1 (5V _ RTC means power supplied by a 5V RTC battery, because when the 12V _ STBY mainpower is turned off, no other power exists on the motherboard, and an additional 5V battery is needed to supply power to the 555 circuit). The drain of the T1 is also connected to the input end of the 555 chip, when the GPIO of the CPLD is in low level or high impedance state, the T1 is cut off, the 555 input is pulled high, when the GPIO inputs high level, the T1 is turned on, and the 555 input is pulled low. The monostable delay circuit formed by 555 is composed of a 555 chip, an RC circuit and a peripheral circuit thereof, and when the input is low, the output is low; when the input is high, the circuit is converted into a transient state, and the output is high; when the input is low again, the output is low after a period of preset duration. The preset duration is determined by the values of R and C in fig. 3:
T＝1.1RC
here we choose C to be 220uf and the preset duration T to be 20S, so R T/1.1/C82.644K ohms, here we choose 80K ohms.
The output end of the 555 circuit is connected to the grid of the T2, the source of the T2 is grounded, and the drain is connected between the R2 and the R3. As mentioned above, when the GPIO signal sends out high level, 555 circuit output end is pulled up instantly, at this time, T2 is conducted, the level between R2 and R3 is pulled down, VR forbids enabling EN, the STBY power of CPLD and BMC is cut off, GPIO pin of CPLD is pulled down or is in high resistance state, T1 is cut off, 555 input pin is pulled up again, namely a low pulse signal is formed for 555, 555 outputs high when receiving low pulse falling edge, can be pulled down again after 20S delay, namely EN pin of VR can be changed from low to high after 20S, more straightly STBY can be recovered after 12V _ BY passes 20S. Thereby completing the 12V _ STBY power down procedure.
Specifically, the situation that the AC power is needed to be cut off is not two situations, one is that the AC power is circularly switched on and off, namely the AC power is powered on and started up within a set time, and the AC power is powered off and shut down after the corresponding test is finished after the AC power is started up, and then the AC power is repeatedly switched on and shut down; one is a single power-off, for example, firmware FW of CPLD or BMC is burned on line, and the firmware FW becomes effective after the AC power-off is restarted, and this only needs to be powered off once.
The process of completing the power-on and power-off times of the mainboard can be completed only by the cooperation of the BMC. Sending a chasis poweron or chasis poweroff to the BMC through the BMC serial port can enable the BMC to inform the CPLD to execute startup or shutdown, and sending a chasis status can inquire whether the mainboard is in a power-on state or a power-off state. The serial port sends the gpiotool number (such as 66) - -set-di-output) to the BMC, the input and output mode of the BMC gpio can be set, and the gpiotool number (such as 66) - -set-data-low/high) can set the BMC gpio to be high or low, so as to inform the CPLD whether the AC is powered off or not. In addition, when the AC or the DC is circulated, the counting times can be counted, and a human-computer interface written by C # is designed for the counting times so as to facilitate the operation.
Specifically, the monostable delay circuit provided by the embodiment of the invention has the advantages of simple structure, low cost and short corresponding time.
Of course, in addition to the structure of the monostable delay circuit provided in the embodiment of the present invention, the monostable delay circuit may also be of other specific types, and the embodiment of the present invention is not limited herein.
The first controllable switch T1 and the second controllable switch T2 may be of the same type, for example, MOS (Metal-Oxide-Semiconductor Field-Effect Transistor) transistors, and the like, which are not limited herein.
As a preferred embodiment, the controlling the server to shut down and turning over the enable level of the enable end of the standby power conversion chip of the server for the preset duration specifically includes:
responding to the alternating current power-off test instruction, controlling the server to shut down and turning over the enabling level of the enabling end of the standby power conversion chip of the server for a preset time;
the power-off test method further includes:
responding to the direct current power-off test instruction, and controlling the server to be powered on after being powered off for a preset time;
after the mainboard is powered on, adding the accumulated test times of the direct current power failure and judging whether the accumulated test times of the direct current power failure reach the preset direct current test times;
if not, returning to respond to the direct current power-off test instruction, and controlling the server to be powered on after being powered off for a preset time;
the tested times are the accumulated testing times of the alternating current outage, and the preset testing times are the preset alternating current testing times.
Specifically, in addition to the alternating current power-off test, the embodiment of the invention can also select the direct current power-off test, so that the convenience and the flexibility of the test are improved, but only one of the tests can be performed at the same time.
The preset dc test frequency and the preset ac test frequency may be set independently, for example, the preset dc test frequency and the preset ac test frequency may be the same value.
As a preferred embodiment, after the ac power outage cumulative test number is increased by one after the BMC is powered on, the power outage test method further includes:
the control prompter prompts the AC power failure accumulated test times;
after the accumulated test times of the direct current power failure is increased by one after the mainboard is powered on, the power failure test method further comprises the following steps:
and the control prompter prompts the accumulated test times of the direct current power failure.
Specifically, the prompt of the prompter can facilitate the staff to quickly and accurately know the accumulated test times.
The prompt may be of various types, for example, a display or a voice prompt, and the embodiment of the present invention is not limited herein.
As a preferred embodiment, the power outage testing method further includes:
and pre-acquiring the preset alternating current test times or the preset direct current test times sent by the human-computer interaction module.
Specifically, in order to facilitate setting of the test times, in the embodiment of the invention, a worker can conveniently send the preset alternating current test times or the preset direct current test times through the human-computer interaction module so as to set the test times, so that the test controllability is improved.
In a preferred embodiment, the processor is a baseboard management controller BMC of the server.
Specifically, the BMC is an original controller in the server, and can achieve the effects of saving cost and improving structural integrity.
Of course, the processor may be of various types other than the BMC, and the embodiment of the present invention is not limited herein.
Referring to fig. 4, fig. 4 is a schematic structural diagram of a power-off testing apparatus applied to a processor, the power-off testing apparatus including:
the control module 1 is used for controlling the shutdown of the server and turning over the enable level of the enable end of the standby power conversion chip of the server for a preset time so as to power off the server for the preset time and power on the server again;
the judging module 2 is used for adding the tested times together after the server is powered on to judge whether the tested times reach the preset testing times, if not, the control module is triggered, and if so, the ending module is triggered;
and the ending module 3 is used for ending the test.
As a preferred embodiment, the turning over the enable level of the enable end of the standby power conversion chip of the server for the preset duration specifically includes:
and sending a trigger pulse to the monostable delay circuit so that the monostable delay circuit overturns the enabling level sent to the enabling end of the standby power supply conversion chip in a steady state for a preset time.
For the description of the power failure testing apparatus provided in the embodiment of the present invention, reference is made to the foregoing embodiment of the power failure testing method, and details of the embodiment of the present invention are not repeated herein.
Referring to fig. 5, fig. 5 is a schematic structural diagram of another power failure testing apparatus provided in the present invention, the power failure testing apparatus includes:
a memory 4 for storing a computer program;
a processor 5 for implementing the steps of the power down test method as in the previous embodiments when executing the computer program.
For the description of the power failure testing apparatus provided in the embodiment of the present invention, reference is made to the foregoing embodiment of the power failure testing method, and details of the embodiment of the present invention are not repeated herein.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A power-off test method is applied to a processor and is characterized by comprising the following steps:
s11: controlling the server to be powered off and turning over the enabling level of the enabling end of the standby power conversion chip of the server for a preset time so that the server is powered off for the preset time and powered on again;
s12: after the server is powered on, adding the tested times together to judge whether the tested times reach a preset test time, if not, returning to S11, and if so, executing S13;
s13: the test is ended.
2. The power-off test method according to claim 1, wherein the turning over the enable level of the enable terminal of the standby power conversion chip of the server for the preset duration specifically comprises:
and sending a trigger pulse to a monostable delay circuit so that the monostable delay circuit can overturn the enabling level sent to the enabling end of the standby power supply conversion chip in a steady state for a preset time.
3. The power-off test method according to claim 2, wherein the monostable delay circuit comprises a first controllable switch, a second controllable switch, a power supply, a monostable delay chip and a peripheral circuit;
the control end of the first controllable switch is connected with the processor, the first end of the first controllable switch is respectively connected with the power supply and the input end of the monostable delay chip, the first end of the first controllable switch is grounded, the power supply is connected with the power supply interface of the monostable delay chip, the output end of the monostable delay chip is connected with the control end of the second controllable switch, the first end of the second controllable switch is connected with the enable end of the standby power supply conversion chip, and the second end of the second controllable switch is grounded;
the peripheral circuit is used for setting the preset duration of the transient state of the monostable delay chip through the peripheral circuit;
wherein the enable level is a high level and the trigger pulse is a high level.
4. The power-off test method according to claim 1, wherein the controlling the server to shut down and to turn over the enable level of the enable terminal of the standby power conversion chip of the server for the preset time period specifically comprises:
responding to the alternating current power-off test instruction, controlling the server to shut down and turning over the enabling level of the enabling end of the standby power conversion chip of the server for a preset time;
the power-off test method further includes:
responding to a direct current power-off test instruction, and controlling the server to be powered on after being powered off for a preset time;
after the mainboard is powered on, adding the accumulated test times of the direct current power failure and judging whether the accumulated test times of the direct current power failure reach the preset direct current test times;
if not, returning to respond to the direct current power-off test instruction, and controlling the server to be powered on after being powered off for a preset time;
the tested times are AC outage accumulated test times, and the preset test times are preset AC test times.
5. The power down test method of claim 4, wherein after adding one to the cumulative number of AC power down tests after the BMC was powered up, the power down test method further comprises:
controlling a prompter to prompt the AC outage accumulated test times;
after the accumulated test times of the direct current power failure is increased by one after the mainboard is powered on, the power failure test method further comprises the following steps:
and the control prompter prompts the accumulated test times of the direct current power failure.
6. The power outage test method according to claim 5, characterized in that the power outage test method further comprises:
and acquiring the preset alternating current test times or the preset direct current test times sent by the human-computer interaction module in advance.
7. The power outage test method according to any one of claims 1 to 6, wherein the processor is a Baseboard Management Controller (BMC) of the server.
8. A power-off test device applied to a processor is characterized by comprising:
the control module is used for controlling the shutdown of the server and overturning the enabling level of the enabling end of the standby power conversion chip of the server for a preset time so that the server is powered off for the preset time and powered on again;
and the judging module is used for adding the tested times together after the server is powered on to judge whether the tested times reach the preset testing times, and if not, the control module is triggered.
9. The power outage test device according to claim 8, wherein the turning over the enable level of the enable terminal of the standby power conversion chip of the server for the preset duration specifically comprises:
and sending a trigger pulse to a monostable delay circuit so that the monostable delay circuit can overturn the enabling level sent to the enabling end of the standby power supply conversion chip in a steady state for a preset time.
10. An outage test apparatus, comprising:
a memory for storing a computer program;
a processor for implementing the steps of the power outage testing method according to any one of claims 1-7 when executing the computer program.
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