CN111831498B - Power-off test method, device and equipment - Google Patents
Power-off test method, device and equipment Download PDFInfo
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- CN111831498B CN111831498B CN202010692659.3A CN202010692659A CN111831498B CN 111831498 B CN111831498 B CN 111831498B CN 202010692659 A CN202010692659 A CN 202010692659A CN 111831498 B CN111831498 B CN 111831498B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application discloses a power-off test method, in the application, considering that a BMC and a CPLD are still in a power-on state after a server is powered off, a processor in the application can control the server to be powered off and turn over the enabling level of an enabling end of a standby power conversion chip of the server for a preset time period, so that the BMC and the CPLD can be completely powered off, the same power-off effect as that of alternating current power-off is achieved, and the BMC and the CPLD are powered on again when the preset time period is finished, the power-off test is circulated until the preset test times are achieved, the work of disconnecting and connecting the alternating current power supply is not needed to be repeated manually, the work efficiency is improved, and the labor cost is reduced. The application also discloses a power-off testing device and equipment, which have the same beneficial effects as the power-off testing method.
Description
Technical Field
The application relates to the field of servers, in particular to a power-off test method, and also relates to a power-off test device and equipment.
Background
In consideration of the situation that the server is inevitably subjected to abnormal power failure in the use process, the server needs to be subjected to power failure test for many times before leaving the factory to verify the reliability of each device in the server, but in the prior art, when the alternating current power failure test is carried out on the server, a worker is required to repeatedly and manually disconnect and connect an alternating current power supply, so that the working efficiency is low, and the labor cost is high.
Therefore, how to provide a solution to the above technical problem is a problem that a person skilled in the art needs to solve at present.
Disclosure of Invention
The application aims to provide a power-off test method, which does not need to repeatedly disconnect and connect an alternating current power supply manually, improves the working efficiency and reduces the labor cost; the application further aims to provide a power-off testing device and equipment, which do not need to repeatedly disconnect and connect an alternating current power supply manually, improve the working efficiency and reduce the labor cost.
In order to solve the above technical problems, the present application provides a power-off test method, which is applied to a processor, and includes:
s11: the method comprises the steps of controlling a server to be powered off and turning over an enabling level of an enabling end of a standby power supply conversion chip of the server for a preset time period so that the server is powered off for the preset time period and powered on again;
s12: after the server is powered on, adding the tested times together to judge whether the tested times reach the preset test times, if not, returning to the step S11, and if so, executing the step S13;
s13: ending the test.
Preferably, the turning preset duration of the enabling level of the enabling end of the standby power conversion chip of the server is specifically:
and sending a trigger pulse to the monostable delay circuit, so that the monostable delay circuit can overturn the enabling level sent to the enabling end of the standby power conversion chip in a steady state for a preset time.
Preferably, the monostable delay circuit comprises a first controllable switch, a second controllable switch, a power supply, a monostable delay chip and a peripheral circuit;
the control end of the first controllable switch is connected with the processor, the first end of the first controllable switch is respectively connected with the power supply and the input end of the monostable time delay chip, the first end of the first controllable switch is grounded, the power supply is connected with the power supply interface of the monostable time delay chip, the output end of the monostable time delay chip is connected with the control end of the second controllable switch, the first end of the second controllable switch is connected with the enabling end of the standby power supply conversion chip, and the second end of the second controllable switch is grounded;
the peripheral circuit is used for setting the preset duration of the transient state of the monostable delay chip through the peripheral circuit;
wherein the enabling level is a high level, and the trigger pulse is a high level.
Preferably, the control server is turned off and turns over the enabling level of the enabling end of the standby power conversion chip of the server for a preset period of time specifically:
responding to an alternating current power-off test instruction, controlling the server to be powered off and turning over the enabling level of the enabling end of the standby power supply conversion chip of the server for a preset period of time;
the power down test method further comprises:
responding to a direct current power-off test instruction, and controlling the server to be powered on after being powered off for a preset time period;
adding the accumulated test times of the direct current power failure after the main board is electrified, and judging whether the accumulated test times of the direct current power failure reach the preset direct current test times or not;
if not, returning to the step of controlling the power-on after the server is powered off for a preset time period in response to the direct current power-off test instruction;
the tested times are accumulated test times of alternating current power failure, and the preset test times are preset alternating current test times.
Preferably, after the accumulated ac power-off test number is increased by one after the BMC is powered up, the power-off test method further includes:
the control prompter prompts the alternating current power failure accumulated test times;
after the accumulated test times of the direct current power-off are increased by one after the main board is powered on, the power-off test method further comprises the following steps:
and the control prompter prompts the direct current power failure accumulated test times.
Preferably, the power-off test method further comprises:
and acquiring the preset alternating current test times or the preset direct current test times sent by the man-machine interaction module in advance.
Preferably, the processor is a baseboard management controller BMC of the server.
In order to solve the technical problem, the application also provides a power-off testing device, which is applied to a processor and comprises:
the control module is used for controlling the server to be powered off and turning over the enabling level of the enabling end of the standby power supply conversion chip of the server for a preset duration, so that the server is powered off for the preset duration and is powered on again;
the judging module is used for adding the tested times to judge whether the tested times reach the preset test times or not after the server is electrified, if not, the control module is triggered, and if so, the ending module is triggered;
and the ending module is used for ending the test.
Preferably, the turning preset duration of the enabling level of the enabling end of the standby power conversion chip of the server is specifically:
and sending a trigger pulse to the monostable delay circuit, so that the monostable delay circuit can overturn the enabling level sent to the enabling end of the standby power conversion chip in a steady state for a preset time.
In order to solve the technical problem, the application also provides a power-off test device, which comprises:
a memory for storing a computer program;
a processor for implementing the steps of the power down test method as claimed in any one of the preceding claims when executing the computer program.
According to the power-off test method, after the server is powered off, the BMC and the CPLD are still in the power-on state, so that the processor can control the server to be powered off and turn over the enabling level of the enabling end of the standby power conversion chip of the server for a preset time period, the BMC and the CPLD can be powered off completely, the power-off effect identical to that of alternating current power-off is achieved, and the BMC and the CPLD are powered on again when the preset time period is finished, the power-off test is circulated until the preset test times are achieved, the work of disconnecting and connecting the alternating current power supply is not needed to be repeated manually, the work efficiency is improved, and the labor cost is reduced.
The application also provides a power-off testing device and equipment, and the power-off testing device and equipment have the same beneficial effects as the power-off testing method.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required in the prior art and the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic flow chart of a power-off test method according to the present application;
fig. 2 is a schematic structural diagram of a server power supply system according to the present application;
FIG. 3 is a schematic diagram of a power failure testing apparatus according to the present application;
FIG. 4 is a schematic diagram of a power failure testing apparatus according to the present application;
fig. 5 is a schematic structural diagram of another power failure testing apparatus according to the present application.
Detailed Description
The core of the application is to provide a power-off test method, which does not need to repeatedly disconnect and connect the alternating current power supply manually, improves the working efficiency and reduces the labor cost; the application further aims to provide a power-off testing device and equipment, which do not need to repeatedly disconnect and connect an alternating current power supply manually, improve the working efficiency and reduce the labor cost.
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Referring to fig. 1, fig. 1 is a flow chart of a power-off testing method according to the present application, where the power-off testing method includes:
s11: the method comprises the steps of controlling the server to be powered off and turning over an enabling level of an enabling end of a standby power supply conversion chip of the server for a preset time period so that the server is powered off for the preset time period and powered on again;
in order to better explain the embodiments of the present application, please refer to fig. 2, fig. 2 is a schematic structural diagram of a server power supply system provided by the present application, and in particular, the core feature of the ac power failure is that the server is powered off and the standby portion (BMC (Baseboard Management Controller, baseboard management controller) and CPLD (Complex Programmable Logic Device )) in the server are powered down, but when the ac power supply is not disconnected, the standby power supply in the server is controlled to be powered off, the power-on states of the BMC and the CPLD are maintained, so that in order to automatically simulate the ac power-off state, the enabling level of the enabling end of the standby power conversion chip in the server can be turned over for a preset period of time after the server is controlled to be powered off, so that the server is thoroughly powered off (simulate ac power-off), and because the preset period of time is turned over, the enabling level is recovered after the preset period of time, the standby power conversion chip outputs electric energy again so that the BMC and the CPLD is powered on, and then the server is controlled to be powered on.
Specifically, in fig. 2, the main board of the server may adopt a power supply scheme as shown in fig. 2, where the AC power outputs 12v_stby direct current and 12v_mainpower direct current after passing through the power supply PSU. The 12v_stby generates other STBY electricity, such as 3v3_stby or 5v_stby, through a corresponding circuit, and these STBY electricity are all used to supply electricity to the CPLD and the BMC, and by sending a power-on or power-off command to the BMC, the BMC notifies the CPLD, and the CPLD controls the time sequence power-up and time sequence power-down of the 12 v_mainpower-down and other mainpower supplies. Functionally, STBY power is the most basic power for ensuring that the motherboard can be powered on normally from a standby state, and main power is used for ensuring normal operation of devices on the motherboard except for CPLD and BMC.
Wherein, the general DC power-off is to cut off the power of the main power source, and the STBY power is continuously. The AC power outage is to disconnect the external AC power, so that the mainpower, STBY power output by the PSU is disconnected altogether, so the idea of the application is to continue AC power on the left side of the PSU, but rather to disconnect mainpower, STBY power on the right side of the PSU. From the previous paragraph, if the STBY power is turned off, the CPLD and the BMC cannot work, and cannot power up the mainpower, that is, the mainpower depends on the STBY power, and the effect of replacing external AC power-on and power-off can be achieved by controlling the on-off of the STBY power.
Specifically, the 12V power output by PSU of the power supply of the server motherboard 12v_stby is controlled to be output as 12v_stby by through the standby power supply conversion chip VR, and the power supply chip is provided with an EN pin for controlling on/off of 12v_stby, when EN is high, VR is on, and when EN is low, VR is off. In the existing scheme, the input level of the pin is controlled to be a normally high level obtained by dividing the voltage of the 12V_PSU through a resistor, so that the EN is normally high as long as the PSU is inserted.
The preset time length can be set autonomously, and the standby power supply conversion chip cannot output electric energy within the preset time length, so that the BMC and the CPLD can complete the power-down process.
S12: after the server is powered on, the tested times are added together to judge whether the tested times reach the preset test times, if not, the S11 is returned, and if yes, the S13 is executed;
specifically, after the server is powered on, the test of one ac power failure can be considered to be completed, and since the purpose of the ac power failure test is that the server is not abnormal under the condition of multiple ac power failures, the ac power failure test generally has a preset number of tests, and the test can be ended after the number of tests reaches the preset number of tests, so that the step S11 can be returned when the preset number of tests is not reached, and the step S13 can be executed when the preset number of tests is reached so as to end the test.
The preset number of tests may be set autonomously, for example, may be 100 times, etc., which is not limited herein.
Specifically, after each time the server is powered on, a worker may detect the server to determine whether the server is abnormal due to ac outage, and may perform the detection according to the original detection flow, which is not limited herein.
S13: ending the test.
Specifically, the ending test means that the ac power-off test ends, and then the server can restore the original normal state.
Of course, the server may send a prompt to end the test through the prompter so that the staff member can learn, and the embodiment of the application is not limited herein.
Based on the above embodiments:
as a preferred embodiment, the preset duration for turning the enable level of the enable end of the standby power conversion chip of the server is specifically:
and sending a trigger pulse to the monostable delay circuit so that the monostable delay circuit can overturn the enabling level sent to the enabling end of the standby power conversion chip in a steady state for a preset period of time.
Specifically, the monostable delay circuit is in a stable state when no trigger pulse is received, and can send an enabling level to the enabling end of the standby power conversion chip, the enabling level cannot interfere with the original level state of the enabling end of the standby power conversion chip, namely, the enabling state is kept, and after the trigger pulse is received, the monostable delay circuit enters a temporary stable state, namely, the output level of the monostable delay circuit is overturned for a preset time period, so that the effect of controlling the standby power conversion chip to lose the energy for the preset time period is achieved.
The monostable delay circuit has the advantages of high stability, long service life, low price and the like.
Of course, besides the monostable delay circuit, other circuits may be used to implement control of turning the enable level of the enable end of the standby power conversion chip of the server for a preset period of time.
For better illustrating the embodiments of the present application, please refer to fig. 3, fig. 3 is a schematic structural diagram of a power-off testing device provided by the present application, as a preferred embodiment, a monostable delay circuit includes a first controllable switch T1, a second controllable switch T2, a power source, a monostable delay chip 555 and a peripheral circuit;
the control end of the first controllable switch T1 is connected with the processor, the first end of the first controllable switch T1 is respectively connected with a power supply and the input end of the monostable delay chip 555, the first end of the first controllable switch T1 is grounded, the power supply is connected with a power interface of the monostable delay chip 555, the output end of the monostable delay chip 555 is connected with the control end of the second controllable switch T2, the first end of the second controllable switch T2 is connected with the enabling end of the standby power conversion chip, and the second end of the second controllable switch T2 is grounded;
the peripheral circuit is used for setting the preset duration of the temporary steady state of the monostable delay chip 555;
wherein the enable level is high and the trigger pulse is high.
Specifically, in fig. 3, as shown in the parts consisting of the 12v_psu, R2, R3 and the 12v_stby module on the right side of fig. 3, R2 may be about 3 times of R3, so that the divided 3V is high, so as to ensure that the EN of the standby power conversion chip VR can be normally high as long as the PSU is plugged in, where we can choose R2 to be 42.2K and R3 to be 8.45K, so as to obtain a voltage of about 3.3V, and of course, different VRs require EN to be different in high level, and adjust the corresponding resistance value.
Specifically, the basic idea in the embodiment of the application is to control the delayed on-off of the VR chip EN pin by forming a monostable delay circuit by a 555 chip, and the specific composition can be as follows:
and the BMC and CPLD chips existing on the main board are utilized to form a basic logic control unit, and the BMC informs whether the CPLD is powered down or powered off and informs whether the CPLD is powered down by AC. When the CPLD judges that the normal shutdown (DC shutdown) is carried out, the original time sequence power-down logic is executed; when the CPLD judges that the AC power is turned off and the last main power is turned off according to the original power-off sequence, the CPLD outputs a high level to a 555 unit through a GPIO (General-purpose input/output interface) pin. As shown in fig. 3, the CPLD outputs a GPIO pin to the G (gate) electrode of T1, the S (source) electrode of T1 is grounded, and the D (drain) electrode is connected to the 5v_rtc power supply through the pull-up resistor R1 (5v_rtc refers to the power supplied by the 5V RTC battery, because when 12V_STBY mainpower is powered off, no other power exists on the motherboard, and an additional 5V battery is required to supply power to the 555 circuit). The drain electrode of the T1 is also connected to the input end of the 555 chip, when the GPIO of the CPLD is in a low level or high resistance state, the T1 is cut off, the 555 input is pulled high, and when the GPIO input is in a high level, the T1 is conducted, and the 555 input is pulled low. The monostable delay circuit formed by 555 is formed by a 555 chip, an RC circuit and a peripheral circuit thereof, and when the input is low, the output is low; when the input is high, the circuit is converted into transient state, and the output is high; when the input is low again, the output is low after a predetermined period of time. The preset time period is determined by the values of R and C in fig. 3:
T＝1.1RC
here we choose C to be 220uf and the preset time period T to be 20S, so r=t/1.1/c= 82.644K ohms, here we choose 80K ohms.
The output end of the 555 circuit is connected to the gate of T2, the source electrode of T2 is grounded, and the drain electrode is connected between R2 and R3. As mentioned above, when the GPIO signal sends a high level, the output end of the 555 circuit is instantaneously pulled high, at this time, T2 is turned on, the level between R2 and R3 is pulled low, VR disables EN, STBY of CPLD and BMC is powered down, GPIO pin of CPLD is pulled low or in a high resistance state, T1 is turned off, 555 input pin is pulled high again, that is, a low pulse signal is formed for 555, 555 output becomes high when receiving the falling edge of low pulse, pulling down again after 20S delay, that is, EN pin of VR is changed from low to high after 20S, and more directly, 12V_STBY is recovered after 20S. Thereby completing the 12v_stby power down process.
Specifically, because the condition of needing AC power off is not two kinds of conditions, one is to circularly switch on and off, namely, power on and power off are set for a fixed time, power off and power off are carried out after corresponding tests are run after power on, and then the steps are repeated; one is a single power-off, e.g., the firmware FW of the CPLD or BMC is burned out online, which takes effect after the AC power-off is restarted, which is only needed once.
The process related to the number of times of powering on and off the motherboard needs to be completed through cooperation of the BMC. The BMC can inform the CPLD of executing startup or shutdown by sending a chasis power on or a chasis power off to the BMC through the BMC serial port, and the sending chasis status can inquire whether the main board is in a power-on state or a power-off state. The input/output mode of the BMC gpio can be set by sending the gpiool number (66-set-dir-output, for example) to the BMC through the serial port, and whether the BMC gpio is high or low can be set by sending the gpiool number (66-set-data-low/high, for example), so as to inform the CPLD whether the AC is powered off. In addition, the times can be counted when AC or DC is circulated, and a man-machine interface written by C# is designed for the purpose of convenience and simplicity in operation.
Specifically, the monostable delay circuit provided by the embodiment of the application has the advantages of simple structure, low cost and short corresponding time.
Of course, besides the structure of the monostable delay circuit provided in the embodiment of the present application, the monostable delay circuit may be of other specific types, and the embodiment of the present application is not limited herein.
The first controllable switch T1 and the second controllable switch T2 may be of the same type, for example, MOS (Metal-Oxide-Semiconductor Field-Effect Transistor ) transistors, etc., which are not limited herein.
As a preferred embodiment, the method for controlling the server to be turned off and turning the enabling level of the enabling end of the standby power conversion chip of the server to a preset period of time specifically comprises:
responding to an alternating current power-off test instruction, controlling the server to be powered off and turning over the enabling level of the enabling end of the standby power supply conversion chip of the server for a preset period of time;
the power down test method further comprises:
responding to a direct current power-off test instruction, and controlling the power-on of the server after the power-off preset time;
after the main board is electrified, the accumulated test times of the direct current power failure are added together to judge whether the accumulated test times of the direct current power failure reach the preset direct current test times or not;
if not, returning to the step of powering on after controlling the server to be powered off for a preset time period in response to the direct current power-off test instruction;
the tested times are accumulated test times of alternating current power failure, and the preset test times are preset alternating current test times.
Specifically, in addition to the ac power-off test, the embodiment of the present application may also select to perform the dc power-off test, thereby improving the convenience and flexibility of the test, but only performing one of the tests at the same time.
The preset dc test times and the preset ac test times may be set independently, for example, the preset dc test times and the preset ac test times may be the same value, which is not limited herein.
As a preferred embodiment, after the accumulated ac power down test number is increased by one after the BMC is powered up, the power down test method further includes:
the control prompter prompts the alternating current power failure to accumulate the test times;
after the accumulated test times of the direct current power-off are increased by one after the main board is powered on, the power-off test method further comprises the following steps:
the control prompter prompts the accumulated test times of the direct current power failure.
Specifically, the accumulated test times can be conveniently and rapidly known by the staff through the prompt of the prompter.
The prompter may be of various types, for example, a display or a voice prompter, which is not limited herein.
As a preferred embodiment, the power-off test method further includes:
the method comprises the steps of obtaining preset alternating current test times or preset direct current test times sent by a man-machine interaction module in advance.
Specifically, in order to facilitate setting of the test times, in the embodiment of the application, a worker can conveniently send preset alternating current test times or preset direct current test times through the man-machine interaction module so as to set the test times, thereby improving the controllability of the test.
As a preferred embodiment, the processor is a baseboard management controller BMC of the server.
Specifically, the BMC is an original controller in the server, and can achieve the effects of saving cost and improving structural integrity.
Of course, the processor may be of various types other than BMC, and embodiments of the application are not limited in this regard.
Referring to fig. 4, fig. 4 is a schematic structural diagram of a power-off testing device provided by the present application, which is applied to a processor, and the power-off testing device includes:
the control module 1 is used for controlling the server to be powered off and turning over the enabling level of the enabling end of the standby power supply conversion chip of the server for a preset duration so that the server is powered off for the preset duration and is powered on again;
the judging module 2 is used for adding together the tested times after the server is powered on to judge whether the tested times reach the preset test times, if not, the control module is triggered, and if yes, the ending module is triggered;
and the ending module 3 is used for ending the test.
As a preferred embodiment, the preset duration for turning the enable level of the enable end of the standby power conversion chip of the server is specifically:
and sending a trigger pulse to the monostable delay circuit so that the monostable delay circuit can overturn the enabling level sent to the enabling end of the standby power conversion chip in a steady state for a preset period of time.
For the description of the power-off test device provided in the embodiment of the present application, reference is made to the foregoing embodiment of the power-off test method, and the embodiment of the present application is not repeated herein.
Referring to fig. 5, fig. 5 is a schematic structural diagram of another power-off testing apparatus provided by the present application, where the power-off testing apparatus includes:
a memory 4 for storing a computer program;
a processor 5 for implementing the steps of the power down test method in the previous embodiment when executing the computer program.
For the description of the power-off test device provided in the embodiment of the present application, reference is made to the foregoing embodiment of the power-off test method, and the embodiment of the present application is not repeated herein.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.
It should also be noted that in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (7)
1. A power down test method applied to a processor, comprising:
s11: the method comprises the steps of controlling a server to be powered off and turning over an enabling level of an enabling end of a standby power supply conversion chip of the server for a preset time period so that the server is powered off for the preset time period and powered on again;
s12: after the server is powered on, adding the tested times together to judge whether the tested times reach the preset test times, if not, returning to the step S11, and if so, executing the step S13;
s13: ending the test;
the enabling level of the enabling end of the standby power conversion chip of the server is turned over for a preset period of time specifically:
sending a trigger pulse to a monostable delay circuit so that the monostable delay circuit can overturn the enabling level sent to the enabling end of the standby power conversion chip in a steady state for a preset period of time;
the monostable delay circuit comprises a first controllable switch, a second controllable switch, a power supply, a monostable delay chip and a peripheral circuit;
the control end of the first controllable switch is connected with the processor, the first end of the first controllable switch is respectively connected with the power supply and the input end of the monostable time delay chip, the first end of the first controllable switch is grounded, the power supply is connected with the power supply interface of the monostable time delay chip, the output end of the monostable time delay chip is connected with the control end of the second controllable switch, the first end of the second controllable switch is connected with the enabling end of the standby power supply conversion chip, and the second end of the second controllable switch is grounded;
the peripheral circuit is used for setting the preset duration of the transient state of the monostable delay chip through the peripheral circuit;
wherein the enabling level is a high level, and the trigger pulse is a high level.
2. The power-off test method according to claim 1, wherein the control server is powered off and turns over the enable level of the enable end of the standby power conversion chip of the server for a preset period of time specifically:
responding to an alternating current power-off test instruction, controlling the server to be powered off and turning over the enabling level of the enabling end of the standby power supply conversion chip of the server for a preset period of time;
the power down test method further comprises:
responding to a direct current power-off test instruction, and controlling the server to be powered on after being powered off for a preset time period;
after the main board of the server is electrified, the accumulated test times of the direct current power failure are added together to judge whether the accumulated test times of the direct current power failure reach the preset direct current test times or not;
if not, returning to the step of controlling the power-on after the server is powered off for a preset time period in response to the direct current power-off test instruction;
the tested times are accumulated test times of alternating current power failure, and the preset test times are preset alternating current test times.
3. The power-down testing method according to claim 2, wherein after the number of times tested is increased by one after the server is powered up, the power-down testing method further comprises:
the control prompter prompts the alternating current power failure accumulated test times;
after the accumulated test times of the direct current power-off are increased by one after the main board of the server is powered on, the power-off test method further comprises the following steps:
and the control prompter prompts the direct current power failure accumulated test times.
4. A power down test method as defined in claim 3, further comprising:
and acquiring the preset alternating current test times or the preset direct current test times sent by the man-machine interaction module in advance.
5. The power down test method according to any one of claims 1 to 4, wherein the processor is a baseboard management controller BMC of the server.
6. A power down testing apparatus for use with a processor, comprising:
the control module is used for controlling the server to be powered off and turning over the enabling level of the enabling end of the standby power supply conversion chip of the server for a preset duration, so that the server is powered off for the preset duration and is powered on again;
the judging module is used for adding the tested times after the server is electrified to judge whether the tested times reach the preset test times or not, and if not, the control module is triggered;
the enabling level of the enabling end of the standby power conversion chip of the server is turned over for a preset period of time specifically:
sending a trigger pulse to a monostable delay circuit so that the monostable delay circuit can overturn the enabling level sent to the enabling end of the standby power conversion chip in a steady state for a preset period of time;
the monostable delay circuit comprises a first controllable switch, a second controllable switch, a power supply, a monostable delay chip and a peripheral circuit;
the control end of the first controllable switch is connected with the processor, the first end of the first controllable switch is respectively connected with the power supply and the input end of the monostable time delay chip, the first end of the first controllable switch is grounded, the power supply is connected with the power supply interface of the monostable time delay chip, the output end of the monostable time delay chip is connected with the control end of the second controllable switch, the first end of the second controllable switch is connected with the enabling end of the standby power supply conversion chip, and the second end of the second controllable switch is grounded;
the peripheral circuit is used for setting the preset duration of the transient state of the monostable delay chip through the peripheral circuit;
wherein the enabling level is a high level, and the trigger pulse is a high level.
7. A power outage testing apparatus comprising:
a memory for storing a computer program;
a processor for implementing the steps of the power down test method according to any one of claims 1-5 when executing the computer program.
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| CN114168393B (en) * | 2021-10-31 | 2023-11-21 | 苏州浪潮智能科技有限公司 | Server testing method, system, equipment and medium |
| CN114325481B (en) * | 2021-12-29 | 2023-10-31 | 深圳市欧瑞博科技股份有限公司 | Power-off duration detection method and device, electronic equipment and storage medium |
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