CN110858165B

CN110858165B - Chip set, chip set starting method and electronic equipment

Info

Publication number: CN110858165B
Application number: CN201810958865.7A
Authority: CN
Inventors: 彭石军; 吴剑锋; 李增山
Original assignee: Hangzhou Hikvision Digital Technology Co Ltd
Current assignee: Hangzhou Hikvision Digital Technology Co Ltd
Priority date: 2018-08-22
Filing date: 2018-08-22
Publication date: 2023-05-02
Anticipated expiration: 2038-08-22
Also published as: CN110858165A

Abstract

The embodiment of the invention provides a chip set, a chip set starting method and electronic equipment, wherein the chip set comprises a processor component, a singlechip, a first switch circuit and a starting controller, and the singlechip is connected with the processor component; the first switch circuit is respectively connected with the singlechip, the processor component and the zero potential point; the starting controller is respectively connected with the processor component and the singlechip; the singlechip and the processor component synchronously acquire a starting instruction sent by the starting controller. If the singlechip does not receive the preset information sent by the processor component within the preset time, the first switch circuit can be controlled to enable the reset port or pin of the processor component to be connected with the zero potential point. And the set CMOS information in the processor component is cleared, the CMOS information is restored to a default value, and related personnel are not required to manually operate, so that the efficiency is improved.

Description

Chip set, chip set starting method and electronic equipment

Technical Field

The present invention relates to the field of computer technologies, and in particular, to a chipset, a chipset starting method, and an electronic device.

Background

With the development of computer technology, from daily life to industrial production, intelligent devices such as computers and the like are increasingly required in various aspects. Therefore, reliability of intelligent devices such as computers is becoming more and more important.

In intelligent devices such as computers, various data can be processed and operated through a processor and various corresponding chip components, so that various functions are realized. In an intelligent device such as a computer, CMOS (Complementary Metal Oxide Semiconductor ) information is stored in an internal chip component, for example, a RAM (random access memory ) chip on a motherboard of the computer, where the CMOS information refers to basic information for starting the intelligent device such as a computer, such as date, time, start-up settings, and the like. CMOS information is a prerequisite for normal start-up and operation of intelligent devices such as computers. If the CMOS information is lost or improperly set, the light is not working properly, and the heavy is not started and working. Therefore, the CMOS information is correctly set and protected, and the CMOS information is very important to the safe use of intelligent devices such as computers and the like.

In the prior art, when an intelligent device such as a computer cannot be started normally, a chip storing CMOS information needs to be powered off by manual operation, for example, by removing a battery in a main board, so that the CMOS information set in the chip is cleared, and the CMOS information is restored to a default value. Therefore, when intelligent equipment such as a computer is started again, the intelligent equipment can be started normally. However, when the CMOS information in the chip is manually cleared, the efficiency is low, and the workload of related personnel is increased.

Disclosure of Invention

The embodiment of the invention aims to provide a chipset, a chipset starting method and electronic equipment, so that when a computer cannot be started normally, CMOS information in the chip is automatically cleared, and the CMOS information is restored to a default value, so that the computer can be started normally, related personnel are prevented from manually clearing the CMOS information, the efficiency is improved, and the workload of the related personnel is reduced. The specific technical scheme is as follows:

the embodiment of the invention provides a chip set, which comprises the following components:

a processor assembly;

the singlechip is connected with the processor component;

the first switch circuit is respectively connected with the singlechip, the processor component and the zero potential point, and is controlled by the singlechip to connect or disconnect the connection between the processor component and the zero potential point;

the starting controller is respectively connected with the processor component and the singlechip and is used for synchronously sending a starting instruction to the processor component and the singlechip;

after the processor component acquires the starting instruction, if the starting instruction is started normally, preset information is sent to the singlechip;

And if the singlechip acquires the starting instruction and does not receive the preset information within the preset time, the singlechip controls the first switch circuit to enable a reset port or pin of the processor component to be connected with the zero potential point through the first switch circuit, so that CMOS information in the processor component is cleared.

Optionally, the processor assembly includes: a processor chip and a north-south bridge chip;

the processor chip is connected with the north-south bridge chip;

the north-south bridge chip is respectively connected with the singlechip, the first switch circuit and the starting controller.

Optionally, the north-south bridge chip is a platform control hub PCH chip.

Optionally, the chipset further includes: an I/O chip;

the I/O chip is respectively connected with the processor component, the singlechip and the starting controller;

the starting controller sends the starting instruction to the I/O chip, and the I/O chip sends a starting signal to the processor component according to the starting instruction so that the processor component starts to start according to the starting signal.

Optionally, the first switch circuit includes a first MOS transistor;

The grid electrode of the first MOS tube is connected with the singlechip, and the source electrode and the drain electrode of the first MOS tube are respectively connected with the zero potential point and the processor component.

Optionally, the chipset further includes: a second switching circuit;

the second switch circuit is respectively connected with the singlechip, the processor component and a power supply, and the power supply supplies power to the processor component through the second switch circuit;

before the singlechip controls the first switch circuit to enable a reset port or pin of the processor component to be connected with the zero potential point through the first switch circuit, the singlechip controls the second switch circuit to enable the power supply to be disconnected with the processor component and stop supplying power to the processor component;

after the CMOS information in the processor component is cleared, the singlechip controls the second switch circuit to enable the power supply to be connected with the processor component, so that the processor component starts to start.

Optionally, the second switching circuit includes a second MOS transistor, or a DC-DC chip for converting DC into DC power, or a low dropout linear regulator LDO;

the grid electrode of the second MOS tube is connected with the singlechip, and the source electrode and the drain electrode of the second MOS tube are respectively connected with the power supply and the processor component;

Or the DC-DC chip or the enable pin of the LDO is connected with the singlechip, and the input end and the output end of the DC-DC chip or the LDO are respectively connected with the power supply and the processor component.

The embodiment of the invention also provides a method for starting the chip set, which is applied to the chip set of any one of the above steps, and comprises the following steps:

the processor component and the singlechip in the chipset synchronously acquire a starting instruction;

if the processor component is started normally, preset information is sent to the singlechip, wherein the preset information is used for indicating that the processor component is started normally;

if the singlechip does not receive the preset information within the preset time, the singlechip controls a first switch circuit to enable a reset port or pin of the processor component to be communicated with the zero potential point through the first switch circuit, and the CMOS information in the processor component is cleared;

after the CMOS information is cleared, the singlechip restarts the processor component.

Optionally, the single chip microcomputer controls the first switch circuit to enable the reset port or pin of the processor component to be connected with the zero potential point through the first switch circuit, and clears the CMOS information in the processor component, including:

The singlechip controls the first switch circuit to enable a reset port or pin of the processor component to be communicated with a zero potential point through the first switch circuit and keep a preset time period;

and clearing the CMOS information in the processor assembly within the preset time period.

Optionally, when the chipset includes an I/O chip, the processor component and the singlechip in the chipset synchronously acquire a start instruction, including:

the I/O chip and the singlechip synchronously acquire a starting instruction;

the I/O chip sends a starting signal to the processor component according to the starting instruction, and the processor component starts starting according to the starting signal;

if the processor component is started normally, sending preset information to the singlechip, wherein the method comprises the following steps:

if the processor component is started normally, the I/O chip sends the preset information to the singlechip.

Optionally, when the chipset includes a second switch circuit, before the singlechip controls the first switch circuit to enable a reset port or pin of the processor component to be connected with the zero potential point through the first switch circuit, the method further includes:

The singlechip controls the second switch circuit to disconnect the power supply from the processor assembly and stop supplying power to the processor assembly;

after the CMOS information is cleared, the singlechip restarts the processor assembly, and the method comprises the following steps:

after the CMOS information in the processor component is cleared, the singlechip controls the second switch circuit to enable the power supply to be connected with the processor component, so that the processor component is restarted.

The embodiment of the invention also provides electronic equipment, which comprises the chip set.

The embodiment of the invention provides a chipset, a chipset starting method and electronic equipment, wherein the chipset comprises a processor component, a singlechip, a first switch circuit and a starting controller, and the singlechip and the processor component synchronously acquire a starting instruction sent by the starting controller. If the singlechip does not receive preset information sent by the processor component within preset time, the processor component can be judged to be not started normally. The first switching circuit can be controlled so that the reset port or pin of the processor component is communicated with the zero potential point, the set CMOS information in the processor component is cleared, and the CMOS information is restored to a default value. After the CMOS information is restored to the default value, the processor assembly may be started up normally. In the embodiment of the invention, the automatic monitoring of the starting state of the processor component is realized through the singlechip, and when the starting is unsuccessful, the set CMOS information in the processor component is automatically cleared, and the CMOS information is restored to the default value. The operation is not needed by related personnel manually, the efficiency is improved, and the workload of the related personnel is reduced. Of course, it is not necessary for any one product or method of practicing the invention to achieve all of the advantages set forth above at the same time.

Drawings

In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a first block diagram of a chipset according to an embodiment of the present invention;

FIG. 2 is a second block diagram of a chipset according to an embodiment of the present invention;

FIG. 3 is a third block diagram of a chipset according to an embodiment of the present invention;

fig. 4 is a flowchart of a method for starting a chipset according to an embodiment of the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Referring to fig. 1, fig. 1 is a first block diagram of a chipset according to an embodiment of the present invention, where the first block diagram includes:

a processor assembly 101. The processor assembly 101 is a chip set including a processor chip, and may include, for example, a conversion chip or a connection chip for implementing data transmission between the data processor and other hardware units, and a corresponding support circuit. In practical applications, the processor chip set under the X86 system or other series of processor chip sets can be used. The processor assembly 101 may be integrated on an integrated circuit board and may be configured to correspond to a motherboard in a computer. In the processor assembly 101, CMOS information may be stored. For example, CMOS information is stored in a RAM chip in the processor assembly 101. The CMOS information can be set, but the problem that the hardware device cannot be started normally is caused when the setting is wrong. When the chip storing the CMOS information is reset, the set CMOS information is cleared and restored to the default CMOS information, such as the default value when shipped.

The singlechip 102, singlechip 102 is connected with processor module 101. The single chip 102 is an embedded microcontroller, which may also be referred to as an MCU (micro control unit) (Micro Control Unit), and is an integrated circuit chip. The microcomputer system is a small and perfect microcomputer system which is formed by integrating functions of CPU, RAM, ROM (Read-Only Memory), various I/O ports, interrupt systems, timers/counters and the like with data processing capacity on a silicon chip by adopting a very large scale integrated circuit technology.

The single chip 102 may be integrated with the processor assembly 101 on an integrated circuit board and interconnected by printed wiring on the integrated circuit board to enable transmission of data information and signals, etc. Alternatively, the single chip 102 and the processor assembly 101 may be disposed on different integrated circuit boards, and may be connected to each other by a data bus, a cable, and various data interfaces.

The first switch circuit 103, the first switch circuit 103 is connected with the singlechip 102, the processor component 101 and the zero potential point respectively. The first switching circuit 103 is a circuit or element having a switching function. The first switch circuit 103 can switch on or off the connection between the processor assembly 101 and the zero potential point under the control of the single chip microcomputer 102. The zero potential point may be a ground point, or in some cases, a negative power supply.

When connected to the processor assembly 101, the first switch circuit 103 may be directly connected to a reset port or pin of the processor assembly 101, or may be connected to a reset port or pin of the processor assembly 101 through other elements such as a resistor, a reactance, or the like. When the reset port or pin of the processor assembly 101 is connected to the zero potential point, the chip in the processor assembly 101 storing the CMOS information can be reset, so that the CMOS information is restored to default.

Specifically, the first switch circuit 103 may have various structural forms, and any electronic component or circuit capable of realizing the above functions may be used as the first switch circuit 103, for example, a small relay, a micro switch, or the like. In the embodiment of the invention, in order to simplify the structure, the cost is reduced. Preferably, the first switching circuit 103 may include: comprising a first MOS (Metal-Oxide-Semiconductor) tube. The first MOS tube is provided with three terminals, namely a grid electrode, a source electrode and a drain electrode. The grid is a control end, and the on-off between the source electrode and the drain electrode can be controlled by applying different levels on the grid.

The grid of the first MOS tube is connected with the singlechip 102, and the source electrode and the drain electrode of the first MOS tube are respectively connected with the zero potential point and the processor component 101.

The port or pin of the singlechip 102 may be connected to the gate of the first MOS transistor, and may output different levels to the gate, so that the zero potential point connected to the source and the drain may be turned off or turned on between the processor component 101 and the zero potential point. The drain of the first MOS transistor may be connected to a reset pin or port in the processor assembly 101, and the source is connected to a zero potential point. The reset pin or port of the processor component 101 can be connected with a zero potential point under the control of the singlechip 102, so that the CMOS information is cleared, and the CMOS information is restored to a default value. Of course, in practical application, when the first MOS transistor is connected, various electronic elements such as a capacitor and a resistor may be further included, and the first MOS transistor is connected to the singlechip 102, the processor component 101 and the zero potential point through various electronic elements, and a specific circuit may be designed according to actual needs, which is not limited herein.

And the starting controller 104 is respectively connected with the processor component 101 and the singlechip 102, and is used for synchronously sending starting instructions to the processor component 101 and the singlechip 102.

The start controller 104 may be a button, switch, pulse switch, or the like. The start controller 104 may be capable of issuing a start command under personnel operation, for example, when a pulse switch is pressed. The start command may be an electrical signal in the form of a pulse, for example, a low level signal.

The processor component 101 and the singlechip 102 are connected with the start controller 104, specifically, can be connected through a cable or a printed circuit on an integrated circuit board, so that after the start controller 104 sends a start instruction, the processor component 101 and the singlechip 102 can synchronously acquire the start instruction.

After the processor assembly 101 obtains the start-up instruction, start-up may be started, for example, power is turned on, so that each chip in the processor assembly 101 is powered up.

After the processor component 101 obtains the start instruction, if the start instruction is normal, the preset information is sent to the singlechip 102. The preset information may be a preset electrical signal, for example, an electrical signal having a preset waveform. The preset information is used to inform the singlechip 102 that the processor component 101 has been started normally, and the singlechip 102 is not required to execute subsequent steps.

If the singlechip 102 does not receive the preset information within the preset time after acquiring the start instruction, the singlechip 102 controls the first switch circuit 103 to enable the reset port or pin of the processor component 101 to be connected with the zero potential point through the first switch circuit 103, so as to clear the CMOS information in the processor component 101. The preset time can be set according to the needs, for example, 1s,2s and the like.

After the singlechip 102 obtains the starting instruction, the internal timer can start timing, and whether preset information sent by the processor component 101 is received or not is monitored in real time. If the preset information is not received within the preset time, it may be considered that the processor assembly 101 is not able to start up normally. The CMOS information in the processor assembly 101 needs to be purged. Therefore, the singlechip 102 may control the first switch circuit 103, for example, apply a high level to the gate of the first MOS transistor, so as to turn on the source and the drain of the first MOS transistor. Such that the reset port or pin of the processor assembly 101 is brought into contact with the zero potential point. Thereby clearing the set CMOS information in the processor assembly 101 and restoring the CMOS information to a default value. In addition, in order to ensure that the CMOS information is cleared, the single-chip microcomputer 102 may keep the high level applied to the gate of the first MOS transistor for a preset period of time, for example, 2s, so as to ensure that the reset port or pin of the processor component 101 is fully connected with the zero potential point, so that the chip in the processor component 101 storing the CMOS information is fully reset, and further ensure that the CMOS information is cleared.

In the embodiment of the present invention, the singlechip 102 and the processor component 101 synchronously acquire the start command sent by the start controller 104. If the singlechip 102 does not receive the preset information sent by the processor component 101 within the preset time, it may be determined that the processor component 101 cannot be started normally. The first switching circuit 103 may thus be controlled such that the reset port or pin of the processor assembly 101 is brought into contact with the zero potential point. Thereby clearing the set CMOS information in the processor assembly 101 and restoring the CMOS information to a default value. After restoring the CMOS information to the default value, the processor assembly 101 may be started up normally. In the embodiment of the invention, the singlechip 102 is used for realizing automatic monitoring of the starting state of the processor component 101, and when the starting is unsuccessful, the set CMOS information in the processor component 101 is automatically cleared, and the CMOS information is restored to a default value. The operation is not needed by related personnel manually, the efficiency is improved, and the workload of the related personnel is reduced.

Referring to fig. 2, in an embodiment of the present invention, in order to enable the processor assembly 101 to operate more stably, the versatility of the processor assembly 101 is improved. The processor assembly 101 may include: a processor chip 201 and a north-south bridge chip 202.

The processor chip 201 may be a chip having data processing capability, such as a CPU or the like.

The north-south bridge 202 is primarily responsible for communication between I/O buses, such as PCI (Peripheral Component Interconnect, peripheral component interconnect standard) buses, USB, SATA (Serial Advanced Technology Attachment ), audio controllers, keyboard controllers, real time clock controllers, advanced power management, and control of the processor chip 201 and memory, among others. The north-south bridge 202 includes a chip for storing CMOS information.

In an embodiment of the present invention, specifically, the north-south bridge 202 may be a PCH (Platform Controller Hub, platform control hub) chip. The PCH chip may provide a controller of a common interface such as PCIE (peripheral component interconnect express, high-speed serial computer expansion bus standard), SATA, USB, etc., so that the processor chip 201 can implement data transmission through the above interface. Compared with the traditional north-south bridge chip, the PCH chip has higher integration level and faster transmission efficiency, and is beneficial to the stable work of the chip set provided by the embodiment of the invention.

The processor chip 201 is connected to the north-south bridge chip 202. The processor chip 201 and the north-south bridge chip 202 may be integrated on an integrated circuit board so as to be connected to each other by printed wiring on the circuit board to enable transmission of data and signals therebetween. Alternatively, the processor chip 201 and the north-south bridge chip 202 may be integrated on a single chip, and connected to each other by a connection line inside the chip, so as to realize data and signal transmission between each other.

The north-south bridge chip 202 is respectively connected with the singlechip 102, the first switch circuit 103 and the start controller 104.

The north-south bridge chip 202 is used for receiving and transmitting various control signals, and based on the various control signals, the auxiliary processor chip 201 performs corresponding data processing work. In embodiments of the present invention, the booting of processor chipset 101 may be implemented primarily by north-south bridge 202.

Therefore, the north-south bridge 202 may be connected to the above components by printed wiring on an integrated circuit board, or by a data bus, a cable, or the like. The reset port or pin of the north-south bridge chip 202 is connected to the first switch circuit 103, for example, the rtcrst# pin of the PCH chip is connected to the first switch circuit 103.

The north-south bridge 202 can acquire a start command sent by the start controller 104, and then start to start the processor chipset 101, and if the start is successful, send preset information to the singlechip 102. If the singlechip 102 does not receive the preset information within the preset time, the first switch circuit 103 is controlled so that the reset port or pin of the north-south bridge chip 202 is connected to the zero potential point, for example, the rtcrst# pin of the PCH chip is connected to the zero potential point, and the CMOS information set in the PCH is restored to the default value.

In combination with the foregoing embodiments, in practical applications, in order to improve the efficiency of data transmission between the processor component 101 and other components in the chipset according to the embodiments of the present invention. Referring to fig. 3, the chip set provided in the embodiment of the present invention may further include: I/O chip 301. The I/O chip 301 is also called Super IO, and is an I/O control circuit capable of providing serial and parallel interfaces, a floppy disk drive, and a control interface such as a keyboard and a mouse.

The I/O chip 301 is connected to the processor assembly 101, the singlechip 102, and the start controller 104, respectively.

The I/O chip 301 may be integrated with the processor assembly 101, the singlechip 102, the start controller 104, etc. on an integrated circuit board, so that connection with each element may be implemented through a printed circuit on the integrated circuit board, or may also be connected through a cable, a data bus, etc. When the processor assembly 101 includes the processor chip 201 and the north-south bridge chip 202, the I/O chip 301 may be connected to the processor chip 201 and the north-south bridge chip 202, respectively, or may be connected to the north-south bridge chip 202, and data transmission with the processor chip 201 may be implemented through the north-south bridge chip 202.

The I/O chip 301 is connected to the start controller 104, and may receive a start command sent from the start controller 104 to the I/O chip 103. For example, the PSIN# pin of I/O chip 301 receives a low signal from enable controller 104, which may be an enable instruction.

The I/O chip 103 sends a start signal to the processor component 101 according to the start command, and the processor component 101 starts to start according to the start signal after receiving the start signal. The start signal may be in the form of a pulsed current, or a control command, etc. For example, the I/O chip 103 outputs a low signal to the processor assembly 101 via the psout# pin, which may be used as a start signal.

The I/O chip 301 is connected to the single chip 102, and the I/O chip 301 can monitor the boot process of the processor assembly 101. If the processor component 101 is started normally, the I/O chip 301 may send preset information to the singlechip 102, so that the processor component 101 is not required to send preset information to the singlechip 102, and the workload of the processor component 101 is reduced.

In connection with the above embodiments, when the processor assembly 101 is started normally, the power supply needs to be turned on, so that the processor assembly 101 is powered up normally to start up normally. When the reset port or pin of the processor assembly 101 is connected to the zero potential point, the connection between the processor assembly 101 and the power supply needs to be disconnected, so that a short circuit fault is avoided.

Therefore, as shown in fig. 3, the chipset provided in the embodiment of the present invention further includes: a second switching circuit 302.

The second switch circuit 302 is respectively connected to the singlechip 102, the processor assembly 101 and a power supply, and the power supply supplies power to the processor assembly 101 through the second switch circuit 302.

The second switching circuit 302 is similar to the first switching circuit 103, and is a circuit or element having a switching function. The processor assembly 101 is connected to a power source through the second switch circuit 302, specifically, may be connected by a cable or the like, so as to implement power transmission. The power source may be a power source device with a voltage regulating function, which can convert a voltage into an operating voltage of an element, such as 3.3V, or may be a built-in power source, such as a battery, which can directly provide an operating voltage for an element, such as the processor assembly 101.

When the processor assembly 101 receives a start instruction or a start signal, the second switch circuit 302 is capable of switching on the connection between the processor assembly 101 and the power source, so that the processor assembly 101 starts to power up and start.

If the processor assembly 101 is not normally started, the singlechip 102 controls the first switch circuit 103 to enable the reset port or pin of the processor assembly 101 to be connected with the zero potential point through the first switch circuit 103. The singlechip 102 firstly controls the second switch circuit 302 to disconnect the power supply from the processor assembly 101 and stop supplying power to the processor assembly 101.

The second switching circuit 302 may switch on or off the connection between the processor assembly 101 and the power supply under the control of the single-chip microcomputer 102. To avoid a short circuit fault, the singlechip 102 first controls the second switch circuit 302 to disconnect the processor assembly 101 from the power supply. Then, the first switch circuit 103 is controlled to connect the reset port or pin of the processor component 101 with the zero potential point, so as to restore the CMOS information to the default value.

Specifically, the second switching circuit 302 may include a second MOS transistor, or a DC-DC (direct current to direct current) chip, or an LDO (low dropout regulator, low dropout linear regulator).

When the second switch circuit 302 includes a second MOS transistor, the gate of the second MOS transistor is connected to the single chip microcomputer 102, and the source and the drain of the second MOS transistor are respectively connected to the power supply and the processor component 101.

Because the second MOS tube has good conduction capability and good controllability, the control by the singlechip 102 can be realized more conveniently. For example, the second MOS transistor is always in a conductive state during the starting process of the processor component 101, and when the CMOS information needs to be cleared, the singlechip 102 may reduce the level of the gate of the second MOS transistor, so that the source and the drain are not conductive any more, and thus the connection between the power supply and the processor component 101 is disconnected. In practical application, the second MOS transistor may further include various electronic elements such as a capacitor and a resistor when connected, and the specific circuit may be designed according to actual needs by connecting the various electronic elements with the singlechip 102, the processor component 101 and the power supply, which is not particularly limited herein.

When the second switch circuit 302 includes a DC-DC chip or LDO, an enable pin of the DC-DC chip or LDO is connected to the single chip 102, and an input terminal and an output terminal of the DC-DC chip or LDO are connected to the power supply and the processor assembly 101, respectively.

The DC-DC chip may convert a fixed direct voltage to a variable direct voltage, also known as a direct current chopper. The DC-DC chip can comprise a hard switch, a soft switch and the like, and can realize the on-off of a circuit in different modes.

LDOs are linear regulators that use transistors or FETs operating in their linear region to subtract excess voltage from the applied input voltage, producing a regulated output voltage.

The DC-DC chip and the LDO have the functions similar to those of the MOS tube, and the on-off between the input end and the output end of the DC-DC chip and the LDO can be controlled through enabling pins of the DC-DC chip and the LDO.

Therefore, when the enabling pin of the DC-DC chip or LDO is connected to the single-chip microcomputer 102, and the input end and the output end of the DC-DC chip or LDO are respectively connected to the power supply and the processor component 101, the on-off between the power supply and the processor component 101 can be realized under the control of the single-chip microcomputer 102. For example, when CMOS information needs to be cleared, the singlechip 102 may control the enable pin of the DC-DC chip or LDO, so that the power supply and the processor component 101 are not turned on any more, and the power supply and the processor component 101 are disconnected.

In the embodiment of the present invention, after the CMOS information in the processor assembly 101 is cleared, the singlechip 102 controls the second switch circuit 302 to connect the power supply to the processor assembly 101, so that the processor assembly 101 starts to be started.

After the CMOS information in the processor assembly 101 is cleared, the singlechip 102 first controls the first switch circuit 103 such that the reset port or pin of the processor assembly 101 is no longer conductive to the zero potential point. Then, the second switching circuit 302 is controlled again to switch on the power supply and the processor assembly 101 again, so that the processor assembly 101 restarts. An automatic restart of the processor assembly 101 is achieved such that the entire startup process is fully automated.

Referring to fig. 4, fig. 4 is a flowchart of a chipset starting method according to an embodiment of the present invention, where the chipset starting method can be applied to any one of the above-mentioned chipsets, and by using the chipset starting method, the above-mentioned chipsets can automatically clear CMOS information when the starting is unsuccessful, restore the CMOS information to a default value, and automatically restart. The manual operation of related personnel is avoided, and the efficiency is improved. The method for starting the chip set comprises the following steps:

in step 410, the processor component and the singlechip in the chipset synchronously acquire the start instruction.

In the chipset, after the start controller triggers the start instruction, for example, the start controller is a start button, and when the user presses the start button, the start instruction is triggered. The starting instruction can be synchronously sent to the connected processor component and the singlechip, so that the processor component and the singlechip synchronously acquire the starting instruction.

Step 420, if the processor component is started normally, preset information is sent to the singlechip, where the preset information is used for indicating that the processor component is started normally.

After the processor assembly obtains the start-up instruction, the processor assembly may start to start, for example, power on, so that each chip in the processor assembly is powered on. If the start-up is successful, the processor component may send preset information to the singlechip, which may be a preset electrical signal, for example, an electrical signal having a preset waveform. If the singlechip receives the preset information, the singlechip indicates that the processor component is started normally, and the singlechip is not required to execute subsequent steps.

In step 430, if the singlechip does not receive the preset information within the preset time, the singlechip controls the first switch circuit, so that the reset port or pin of the processor component is connected with the zero potential point through the first switch circuit, and the CMOS information in the processor component is cleared.

After the singlechip acquires the starting instruction, the singlechip can start timing through an internal timer and monitor whether preset information sent by the processor component is received or not in real time. If the preset information is not received within the preset time, the processor component is considered to be unable to start normally. The CMOS information stored in the processor assembly needs to be purged. The preset time can be set according to the needs, for example, 1s,2s and the like.

Specifically, the singlechip may control the first switch circuit, for example, when the first switch circuit is a first MOS transistor, a high level may be applied to the gate of the first MOS transistor, so that the source and the drain of the first MOS transistor are turned on. Such that the reset port or pin of the processor assembly is brought into communication with the zero potential point. Thereby clearing the saved CMOS information in the processor assembly and restoring the CMOS information to a default value.

In addition, in order to fully ensure that the CMOS information can be cleared, in the embodiment of the present invention, in the practical application, step 430, if the singlechip does not receive the preset information within the preset time, the singlechip controls the first switch circuit, so that the reset port or pin of the processor component is connected with the zero potential point through the first switch circuit, and clearing the CMOS information in the processor component may include:

In step 430a, the singlechip controls a first switch circuit in the processor assembly, so that a reset port or pin of the processor assembly is connected with a zero potential point through the first switch circuit, and the preset duration is maintained.

Step 430b, clearing the CMOS information in the processor assembly for a predetermined period of time.

The preset time length can be set according to the needs, and can be generally 2s, 3s and the like. The reset port or pin of the processor assembly is held on with the zero potential point for a preset period of time. Therefore, the reset port or pin of the processor component and the zero potential point can be kept in a connection state for a certain period of time, so that the chip in the processor component 101, which is stored with the CMOS information, is fully reset, the CMOS information is further ensured to be cleared, and the problem that the CMOS information is not completely cleared due to the short reset time is avoided.

Step 440, after the CMOS information is cleared, the single chip computer restarts the processor assembly.

After the stored CMOS information in the processor assembly is cleared, the processor assembly may be restarted under the control of the single chip microcomputer. Specifically, the singlechip may control the power supply connected to the processor assembly, so that the power supply is turned on again with the processor assembly, or the power supply supplies power to the processor assembly again, so that the processor assembly is started to restart automatically.

In combination with the foregoing embodiment, optionally, in the method for starting a chipset according to the embodiment of the present invention, when the chipset includes an I/O chip, step 410 may include that a processor component and a singlechip in the chipset synchronously acquire a starting instruction:

in step 410a, the I/O chip and the singlechip synchronously acquire a starting instruction.

When an I/O chip is included in the chipset, then the processor assembly may boot under the control of the I/O chip such that the processor assembly does not need to be directly connected to the boot controller. The starting process of the processor component is more stable.

Because the I/O chip and the singlechip are connected with the starting controller, the starting instruction sent by the starting controller can be synchronously acquired. For example, the PSIN# pin of the I/O chip receives a low level signal from the start controller, which may be a start command.

In step 410b, the I/O chip sends a start signal to the processor assembly according to the start instruction, and the processor assembly starts to start according to the start signal.

After the I/O chip has acquired the boot instructions, a boot signal may be sent to the processor assembly. The start signal may be in the form of a pulsed voltage or a control command, etc. For example, the I/O chip may output a low signal to the processor assembly via the PSOUT# pin, which may be used as a start signal.

Correspondingly, in step 420, if the processor component is started normally, the preset information is sent to the singlechip, including:

The I/O chip is connected with the singlechip and can monitor the starting process of the processor component. If the processor component is started normally, the I/O chip can send preset information to the singlechip, so that the processor component is not required to send the preset information to the singlechip, and the workload of the processor component is reduced.

In combination with the foregoing embodiment, optionally, in the method for starting a chipset according to the embodiment of the present invention, when the chipset includes the second switch circuit, in step 430, the singlechip controls the first switch circuit to enable the reset port or pin of the processor component to be connected to the zero potential point through the first switch circuit, and before the method further includes:

in step 421, the singlechip controls the second switch circuit to disconnect the power supply from the processor assembly and stop supplying power to the processor assembly.

The second switch circuit is respectively connected with the singlechip, the processor component and a power supply, and the power supply supplies power to the processor component through the second switch circuit. During the starting process of the processor component, the power supply is in a conducting state with the processor component through the second switch circuit. The processor assembly can be powered to cause the processor assembly to boot. The second switch circuit can be controlled by the singlechip to connect or disconnect the connection between the processor component and the power supply. For example, after the singlechip acquires the starting instruction, the second switch circuit can be controlled to enable the connection between the processor component and the power supply to be in a conducting state, so that the processor component can start starting according to the starting instruction or the starting information.

If the processor component is not started normally, the singlechip controls the first switch circuit to enable the reset port or pin of the processor component to be communicated with the zero potential point through the first switch circuit. In order to avoid short circuit faults, the singlechip firstly controls the second switch circuit to disconnect the processor component from the power supply. And then controlling the first switching circuit to connect the reset port or pin of the processor component with the zero potential point, clear the CMOS information and restore to the default value.

Accordingly, in step 404, after the CMOS information is cleared, the single-chip microcomputer restarts the processor component, including:

after the CMOS information in the processor component is cleared, the singlechip controls the second switch circuit to connect the power supply with the processor component, so that the processor component is restarted.

After the CMOS information in the processor component is cleared, the singlechip firstly controls the first switch circuit, so that the reset port or pin of the processor component is not conducted with the zero potential point. The second switching circuit is then controlled to turn on the power supply and the processor assembly again, so that the processor assembly restarts. And further, the automatic restarting of the processor component is realized, so that the whole starting process completely realizes the automatic operation.

The electronic equipment provided by the embodiment of the invention can be intelligent equipment with data processing capability, such as computers, notebook computers, rack-mounted servers and the like. The chip set can be integrated in a main board of the computer or can be connected with the main board as an independent component, so that the electronic equipment provided by the embodiment of the invention can automatically clear CMOS information and realize automatic restarting when the starting is unsuccessful.

It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

In this specification, each embodiment is described in a related manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments.

The foregoing description is only of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A chipset, comprising:

a processor assembly;

the singlechip is connected with the processor component;

2. The chipset of claim 1 wherein the processor component comprises: a processor chip and a north-south bridge chip;

the processor chip is connected with the north-south bridge chip;

3. The chipset of claim 2, wherein the north-south bridge chip is a platform control hub PCH chip.

4. The chipset of claim 1, further comprising: an I/O chip;

5. The chipset of claim 1, wherein the first switching circuit comprises a first MOS transistor;

6. The chipset of claim 1, further comprising: a second switching circuit;

7. The chipset of claim 6, wherein the second switching circuit comprises a second MOS transistor, or a DC-DC chip for DC-DC power supply, or a low dropout linear regulator LDO;

8. A chipset activation method, characterized in that the method is applied in a chipset according to any of the claims 1 to 7, the method comprising:

9. The method of claim 8, wherein the single-chip microcomputer controls a first switch circuit to enable a reset port or pin of the processor assembly to be connected with the zero potential point through the first switch circuit, and clearing CMOS information in the processor assembly comprises:

10. The method of claim 8, wherein when the chipset includes an I/O chip, the processor component and the single-chip microcomputer in the chipset synchronously acquire the start instruction, comprising:

the I/O chip and the singlechip synchronously acquire a starting instruction;

11. The method of any of claims 8 to 10, wherein when a second switching circuit is included in the chipset, before the singlechip controls the first switching circuit to cause a reset port or pin of the processor assembly to be turned on with the zero potential point through the first switching circuit, the method further comprises:

12. An electronic device, characterized in that it comprises a chipset according to any of the claims 1 to 7.