CN102221864A - Computer, and computer startup management system and method thereof - Google Patents
Computer, and computer startup management system and method thereof Download PDFInfo
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- CN102221864A CN102221864A CN2010101474191A CN201010147419A CN102221864A CN 102221864 A CN102221864 A CN 102221864A CN 2010101474191 A CN2010101474191 A CN 2010101474191A CN 201010147419 A CN201010147419 A CN 201010147419A CN 102221864 A CN102221864 A CN 102221864A
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Abstract
The invention relates to a computer, and a computer startup management system and method thereof. The computer startup management system comprises a control module, a timing circuit, a switching circuit and a complementary metal oxide semiconductor (CMOS) clearing circuit, wherein the control circuit is in a basic input/output system (BIOS) and outputs a first control signal through a general purpose input/output (GPIO) interface, and the first control signal is at a first level in startup and triggered into a second level when the BIOS definitely can normally finish running is determined by the setting of the first control signal; the timing circuit is used for receiving the first control signal, timing and outputting a second control signal when the first control signal is still kept at the first level till the first predetermined time TH; the switching circuit is used for immediately switching off a main board power supply when the second control signal is received; and the CMOS clearing circuit is used for constantly lowering real time clock reset (RTC RST) signals at a third predetermined time TJCC period when the second control signal is received and after a second predetermined time TD is delayed so as to clear CMOS. By implementing the system and the method, the CMOS setting of the last normal startup can be automatically recovered without any manual operation or intervention, and the system is restarted.
Description
Technical field
The present invention relates to computing machine, more particularly, relate to a kind of computer booting and start management system, comprise the method that this computer booting starts the computing machine of management system and carry out starting up's management in computing machine.
Background technology
CMOS (refers to preserve basic log-on message of computing machine such as date, time, start the chip be provided with etc., it is a read-write RAM chip on the mainboard, be to be used for preserving the hardware configuration of BIOS and user setting to some parameter) reference record computing machine important resource configuration parameter, incorrect CMOS parameter is provided with, may cause computing machine normally to start, at this moment need manually clear CMOS that computing machine is normally started, the step of manually clear CMOS: 1., cut off host power supply, 2., the lithium battery or the clear CMOS of short circuit that take off to CMOS power supply jump cap, and wherein the 2. the step need be opened cabinet and operated on computer motherboard.But the client does not often know and can allow computing machine normally start by manually clear CMOS, usually reports computer failure by mistake, increases the customer service cost of computer vendors.In addition, industrial computer is not easy to assemble in industry spot, needs again to reset the CMOS parameter behind the intact clearly CMOS, causes the mode of manually clear CMOS both inconvenient, operates and more complicated.
The patent No. of on October 19th, 2005 bulletin is to disclose the real-time clock feed circuit that a kind of CMOS of removing is provided with in the Chinese utility model patent instructions of ZL 200420077943.6.The button that to remove CMOS in the scheme of this utility model is placed on the outside surface of cabinet, for the user has brought convenience.Though this patent need not be opened cabinet when clear CMOS, still need manually clear CMOS, and also need to reset after finishing clearly.
Summary of the invention
The technical problem to be solved in the present invention is that the defective at the manually clear CMOS of above-mentioned needs of prior art makes the normal startup of computing machine provides a kind of computer booting to start management system.
Another technical matters that the present invention will solve is that manual clear CMOS makes the normal defective that starts of computing machine at the above-mentioned needs of prior art, and a kind of computing machine is provided, and it can manage the starting up.
The another technical matters that the present invention will solve is that the defective at the manually clear CMOS of above-mentioned needs of prior art makes the normal startup of computing machine provides a kind of computer booting to start management method.
The technical solution adopted for the present invention to solve the technical problems is: construct a kind of computer booting and start management system, comprising:
Be included in the control module in the basic input/output (BIOS), it exports first control signal by general input/output interface, described first control signal be arranged so that when start the time be first level, and confirm that it is second level that the normal surely operation of BIOS one triggers when finishing;
Timing circuit, it receives described first control signal and timing, if up to first schedule time TH, described first control signal still remains first level, then exports second control signal;
On-off circuit, it is connected in described timing circuit, and disconnects motherboard power supply immediately when receiving described second control signal;
Clear cmos circuit, it is connected in described timing circuit, and postpone second schedule time TD when receiving described second control signal after, continues to drag down the reset pin signal of CMOS to remove CMOS during the 3rd schedule time TJCC;
Wherein, described first schedule time TH is greater than the required time of the power-on self-test of described computing machine, described second schedule time TD thoroughly exhausts required time more than or equal to the south bridge power supply of mainboard outage back, and described the 3rd schedule time TJCC removes the required time of CMOS more than or equal to finishing.
Start in the management system at computer booting of the present invention, comprise nonvolatile random access memory, store last effectively BIOS configuration information on it; Wherein, after finishing CMOS and removing, described control module is used effective BIOS of the described last time that is stored in the described nonvolatile random access memory to be provided with to restart described computing machine.
Start in the management system at computer booting of the present invention,, then close described computer booting and start management system if described first control signal becomes second level from first level in first schedule time TH.
Start in the management system at computer booting of the present invention, described timing circuit comprises 555 triggers and booting wait time adjusting circuit; Wherein, the triggering input pin of described 555 triggers link to each other with the thresholding input pin so that its as oscillator work, the high level lasting time of output pin output square wave is described first schedule time T
HDescribed booting wait time adjusting circuit is used to set described first schedule time T
H
Start in the management system at computer booting of the present invention, described on-off circuit comprises second switch device (Q2) and first switching device (Q1) that is controlled by described second control signal, is respectively applied for the on/off of electric power starting (PS_ON) signal between control ATX power supply and the motherboard power supply interface and the on/off of standby (SB) voltage that the ATX power supply provides to mainboard.
Start in the management system at computer booting of the present invention, described clear cmos circuit comprises delay circuit, Schmidt's (SCHMITT) trigger and the 5th switching device (Q5); Wherein, described delay circuit is used for described second control signal delayed time and is sent to described SCHMITT trigger behind second schedule time TD, described SCHMITT trigger produces the pulse that is used to control described the 5th switching device, drags down to realize CMOS reset pin signal; The duration of described pulse is the 3rd schedule time T
JCC
Another technical scheme that the present invention solves its technical matters is, constructs a kind of computing machine, and it comprises that aforesaid computer booting starts management system.
The another technical scheme that the present invention solves its technical matters is, provides a kind of computer booting to start management method, it is characterized in that, in comprising the computing machine that computer booting starts management system, carries out following steps during start:
In basic input/output (BIOS) operational process, export first control signal by general input/output interface, described first control signal be arranged so that when start the time be first level, and confirm that it is second level that the normal surely operation of BIOS one triggers when finishing;
Receive described first control signal and timing, if up to first schedule time T
H, described first control signal still remains first level, then exports second control signal;
Receive described second control signal, and disconnect motherboard power supply immediately, and postponing second schedule time T
DAfter, at the 3rd schedule time T
JCCContinue to drag down the reset pin signal of CMOS during this time to remove CMOS;
Wherein, described first schedule time T
HGreater than the required time of the power-on self-test of described computing machine, described second schedule time T
DThoroughly exhaust required time, described the 3rd schedule time T more than or equal to the south bridge power supply of mainboard outage back
JCCRemove the required time of CMOS more than or equal to finishing.
Start in the management method at computer booting of the present invention, also comprise: after finishing the CMOS removing, use the last effectively BIOS that is stored in the nonvolatile random access memory to be provided with and restart described computing machine.
Start in the management method at computer booting of the present invention, also comprise: if at first schedule time T
HInterior described first control signal becomes second level from first level, then closes described computer booting and starts management system.
Start in the management method at computer booting of the present invention, also comprise:
When the BIOS normal operation period monitors Pause key when being pressed, send the instruction that the temporary close computer booting starts management system, and when bios program recovers to carry out, open computer booting again and start management system.
Implement the present invention and have following beneficial effect: cause computing machine not start shooting or non-artificial factor (for example virus) is destroyed CMOS information and caused under the situation that computing machine do not start shooting in the setting of CMOS information errors, need not to open cabinet and take off the lithium battery or the clear CMOS jumping of the short circuit cap of powering into CMOS, also need not to press by any button, can remove CMOS, need not the CMOS setting that manually-operated promptly can automatically restore to normal boot-strap last time, be user-friendly to.
Particularly for the particular application of industrial computer, the present invention can reduce the workload that reconfigures CMOS, the problem that minimizing industrial computer CMOS information errors causes computing machine not start shooting, thereby reduces the industrial computer maintenance cost.
Description of drawings
The invention will be further described below in conjunction with drawings and Examples, in the accompanying drawing:
Fig. 1 is the structural representation that computer booting of the present invention starts management system;
Fig. 2 is the schematic diagram that computer booting of the present invention starts the timing circuit that uses among management system one embodiment;
Fig. 3 is the Spice simulation waveform figure of timing circuit output signal shown in Figure 2;
Fig. 4 is first's circuit theory diagrams that computer booting starts management system one embodiment according to the present invention;
Fig. 5 is the second portion circuit theory diagrams that computer booting starts management system one embodiment according to the present invention;
Fig. 6 is the timing waveform that second portion circuit shown in Figure 5 generates;
Fig. 7 is the flow chart of steps that computer booting of the present invention starts management method;
Fig. 8 is the synoptic diagram of clear according to an embodiment of the invention CMOS function;
Fig. 9 recovers the synoptic diagram that last effectively BIOS is provided with function according to one embodiment of the invention.
Embodiment
In the actual calculation machine was used, the change of CMOS configuration sometimes caused computing machine normally to start, and need do CMOS action clearly.For manually clear CMOS, industry spot is inconvenient to take apart cabinet, also needs to carry out again BIOS (Basic Input/Output System, basic input/output) behind the intact clearly CMOS and is provided with.Sometimes the client does not know that this class can solve by clear CMOS unusually, can be judged as main board failure by mistake and needs the technical support of computer vendors.The present invention conceives a kind of computer booting and starts management system, automatically performs CMOS action clearly when computing machine does not start.In addition, also can automatically load last correct BIOS parameter is set.Thereby can address the above problem, to reduce unusual that analogue causes.
Computer booting of the present invention starts management system and judges whether normal boot-strap of system by a signal, and behind the normal boot-strap, computer booting starts management system and do not work; System boot is undesired, and computer booting starts management system work.After BIOS was checked through the work of computer booting startup management system, importing last time, correct BIOS was provided with parameter.
The management system that starts computer booting of the present invention can adopt timing circuit and on-off circuit to simulate the step that manually clear CMOS finishes: 1. cut off host power supply, 2. the RTC_RST signal ground.In one embodiment of the invention, computer booting starts management system and selects VCC5VSB as power supply, uses metal-oxide-semiconductor to make switch and realizes the entire circuit function, considers the sequential requirement simultaneously.
Figure 1 shows that the invention computer booting starts the structural representation of management system, comprising control module (being included among the BIOS) 110, timing circuit 120, on-off circuit 130 and clear cmos circuit 140.Also show the primary power 132 and the standby power 134 that link to each other with on-off circuit 130 among Fig. 1, the CMOS 141 that links to each other with clear COMS circuit 140.
On-off circuit 130 comprises suitable circuit, logic and/or code, and it is connected in described timing circuit, and disconnects motherboard power supply immediately when receiving the described second control signal S2, comprises primary power 132 and standby power 134.
Start in the technical scheme of management system first schedule time T at computer booting of the present invention
HShould be greater than the required time of the power-on self-test of described computing machine, second schedule time T
DThoroughly exhaust required time, the 3rd schedule time T more than or equal to the south bridge power supply of mainboard outage back
JCCRemove the required time of CMOS more than or equal to finishing.Sequential require will be in the back according to embodiments of the invention, describe in conjunction with timing waveform shown in Figure 6.
By the following examples, technical scheme of the present invention is further described.Should be appreciated that present embodiment just is used for explaining and explanation the present invention, be not limited to protection scope of the present invention.Under general plotting of the present invention, can also adopt other schemes to realize timing circuit, on-off circuit and clear cmos circuit.
In the present embodiment, computer booting starts management system and comprises hardware circuit part and software section (BIOS processing), below is described respectively.
One, hardware circuit part:
In one embodiment of this invention, use 555 trigger U1 to make timer (as shown in Figure 2) in the timing circuit, it is operated in unstable operation (Astable Operation) pattern, the triggering input pin of 555 trigger U1 (pin 2) links to each other with thresholding input pin (pin 6), make 555 as oscillator work, output pin (pin 3) output square wave.First capacitor C 1 is charged by first resistance R 1 and second resistance R 2, and by 2 discharges of second resistance R, so the cycle of the value of first resistance R 1, second resistance R 2 and first capacitor C 1 control output signal, wherein T
H=0.693 (R1+R2) * C1, T
L=0.693 (R1) * C1.When realizing, physical circuit need consider that capacitor C 1 appearance value under high low temperature changes.
The Spice simulation waveform of 555 trigger U1 output signals as shown in Figure 3, the high level lasting time of output pin output square wave is T
H, low duration is T
LAs seen from Figure 3, the T in the 1st cycle
HObviously be longer than the T in the 2nd cycle
H, this is that electric capacity does not discharge fully and is recharged again subsequently because the time of electric capacity primary charging is longer.Computer booting starts management system and only utilizes first cycle, at the T in the 1st cycle
HIn do not receive the normal boot-strap signal that BIOS sends, computer booting starts management system then can be at T
LFinish CMOS operation clearly during this time.Therefore, the T in first cycle
HTime is corresponding to aforementioned first schedule time T
H
Fig. 4 is first's circuit theory diagrams that computer booting starts management system one embodiment according to the present invention.The management system that starts computer booting adopts cut off the electricity supply unlatchings (PS_ON) signal and VCC5VSB to come performing step 1. (cut-out host power supply), allows the ATX power cut-off, and computer booting startup management system is powered by VCC5VSB.Concrete principle as shown in Figure 4.Timing circuit 120 comprises 555 trigger U1 and booting wait time adjusting circuit 125, and booting wait time adjusting circuit 125 is used to adjust first schedule time T
HWith the 4th schedule time T
L555 triggers link to each other with the 3rd switching device Q3 that is subjected to GPIO output control by booting wait time adjusting circuit 125.More specifically, the triggering input pin of 555 triggers (pin 2) links to each other with thresholding input pin (pin 6).The booting wait time adjusting circuit comprises the 4th resistance R 4, the 5th resistance R 5 and second capacitor C 2 of polyphone successively, and circuit one end that should contact links to each other other end ground connection by first resistance R 1 with VCC5.The DSCHG pin of 555 triggers is connected in the node of the 4th resistance R 4 and the 5th resistance R 5, and triggering input pin of 555 triggers (pin 2) and thresholding input pin (pin 6) are connected in the node of the 5th resistance R 5 and second capacitor C 2; The 3rd switching device Q3 is a metal-oxide-semiconductor, and its controlled end (grid) is connected with the GPIO interface, and source electrode is connected in VCC5, grounded drain by first resistance R 1.
Among Fig. 4, the 3rd switching device Q3 is used to control 555 flip-flop operation states, acquiescence GPIO=0 when start, 555 trigger operate as normal.Pre-determine T
HTime, regulate resistance R 4, R5 and capacitor C 2 and can change T
HTime span, capacitor C 2 is selected the patch capacitor of X5R type for use, between-55～85 ℃, it is less that capacitor's capacity changes.If at T
HIn time, BIOS operation normal (representing normal boot-strap) drives GPIO and puts height, and then computer booting startup management system is not worked, and 555 trigger output pins (pin 3) are output as height, the first switching device Q1 and second switch device Q2 conducting, the mainboard operate as normal is unaffected.If surpass T
HTime, BIOS does not drive GPIO and puts height, and then 555 trigger output pins (pin 3) are output as lowly, and computer booting starts management system work, the first switching device Q1 and not conducting of second switch device Q2, and cut-out ATX is to the power supply of mainboard.Wherein, the first switching device Q1 is used to control the on/off of standby (StandBy the is abbreviated as SB) voltage that the ATX power supply provides to mainboard, and second switch device Q2 is used to control the on/off of electric power starting (PS_ON) signal between ATX primary power and the motherboard power supply interface.First to the 3rd switching device all uses metal-oxide-semiconductor to realize in the present embodiment, as selection, also can adopt other embodiments, and for example relay or other can be carried out the device/device of switch motion.
Fig. 5 is the second portion circuit theory diagrams that computer booting starts management system one embodiment according to the present invention.Computer booting starts management system at the 4th schedule time T
L2. execution in step removes CMOS during this time, and schematic diagram as shown in Figure 5.Clear cmos circuit 140 comprises delay circuit 142, Schmidt (SCHMITT) trigger 144 and the 5th switching device Q5.The 6th resistance R 6 and the 4th capacitor C 4 constitute the RC delay circuit among Fig. 5, and purpose is behind the outage certain hour, and the 5th switching device Q5 just works.The pulse that utilization SCHMITT trigger 144 produces control the 5th switching device Q5, thereby the on/off of connecting path between the reset pin (RTC_RST) of control CMOS and the ground.
Fig. 6 is the timing waveform that Fig. 4, first, second partial circuit shown in Figure 5 generate.
As shown in Figure 6,555 trigger output pins (pin 3) are at first schedule time T
HOutput high level, at the 4th schedule time output low level T
LThe output signal of 555 triggers is exported the JCC signal simultaneously after the 4th switching device Q4 is anti-phase.After receiving the JCC signal, delay circuit second schedule time T that delays time
DAfter be sent to the SCHMITT trigger, the SCHMITT trigger produces the pulse be used to control the 5th switching device subsequently, the duration of this pulse is the 3rd schedule time T
JCCAt the 3rd schedule time T
JCCIn, the RTC_RST signal is dragged down, thereby realizes removing the operation of CMOS.
Second schedule time T
DTime span is to control the 3rd schedule time T by resistance R 6 and capacitor C 4
JCCTime span is to be controlled by resistance R 7 and capacitor C 5.Add T
DPurpose be to allow south bridge power supply thoroughly be exhausted the 3rd schedule time T
JCCThe RTC_RST of Q5 conducting during this time signal ground is finished CMOS operation clearly.The 4th schedule time T
LFinish back first switching device Q1 and second switch device Q2 conducting, computing machine starts automatically, and this is because the AFTERG3_EN register is put 0, powers on once more after AFTERG3_EN puts 0 and can start automatically, and the ATFERG3_EN effect is as follows:
The ATFERG3_EN register value is used to determine break down at power supply to enter which kind of state when re-powering after (G3 state).
When register value is 0, when re-powering, system will automatically return to S0 state (guiding);
When register value is 1, will turn back to S5 state (, will turn back to the S4 state in this case) unless it is in the S4 state.In the S5 state, unique can realize the incident of waking up be power knob or any after power fail, kept can realize the incident waken up.
Annotate: when generation is closed based on THRMTRIP#, will be provided with register value.
Fig. 7 is the flow chart of steps that computer booting of the present invention starts management method.As shown in Figure 7, computer booting of the present invention starts management method and starts from step 710, and start powers on.In step 720, in the BIOS operational process, export first control signal by the GPIO interface.First control signal be arranged so that when start the time be first level, and confirm that it is second level that the normal surely operation of BIOS one triggers when finishing.In step 730, receive described first control signal and timing, if up to first schedule time T
H, described first control signal still remains first level, then exports second control signal.In step 740, receive second control signal, and disconnect motherboard power supply immediately, and postponing second schedule time T
DAfter, at the 3rd schedule time T
JCCContinue to drag down the RTC_RST signal during this time to remove CMOS.Afterwards, proceed subsequent operation in step 750.Wherein, aforementioned subsequent operation comprises removing and enters the CMOSSETUP menu behind the CMOS and carry out the parameter setting, and the system of parameter after setting completed restart, and relevant this point will describe in conjunction with Fig. 9 in the back.
In addition, if at first schedule time T
HInterior described first control signal becomes second level from first level, then closes described computer booting and starts management system.
Two, software section, promptly the self-healing BIOS of CMOS handles:
At first select the GPIO (such purpose is to guarantee to power on to give tacit consent to open computer booting startup management system circuit) of the acquiescence output low level that powers on.RC delay circuit according to timing circuit (is provided with time-delay by resistance, electric capacity and is T
H), if power on T
HAfterwards, GPIO remains low level, then starts computer booting and starts management system, clear CMOS and restarting systems.
TH be provided with time span greater than system start-up to normally running through power-on self-test (Power On SelfTest, be called for short POST) the used time of Stage code, in case when confirming that the normal surely operation of BIOS one finishes, BIOS GPIO is set to height, the starting up's management system of promptly shutting down computer circuit.The selection of the time point of the starting up's management system of shutting down computer, based on confirming that the normal operation one of BIOS finishes this fact surely, for example can be to select one the POST stage and can trust the code point of (can confirm that the normal operation one of BIOS finish surely) the starting up's management system of shutting down computer before BIOS finishes.In one embodiment, for example can be after BIOS have moved the DMI code, GPIO is set to height.
Open NVRAM (Non-Volatile Random Access Memory, nonvolatile random access memory) function in the bios code, after CMOS was eliminated, the user entered CMOS setting (CMOSSETUP) menu and carries out the parameter setting.The NVRAM function is not to work when withdrawing from CMOS SETUP menu, but confirms that after restarting the user is provided with the energy normal boot-strap, just writes NVRAM with setting.Otherwise the startup timing circuit automatically recovers back the last time state effectively is set.What store among the NVRAM is that last effectively BIOS is provided with state.That is to say that using the last effectively BIOS that is stored among the described NVRAM to be provided with restarts computing machine.
In addition, in the time of need returning Default Value as if the user, enter CMOS SETUP, get final product according to the prompting factory reset.
Before BIOS puts high GPIO, press time-out (Pause) key during for fear of computer starting, cause computer booting to start management system and delay work.In bios code, when the user was come into force by the Pause key, the temporary close computer booting started the management system circuit, when treating again POST, opened computer booting more again and started management system.
In addition, when the user entered among the CMOS SETUP, the user had grace time for convenience, and computer booting startup this moment management system also need be closed.
Fig. 8 is the synoptic diagram of clear according to an embodiment of the invention CMOS function.In the embodiment shown in fig. 8, the GPIO acquiescence low level that powers on, and low level computer-chronograph starting up management system starts working, and closes COMS during high level from recovering module.
Need to prove that the general BIOS POST time different chipsets, different bios codes, connects different equipment about 15 seconds, this time is all inequality.Generally, give enough the sufficient time,, regulate T again by hardware according to concrete condition
HChange.Common first schedule time T
HCan select to set second schedule time T at 20 seconds to 1 minute
DWith the 3rd schedule time T
JCCCan in the 100ms-300ms scope, select.
Fig. 9 recovers the synoptic diagram that last effectively BIOS is provided with function according to one embodiment of the invention.As shown in Figure 9, in step 1, the BIOS that NVRAM has stored the A configuration when dispatching from the factory is provided with, and the user enters SETUP and carries out BIOS and be provided with subsequently, for example is set to the B configuration, the starting system of laying equal stress on, the still A configuration of storing among the NVRAM this moment.In step 2A, after system restarted, when carrying out POST with the B configuration, the deadlock that makes a mistake then recovered the A configuration among the NVRAM automatically, enters operating system.If at another step 2B, when carrying out POST, can normally start with the B configuration, then the B configuration is write among the NVRAM, and enter operating system, at this moment, what store among the NVRAM is the B configuration.
Need to prove, the embodiment of timing circuit of the present invention, on-off circuit and clear cmos circuit is not limited to the foregoing description, for example, can also use single-chip microcomputer, programmable gate circuit ... realize Deng device/assembly that those skilled in the art are familiar or commonly used.For example timing circuit can replace with single-chip microcomputer or CPLD, and the MOS switching tube can replace with relay or the IC with switching function.In the preferred embodiments of the present invention, selecting 555 triggers for use is for cost consideration as the main devices of timing circuit.
In addition, different embodiments based on timing circuit, on-off circuit and clear cmos circuit, the processing of BIOS also need be adjusted accordingly, for example, can select the GPIO of the acquiescence output high level that powers on to start computer booting startup management system, aforementioned like this first level can be adjusted into high level, and second level is adjusted into low level.
Claims (11)
1. a computer booting starts management system, it is characterized in that, comprising:
Be included in the control module in the basic input/output (BIOS), it exports first control signal by general input/output interface, described first control signal be arranged so that when start the time be first level, and confirm that it is second level that the normal surely operation of BIOS one triggers when finishing;
Timing circuit, it receives described first control signal and timing, if up to first schedule time T
H, described first control signal still remains first level, then exports second control signal;
On-off circuit, it is connected in described timing circuit, and disconnects motherboard power supply immediately when receiving described second control signal;
Clear cmos circuit, it is connected in described timing circuit, and postpones second schedule time T when receiving described second control signal
DAfter, at the 3rd schedule time T
JCCContinue to drag down the reset pin signal of CMOS during this time to remove CMOS;
Wherein, described first schedule time T
HGreater than the required time of the power-on self-test of described computing machine, described second schedule time T
DThoroughly exhaust required time, described the 3rd schedule time T more than or equal to the south bridge power supply of mainboard outage back
JCCRemove the required time of CMOS more than or equal to finishing.
2. computer booting according to claim 1 starts management system, it is characterized in that, comprises nonvolatile random access memory, stores last effectively BIOS configuration information on it; Wherein, after finishing CMOS and removing, described control module is used effective BIOS of the described last time that is stored in the described nonvolatile random access memory to be provided with to restart described computing machine.
3. computer booting according to claim 2 starts management system, it is characterized in that, if at first schedule time T
HInterior described first control signal becomes second level from first level, then closes described computer booting and starts management system.
4. computer booting according to claim 3 starts management system, it is characterized in that described timing circuit comprises 555 triggers and booting wait time adjusting circuit; Wherein, the triggering input pin of described 555 triggers link to each other with the thresholding input pin so that its as oscillator work, the high level lasting time of output pin output square wave is described first schedule time T
HDescribed booting wait time adjusting circuit is used to set described first schedule time T
H
5. start management system according to each described computer booting in the claim 1 to 4, it is characterized in that, described on-off circuit comprises second switch device (Q2) and first switching device (Q1) that is controlled by described second control signal, is respectively applied for the on/off of electric power starting (PS_ON) signal between control ATX power supply and the motherboard power supply interface and the on/off of standby (SB) voltage that the ATX power supply provides to mainboard.
6. start management system according to each described computer booting in the claim 1 to 4, it is characterized in that described clear cmos circuit comprises delay circuit, Schmidt's (SCHMITT) trigger and the 5th switching device (Q5); Wherein, described delay circuit is used for described second control signal second schedule time T that delays time
DAfter be sent to described SCHMITT trigger, described SCHMITT trigger produces the pulse that is used to control described the 5th switching device, drags down to realize CMOS reset pin signal; The duration of described pulse is the 3rd schedule time T
JCC
7. a computing machine is characterized in that, comprises as each described computer booting in the claim 1 to 6 starting management system.
8. a computer booting starts management method, it is characterized in that, in the computing machine that comprises computer booting startup management system, carries out following steps during start:
In basic input/output (BIOS) operational process, export first control signal by general input/output interface, described first control signal be arranged so that when start the time be first level, and confirm that it is second level that the normal surely operation of BIOS one triggers when finishing;
Receive described first control signal and timing, if up to first schedule time T
H, described first control signal still remains first level, then exports second control signal;
Receive described second control signal, and disconnect motherboard power supply immediately, and postponing second schedule time T
DAfter, at the 3rd schedule time T
JCCContinue to drag down the reset pin signal of CMOS during this time to remove CMOS;
Wherein, described first schedule time T
HGreater than the required time of the power-on self-test of described computing machine, described second schedule time T
DThoroughly exhaust required time, described the 3rd schedule time T more than or equal to the south bridge power supply of mainboard outage back
JCCRemove the required time of CMOS more than or equal to finishing.
9. computer booting according to claim 8 starts management method, it is characterized in that, also comprises: after finishing the CMOS removing, use the last effectively BIOS that is stored in the nonvolatile random access memory to be provided with and restart described computing machine.
10. computer booting according to claim 8 starts management method, it is characterized in that, also comprises: if at first schedule time T
HInterior described first control signal becomes second level from first level, then closes described computer booting and starts management system.
11. computer booting according to claim 8 starts management method, it is characterized in that, also comprises:
When the BIOS normal operation period monitors Pause key when being pressed, send the instruction that the temporary close computer booting starts management system, and when bios program recovers to carry out, open computer booting again and start management system.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201010147419.1A CN102221864B (en) | 2010-04-15 | 2010-04-15 | Computer, and computer startup management system and method thereof |
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| CN103678060A (en) * | 2012-09-20 | 2014-03-26 | 恩斯迈电子(深圳)有限公司 | Self-repairing device for computer mainboard |
| CN104182243A (en) * | 2013-05-21 | 2014-12-03 | 纬创资通股份有限公司 | Sleep state control system, computer system and sleep state detection method thereof |
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