WO2019015087A1

WO2019015087A1 - A startup signal processing method and device

Info

Publication number: WO2019015087A1
Application number: PCT/CN2017/103110
Authority: WO
Inventors: 齐京
Original assignee: 西安中兴新软件有限责任公司
Priority date: 2017-07-20
Filing date: 2017-09-25
Publication date: 2019-01-24
Also published as: CN109283991A

Abstract

A startup signal processing method, comprising: upon detection of a system power source, generating a valid system startup trigger signal and triggering execution of a startup process (S11); and turning off the valid system startup trigger signal after completing execution of the startup process (S12). The method prevents errors or interruptions caused by strain on a power source during the startup process.

Description

Method and device for processing start signal

Technical field

The embodiments of the present invention relate to the field of communications technologies, and in particular, to a method and an apparatus for processing a boot signal.

Background technique

With the development of electronic product technology and functions, the implementation of the product has become diversified, mainly including button triggering, dialing triggering, power-on and triggering, etc. The power-on triggering mode does not require other operations, as long as the power is turned on. That is, the booting is triggered, and the existing product is implemented by applying a normal high or low level that triggers the logic to the power-on trigger source pin of the processor, and is currently used on many existing platforms.

With the rapid development of electronic product technology, in some processor platforms, the function of triggering the power-on has become more and more. For example, different functions are defined according to the different time lengths triggered by the power-on trigger signal, so the previous processing In the implementation of the design in the platform, a normal high or low level that triggers the logic is applied to the power-on trigger source pin, and is triggered when used on the processor platform with the time length definition of the power-on trigger pin. A new interrupt is generated, causing problems in use.

In the low pulse output circuit and the device applying the low pulse output, it is described that the externally applied low to high level controls the second logic circuit through the first logic circuit, and the second logic circuit controls the third logic circuit through the delay circuit, A method of generating a low-pulse signal is used. In this method, more logic circuits are used, and a RC (Resistance-Capacitance) delay circuit is used, which increases the number of devices used, is not sufficiently streamlined, and is applied. In the different function usage scenarios of power-on, if the system needs to be restarted after shutdown, this method of generating low pulses according to the externally input low-to-high step pulse signal cannot be realized without powering down the power supply for re-powering. The second power-on, in addition, the RC delay circuit will make the start pulse signal generation speed very slow, may not be used in some scenarios with low power-on delay.

Summary of the invention

The technical problem to be solved by the embodiments of the present invention is to provide a method and a device for processing a boot signal, so as to avoid the occurrence of an erroneous interrupt during the startup of the power supply.

A method for processing a boot signal, comprising:

When the system power supply is detected, a power-on trigger valid signal is generated, and the boot process is triggered;

After the boot process is completed, the power-on trigger valid signal is turned off.

Optionally, the turning off the power-on triggering valid signal includes:

Immediately turn off the power-on trigger valid signal, or

The power-on trigger valid signal is turned off after a specified time.

Optionally, after detecting that the system power exists, the method further includes:

Detecting the effectiveness of the system power supply.

Optionally, when the detecting that the system power is present, generating a power-on trigger valid signal is implemented by:

a gate of the first semiconductor metal oxide MOS transistor is connected to the system power supply through a first resistor, a source of the first MOS transistor is grounded, and a drain of the first MOS transistor passes through a second resistor and the system The power connection is configured to: when the system power is present, the drain output of the first MOS transistor triggers a valid signal.

Optionally, after the booting process is completed, turning off the power-on triggering valid signal is implemented by:

The source of the second MOS transistor is grounded, the drain of the second MOS transistor is connected to the gate of the first MOS transistor to the first node, and the gate of the MOS transistor receives a request to turn off the power-on triggering valid signal. After the level signal, the potential of the first node is lowered, and the first MOS transistor is turned off.

A processing device for a boot signal, comprising:

The signal generating module is configured to generate a power-on trigger valid signal when the system power is detected to be present Number, triggering the execution of the boot process;

The control module is configured to turn off the power-on trigger valid signal after the boot process is completed.

Optionally, the control module, when the power-on triggering valid signal is turned off, includes: immediately turning off the power-on triggering valid signal, or turning off the power-on triggering valid signal after a specified time.

Optionally, the processing device further includes:

The detecting module is configured to detect the validity of the system power after detecting the presence of the system power.

Optionally, the signal generating module includes a first semiconductor metal oxide MOS transistor and a second resistor, wherein a gate of the first MOS transistor is connected to the system power supply through a first resistor, the first MOS The source of the tube is grounded, and the drain of the first MOS transistor is connected to the system power supply through the second resistor. When the system power supply is present, the drain output of the first MOS transistor outputs a power-on triggering valid signal.

Optionally, the control module includes a second MOS transistor and the first resistor, wherein a source of the second MOS transistor is grounded, a drain of the second MOS transistor is opposite to the first MOS transistor The gate and the first resistor are connected to the first node, and after receiving the level signal requesting to turn off the power-on triggering valid signal, the gate of the second MOS transistor lowers the potential of the first node, and turns off the first A MOS tube.

Optionally, the signal generating module includes a first triode and a third resistor, wherein a base of the first triode is connected to the system power supply through a fourth resistor, the first triode The emitter of the first triode is connected to the system power supply through the third resistor, and the collector output of the first triode is activated to trigger an effective signal when the system power source is present. .

Optionally, the control module includes a second transistor, a third transistor, the fourth resistor, and a fifth resistor, wherein an emitter of the second transistor is grounded, and the second The collector of the pole tube is connected to the base of the first transistor and the fourth resistor to the second node, the emitter of the third transistor is grounded, and the collector of the third transistor And the base of the second triode And connecting one end of the fifth resistor, the other end of the fifth resistor is connected to the system power supply, and after the base of the third transistor receives a level signal requesting to turn off the power-on trigger valid signal, The third transistor is turned off, the second transistor is turned on to lower the potential of the second node, and the first transistor is turned off.

According to still another embodiment of the present invention, there is also provided a storage medium comprising a stored program, wherein the program is executed to perform the method of any of the above.

According to still another embodiment of the present invention, there is also provided a processor for running a program, wherein the program is executed to perform the method of any of the above.

In summary, the embodiments of the present invention provide a method and a device for processing a power-on signal, which can avoid the occurrence of an erroneous interrupt during the power-on triggering process.

DRAWINGS

1 is a flowchart of a method for processing a boot signal according to Embodiment 1 of the present invention;

2 is a schematic diagram of a device for processing a boot signal according to a second embodiment of the present invention;

3 is a general block diagram of a device for processing a boot signal according to Embodiment 3 of the present invention;

4 is a flowchart of a method for processing a boot signal according to Embodiment 3 of the present invention;

FIG. 5 is a schematic diagram of a device for processing a boot signal according to Embodiment 4 of the present invention; FIG.

FIG. 6 is a schematic diagram of a device for processing a boot signal according to Embodiment 5 of the present invention.

Detailed ways

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, in the case of no conflict, the features in the embodiments and the embodiments in the present application may be arbitrarily combined with each other.

Embodiment 1

FIG. 1 is a flowchart of a method for processing a boot signal according to an embodiment of the present invention. As shown in FIG. 1 , the processing method of this embodiment includes the following steps:

S11. When the system power supply is detected, a power-on trigger valid signal is generated, and the triggering execution is started. Machine process

S12. After the boot process is completed, the power-on trigger valid signal is turned off.

In an embodiment, the turning off the power-on triggering valid signal may immediately turn off the power-on triggering valid signal, or may turn off the power-on triggering valid signal after a specified time.

The method of the embodiment implements the intelligent control of the power-on trigger source signal, and avoids the interruption caused by the application of the power source to trigger an error during the power-on.

Embodiment 2

FIG. 2 is a schematic diagram of a device for processing a boot signal according to an embodiment of the present invention. As shown in FIG. 2, the processing device of this embodiment includes:

The signal generating module is configured to generate a power-on triggering valid signal when the system power source is detected, and trigger a booting process;

In an embodiment, the controlling module, when the power-on triggering valid signal is turned off, includes: immediately turning off the power-on triggering valid signal, or turning off the power-on triggering valid signal after a specified time.

In an embodiment, the processing device further includes:

In one embodiment, the signal generating module includes a first semiconductor metal oxide MOS transistor and a second resistor, wherein a gate of the first MOS transistor is connected to the system power supply through a first resistor, A source of the MOS transistor is grounded, and a drain of the first MOS transistor is connected to the system power supply through a second resistor, and a drain output of the first MOS transistor outputs a valid signal when the system power supply is present.

The control module includes a second MOS transistor and the first resistor, wherein a source of the second MOS transistor is grounded, a drain of the second MOS transistor and a gate of the first MOS transistor Connected to the first node, after receiving the level signal requesting to turn off the power-on triggering valid signal, the gate of the MOS transistor lowers the potential of the first node and turns off the first MOS transistor.

The device of the embodiment can realize the intelligent control of the power-on trigger source signal, and avoids the interruption caused by the application of the power source to trigger an error during the power-on.

Embodiment 3

FIG. 3 is a general block diagram of a device for processing a boot signal according to an embodiment of the present invention. As shown in FIG. 3, the processing device of the embodiment includes: a boot signal logic generating unit 301 (corresponding to the signal generating module above) and a boot signal. The logic control unit 302 (corresponding to the above control module), the power-on signal logic generating unit outputs a power-on trigger signal to the power-on process execution unit in the power processor, and the power-on signal logic feedback unit in the power processor turns to the power-on signal logic according to the situation. The control unit sends a power-off trigger valid signal. The thick arrows in Figure 3 represent the power lines that the system power supplies to the product, and the thin arrows represent the control lines for the control signals.

The system power control startup signal generating unit generates a power-on signal, and the power-on signal triggers the booting process execution unit to execute the booting process. The booting process execution unit feeds back the power-on logic feedback unit to request to turn off the power-on triggering valid signal according to the function requirement, and the booting process control unit receives the feedback. After the signal is turned off, the power-on signal generation unit is turned off, and the power-on trigger signal becomes invalid.

After the system is shut down, if the system power is still normal, the circuit in this embodiment will once again generate a power-on trigger signal to trigger the system to boot.

The workflow diagram of this embodiment is shown in Figure 4. The specific steps are as follows:

Step 101: Detecting system power. When the system power is present, generating a valid power-on trigger level signal by the power-on signal logic generating unit, and proceeding to step 102. If the system power supply does not exist, the system is in a power-off state and cannot be turned on. The logic generation unit also does not generate a power-on trigger signal.

Step 102: After the boot process execution unit detects the valid boot trigger level signal, the boot process is performed. If the system platform used by the product needs to detect the active level of the input system power, the boot process also needs to be detected. The effectiveness of the system power supply.

The effectiveness of the power supply of the detection system in this embodiment is an effective input for detecting whether the input voltage reaches a range of the system power-on level.

Step 103: After the boot process is completed, determine whether to immediately turn off the power-on trigger signal according to the function requirement. If it is not necessary to trigger a new interrupt according to the length of the power-on signal, perform step 104. Otherwise, the length of time is defined according to the demand function, and after the time is reached, step 104 is performed.

Step 104: The power-on signal logic feedback unit requests the power-on logic signal control unit to turn off the power-on trigger valid signal, and the power-on logic signal control unit turns off the power-on trigger logic signal unit after receiving the request, and sets the valid power-on trigger level signal to be invalid. level.

After the power-on, it is assumed that there are other factors that cause the system power supply to be unstable, and the power-on signal generation method provided in the embodiment of the present invention starts from step 102 after the power-off, and generates a power-on trigger signal to trigger the system to start.

The method for processing a power-on signal according to an embodiment of the present invention can convert a high-level signal into a pulse signal with adjustable time width.

When the different lengths of the power-on signal have different definitions, the power-on pulse signal whose time length can be adjusted is needed, and the power-on process execution unit sets the active level to be invalid through the feedback unit after the set time length is executed. The length of time can be adjusted according to the set time.

Embodiment 4

FIG. 5 is a schematic diagram of a device for processing a boot signal according to an embodiment of the present invention. In this embodiment, the boot trigger signal is an active low signal, and the system power supply supplies power to the entire product, and the product mainly includes power management, a processor, and other parts. .

In this embodiment, the boot signal logic generating unit comprises a Q1 tube and a resistor R2, and the boot process execution unit can be implemented by a power management chip, a processor chip and a display part circuit, and the boot signal logic feedback unit can be implemented by the processor GPIO (General Purpose Input Output, general purpose input / output), the power-on signal logic control unit is realized by Q2 tube and resistor R2.

When the system power is detected, the system power supply adds an initial high level state to the power-on trigger signal through R2. Q2 defaults to the off state. After the system power supply turns on the Q1 tube, the active low-level signal generated by the power-on trigger is generated. After the chip detects a valid power-on trigger signal, it starts powering up the system and simultaneously displays part of the circuit to perform the power-on display action. After the boot is completed, the processor chip selects the specific time request to open the Q2 tube according to the definition of the function requirement by the GPIO. After the Q2 is turned on, the level of the R1 near the Q1 side becomes low, the Q1 tube will be turned off, and the power-on trigger signal becomes invalid. .

In addition, when the system is powered off, if the system power is still normal, this circuit will once again generate a power-on trigger signal to trigger the system to boot.

In the embodiment of the signal generating method for triggering the automatic startup of the product when the power source is applied, the Q1 tube and the Q2 tube in the power-on signal logic generating unit and the power-on signal logic control unit may be MOS (Metal-Oxide-Semiconductor, semiconductor metal oxide). In the embodiment, an N-channel MOS transistor can be used in this embodiment.

In an embodiment, the MOS transistor in FIG. 5 can also be replaced with a triode, and the power-on signal logic feedback unit can also be implemented by other processor-controlled power signals.

Embodiment 5

FIG. 6 is a schematic diagram of another implementation of the present invention by using a triode method. In this embodiment, the boot signal logic generating unit includes a Q1 tube and a resistor R2, and the boot process execution unit can be powered by a power management chip, a processor chip, and a display. Part of the circuit is implemented, the power-on signal logic feedback unit can be implemented by the processor's default pull-up GPIO (General Purpose Input Output), and the boot signal logic control unit is composed of Q2 tube, Q3 tube, resistor R2 and resistor. R3 implementation.

When the system power is detected, the system power supply adds an initial high state to the power-on trigger signal through R2. Q3 defaults to saturation conduction, Q2 is off, Q1 is saturated, and the active low level signal is generated. After the power management chip detects a valid power-on trigger signal, the system starts power-on, and at the same time, some circuits are displayed to perform a power-on display action. After the boot is completed, the processor chip selects the specific time request through the GPIO according to the definition of the functional requirements to cut off Q3, Q2. When it becomes saturated, the level of R1 near the Q1 side becomes low, the Q1 tube becomes OFF, and the power-on trigger signal becomes invalid.

The triode of the embodiment adopts an NPN triode, and of course, a PNP triode can also be used. The principle is similar, and the description will not be repeated here.

This embodiment provides a way to finally convert a high level power signal into a time width adjustable pulse signal. The power-on signal logic control unit selects whether to turn on or off the power-on trigger source signal according to the detection of the logic signal feedback unit of the power-on signal according to different demand functions and scene definitions, thereby realizing the intelligent control of the power-on trigger source signal, and avoiding the application of the power source to trigger the power-on process. An error interrupt was generated.

Embodiments of the present invention also provide a storage medium including a stored program, wherein the program described above executes the method of any of the above.

Optionally, in the embodiment, the foregoing storage medium may include, but is not limited to, a USB flash drive, a Read-Only Memory (ROM), and a Random Access Memory (RAM). A variety of media that can store program code, such as a hard disk, a disk, or an optical disk.

Embodiments of the present invention also provide a processor for running a program, wherein the program is executed to perform the steps of any of the above methods.

One of ordinary skill in the art will appreciate that all or a portion of the steps described above can be accomplished by a program that instructs the associated hardware, such as a read-only memory, a magnetic or optical disk, and the like. Alternatively, all or part of the steps of the above embodiments may also be implemented using one or more integrated circuits. Correspondingly, each module/unit in the foregoing embodiment may be implemented in the form of hardware or in the form of a software function module. The invention is not limited to any specific form of combination of hardware and software.

The above is only a preferred embodiment of the present invention, and of course, the present invention may be embodied in various other embodiments without departing from the spirit and scope of the invention. Corresponding changes and modifications are intended to be included within the scope of the appended claims.

Industrial applicability

As described above, the method and apparatus for processing a power-on signal provided by the embodiments of the present invention have the following beneficial effects: the application of the power source can be avoided to trigger an error interrupt during the power-on process.

Claims

A method for processing a boot signal, comprising:

When the system power supply is detected, a power-on trigger valid signal is generated, and the boot process is triggered;

After the boot process is completed, the power-on trigger valid signal is turned off.
The method of claim 1 wherein: said turning off said power-on triggering valid signal comprises:

Immediately turn off the power-on trigger valid signal, or

The power-on trigger valid signal is turned off after a specified time.
The method of claim 1 wherein: after detecting the presence of the system power supply, the method further comprises:

Detecting the effectiveness of the system power supply.
The method of claim 1 wherein: when said detecting that system power is present, generating a power-on trigger valid signal is accomplished by:

a gate of the first semiconductor metal oxide MOS transistor is connected to the system power supply through a first resistor, a source of the first MOS transistor is grounded, and a drain of the first MOS transistor passes through a second resistor and the system The power connection is configured to: when the system power is present, the drain output of the first MOS transistor triggers a valid signal.
The method of claim 4, wherein after the booting process is completed, turning off the power-on trigger valid signal is implemented by:

The source of the second MOS transistor is grounded, the drain of the second MOS transistor is connected to the gate of the first MOS transistor to the first node, and the gate of the MOS transistor receives a request to turn off the power-on triggering valid signal. After the level signal, lowering the potential of the first node, turning off the The first MOS tube is described.
A processing device for a boot signal, comprising:

The signal generating module is configured to generate a power-on triggering valid signal when the system power source is detected, and trigger a booting process;

The control module is configured to turn off the power-on trigger valid signal after the boot process is completed.
The processing apparatus of claim 6 wherein:

The control module, when the power-on triggering valid signal is turned off, includes: immediately turning off the power-on triggering valid signal, or turning off the power-on triggering valid signal after a specified time.
The processing device of claim 6 wherein: said processing device further comprises:

The detecting module is configured to detect the validity of the system power after detecting the presence of the system power.
A processing apparatus according to any of claims 6-8, wherein:

The signal generating module includes a first semiconductor metal oxide MOS transistor and a second resistor, wherein a gate of the first MOS transistor is connected to the system power supply through a first resistor, and a source of the first MOS transistor Grounding, the drain of the first MOS transistor is connected to the system power supply through the second resistor, and the drain output of the first MOS transistor outputs a power-on triggering valid signal when the system power supply is present.
The processing apparatus of claim 9 wherein:

The control module includes a second MOS transistor and the first resistor, wherein a source of the second MOS transistor is grounded, a drain of the second MOS transistor and the first MOS transistor The gate and the first resistor are connected to the first node, and after receiving the level signal requesting to turn off the power-on triggering valid signal, the gate of the second MOS transistor lowers the potential of the first node, and turns off the The first MOS tube.
A processing apparatus according to any of claims 6-8, wherein:

The signal generating module includes a first triode and a third resistor, wherein a base of the first triode is connected to the system power supply through a fourth resistor, and an emitter of the first triode is grounded The collector of the first transistor is connected to the system power supply through the third resistor, and the collector output of the first transistor triggers a valid signal when the system power is present.
A processing apparatus according to claim 11 wherein:

The control module includes a second triode, a third triode, the fourth resistor and a fifth resistor, wherein an emitter of the second triode is grounded, and the second triode is set The electrode is connected to the base of the first transistor and the fourth resistor to the second node, the emitter of the third transistor is grounded, the collector of the third transistor and the first a base of the two transistors is connected to one end of the fifth resistor, and the other end of the fifth resistor is connected to the system power supply, and a base of the third transistor receives a request to turn off the power-on trigger effective signal. After the level signal, the third transistor is turned off, the second transistor is turned on to lower the potential of the second node, and the first transistor is turned off.
A storage medium, the storage medium comprising a stored program, wherein the program is executed to perform the method of any one of claims 1 to 5.