CN106324477B - Latched test apparatus and method - Google Patents
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- CN106324477B CN106324477B CN201510392652.9A CN201510392652A CN106324477B CN 106324477 B CN106324477 B CN 106324477B CN 201510392652 A CN201510392652 A CN 201510392652A CN 106324477 B CN106324477 B CN 106324477B
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Abstract
The present invention provides a kind of latched test apparatus and method, and the latched test method includes the following steps: to execute setting operation, to set benchmark test value according to test section, and utilize benchmark test value setting trigger pulse and preset error value；The test chip in wafer to be measured is tested using trigger pulse, and differentiates whether test chip is in latch mode；According to differentiation result, latch critical value and benchmark test value, and decides whether to update test section and latch critical value and whether return to the step of executing setting operation；When test chip is in latch mode, and the difference of latch critical value and benchmark test value is not more than preset error value, stop the test of test chip.
Description
Technical field
The invention relates to a kind of latched test apparatus and method, and in particular to one kind can be used to test to be measured
The latched test apparatus and method of wafer.
Background technique
Latch-up (Latch-up effect) is the key factor for influencing the reliability of integrated circuit, therefore integrated
Circuit can all carry out the test of latch-up immunity mostly before factory.In general, the manufacturing process of integrated circuit includes circuit
Design, chip manufacturing and chip package.In addition, existing latched test method is the trigger pulse using linear increment, to
The integrated circuit in chip package stage carries out latched test.However, since trigger pulse is gradually to be incremented by a linear fashion,
Existing latched test method, which must often expend the huge testing time, could complete the test of integrated circuit latch-up immunity.
It is tested, therefore is manufactured in the integrated circuit in chip package stage further, since existing latched test method is only capable of being directed to
Quotient must often wait until the final stage of integrated circuit in the fabrication process, can just decide whether to remake integrated circuit,
And then lead to the production cost of integrated circuit and the increase of production time.
Summary of the invention
The present invention provides a kind of latched test apparatus and method, can reduce the testing time, and helps to reduce production cost
With the production time.
Latched test method of the invention, includes the following steps.Setting operation is executed, it is more to be covered from test section
Benchmark test value is chosen one as in a test value, and utilizes benchmark test value setting trigger pulse and preset error value.Wherein, base
Quasi- test value is divided into the first subinterval and the second subinterval for section is tested.The survey in wafer to be measured is tested using trigger pulse
Chip is tried, to obtain an at least detection signal.Differentiate whether test chip is in latch mode according to an at least detection signal.When
When test chip is not in latch mode, test section is updated according to the first subinterval, and return to the step of executing setting operation.
When test chip is in latch mode, and the difference of latch critical value and benchmark test value is greater than preset error value, according to base
Quasi- test value and the second subinterval update latch critical value and the test section respectively, and return to the step of executing setting operation.
When test chip is in latch mode, and the difference of latch critical value and benchmark test value is not more than preset error value, stop
Test the test of chip.
Latched test device of the invention, including controller, signal generator and signal detection device.Controller is from test section
Between choose one as benchmark test value in multiple test values for being covered, and using benchmark test value setting trigger pulse and default miss
Difference, and benchmark test value is divided into the first subinterval and the second subinterval for section is tested.Signal generator benchmark is surveyed
Examination value generates trigger pulse, and trigger pulse is sent to the test chip in wafer to be measured, with cause latched test device into
The test of row test chip.The detecting of signal detection device carrys out the signal of self-test chip, to obtain an at least detection signal, and controls
Device differentiates whether test chip is in latch mode according to an at least detection signal.When test chip is not in latch mode,
Controller updates test section according to the first subinterval, and resets trigger pulse according to updated test section, so that
Latched test device is set to carry out the test of test chip again.When test chip is in latch mode, and latch critical value and base
When the difference of quasi- test value is greater than preset error value, controller benchmark test value updates latch with the second subinterval respectively and faces
Dividing value and test section, to cause latched test device to carry out the test of test chip again.When test chip is in latch shape
State, and when the difference of latch critical value and benchmark test value is not more than preset error value, latched test device stops test chip
Test.
Based on above-mentioned, the adjustable test section of the present invention, and corresponding benchmark test value can be selected in response to test section,
To set the trigger pulse to test wafer to be measured whereby.Whereby, it can reduce the testing time, and facilitate reduction and be produced into
Sheet and production time.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and cooperate appended attached drawing
It is described in detail below.
Detailed description of the invention
Fig. 1 is the schematic diagram of the latched test device of an embodiment according to the present invention.
Fig. 2 is the flow chart of the latched test method of an embodiment according to the present invention.
Fig. 3 is an embodiment according to the present invention to illustrate to test schematic diagram of the section in adjustment.
Fig. 4 is that the variation to illustrate change of the benchmark test value with test section of an embodiment according to the present invention is shown
It is intended to.
Fig. 5 is the detailed flowchart to illustrate step S220 Yu step S230 of an embodiment according to the present invention.
Fig. 6 is the waveform diagram to illustrate latched test of an embodiment according to the present invention.
Fig. 7 is the detailed flowchart to illustrate step S220 Yu step S230 of another embodiment according to the present invention.
Fig. 8 is the waveform diagram to illustrate latched test of an embodiment according to the present invention.
[symbol description]
100: latched test device
110: signal generator
120: signal detection device
200: wafer to be measured
210: test chip
Step in S210~S280: Fig. 2 embodiment
VH3, VL3, VA31~VA33: test value
310~330: numerical intervals
311,321,331: the first subinterval
312,322,332: the second subinterval
VA41~VA46: benchmark test value
Step in S510~S560: Fig. 5 embodiment
T61~T63, T81~T83: period
610: supply voltage
620,810: trigger pulse
Step in S710~S750: Fig. 7 embodiment
Specific embodiment
Fig. 1 is the schematic diagram of the latched test device of an embodiment according to the present invention.As shown in Figure 1, latched test device
100 can be in this way to test the tester table of wafer 200 to be measured.Wherein, wafer 200 to be measured includes test chip 210, and is tested
It include integrated circuit in chip 210.Latched test device 100 can be electrically connected to by the probe on probe card (not showing)
Wafer 200 to be measured, to carry out various tests to the integrated circuit in the test chip 210 on wafer 200 to be measured, such as latch is surveyed
Examination.
Latched test device 100 includes signal generator 110, signal detection device 120 and controller 130.Signal generator
110 can produce trigger pulse, and trigger pulse can be transmitted by probe to test chip 210.In addition, controller 130 can foundation
Benchmark test value adjusts the size (for example, vibration good fortune) of trigger pulse, can cause to test the generation latch effect of chip 210 to emulate whereby
The various trigger sources answered.Signal detection device 120 can detect the signal on test chip 210 by probe, for controller 130
Characteristic or state of analysis test chip 210 etc., thus the latch-up immunity of the integrated circuit in validation test chip 210.
Fig. 2 is the flow chart of the latched test method of an embodiment according to the present invention, and below will be referring concurrently to Fig. 1 and figure
2 further explain the latched test that latched test device 100 carries out wafer 200 to be measured.As shown in step S210, door bolt
Setting operation can be performed in lock test device 100, to set benchmark test value, trigger pulse and preset error value whereby.It is specific and
It says, the controller 130 in latched test device 100 can choose one as benchmark from multiple test values that a test section is covered
Test value, and utilize benchmark test value setting trigger pulse and preset error value.Wherein, benchmark test value will test interval division
At the first subinterval and the second subinterval.
For example, Fig. 3 is an embodiment according to the present invention to illustrate to test schematic diagram of the section in adjustment.Such as
Shown in Fig. 3, test section can be for example the numerical intervals 310 from test value VL3 to test value VH3.Controller 130 can will be located at
Test value VA31 in numerical intervals 310 is set as benchmark test value, so can benchmark test value set trigger pulse.
In addition, benchmark test value VA31 can be brought into an expression formula to calculate preset error value by controller 130.If for example, VA31
=a × 10b, the calculated preset error value of institute is represented by 10(b-2), wherein 1≤a < 10 and b are integer.It is, working as VA31
When=300mA, preset error value is equal to 1mA.As VA31=20mA, preset error value is equal to 0.1mA.Furthermore benchmark
Numerical intervals 310 can be divided into the first subinterval 311 and the second subinterval 312 by test value VA31, and in the first subinterval 311
Test value be greater than benchmark test value VA31, the test value in the second subinterval 312 is less than benchmark test value VA31.
As shown in step S220, signal generator 110 can benchmark test value generation trigger pulse.In addition, signal produces
Trigger pulse can be sent to test chip 210 by raw device 110, so that latched test device 100 carries out the survey of test chip 210
Examination.Signal detection device 120 can detect the signal for carrying out self-test chip 210 and generate an at least detection signal accordingly.Furthermore as walked
Shown in rapid S230 and step S240, controller 130 can differentiate whether test chip 210 is according to an at least detection signal
Latch mode, and can differentiate whether latch critical value and the difference of benchmark test value are greater than preset error value.
When 130 discriminating test chip 210 of controller is not in latch mode, that is, it is integrated in test chip 210
When circuit does not generate latch-up, as shown in step S250, controller 130 can update test section according to the first subinterval, and
Return to step S210.For example, as shown in figure 3, when being test chip 210 using test result acquired by test value VA31
When not generating latch-up, controller 130 can update test section according to the first subinterval 311, and then cause to test section
It is updated to the numerical intervals 320 from test value VA31 to test value VH3.In addition, latched test device 100 repeats step
S210 is surveyed with selecting test value VA32 from updated test section (it is, numerical intervals 320) as new benchmark
Examination value, and trigger pulse and preset error value are reset using new benchmark test value (it is, test value VA32).Its
In, new benchmark test value (it is, test value VA32) can be by updated test section (it is, numerical intervals 320)
It is divided into the first subinterval 321 and the second subinterval 322.
Furthermore latched test device 100 repeats step S210~S230, to utilize the trigger pulse after resetting again
The secondary test for carrying out test chip 210, and the test result of analysis test chip 210 again.On the other hand, when controller 130
Discriminating test chip 210 is in latch mode (it is, the integrated circuit in test chip 210 generates latch-up), and fastens with a bolt or latch
When locking the difference of critical value and benchmark test value greater than preset error value, as shown in step S260 and step S270, controller 130
Can benchmark test value update latch critical value, and can according to the second subinterval update test section.
For example, as shown in figure 3, when being that test chip 210 generates using test result acquired by test value VA32
Latch-up, the and when difference of latch critical value and benchmark test value is greater than preset error value, controller 130 can benchmark survey
Examination value (it is, test value VA32) updates latch critical value, and test section can be updated according to the second subinterval 322, into
And test section is caused to be updated to the numerical intervals 330 from test value VA31 to test value VA32.In addition, latched test device
100 repeatable step S210, to select test value VA33 work from updated test section (it is, numerical intervals 330)
For new benchmark test value, and reset using new benchmark test value (it is, test value VA33) trigger pulse with
Preset error value.Wherein, new benchmark test value (it is, test value VA33) can by updated test section (it is,
Numerical intervals 330) it is divided into the first subinterval 331 and the second subinterval 332.
And so on, latched test device 100 can be continuously updated test section, and using updated test section come
Trigger pulse is reset, and then carries out the test of test chip 210 again.In addition, when the test result of test chip 210 is
Test chip 210 be in latch mode, and when the difference of latch critical value and benchmark test value is no more than preset error value, then such as
Shown in step S280, latched test device 100 will stop the test of test chip 210.In addition, latched test device 100 is final
Acquired latch critical value will can be used to define the integrated circuit in test chip 210 for the protective capacities of latch-up.
It is noted that since latched test device 100 can be continuously updated test section, latched test device
100 can expend the test that less testing time carrys out achievable test chip 210.For example, Fig. 4 is real for according to the present invention one
Apply the variation schematic diagram to illustrate change of the benchmark test value with test section of example.In Fig. 4 embodiment, initial survey
Examination section can be for example from 0~500mA.In the 1st test, 100 benchmark test value VA41 of latched test device (
It is exactly 250mA) latch is not in for test chip 210 to the test result that test chip 210 is tested, and analyzed
State, therefore latched test device 100 updates test using the upper half section (it is, first subinterval) in test section
Section.Whereby, in the 2nd test, latched test device 100 by can according to bigger benchmark test value VA42 (it is,
375mA) come to test chip 210 test.
In addition, the 2nd test result is that test chip 210 generates latch-up, and latch critical value and benchmark test
The difference of value is greater than preset error value.Therefore, latched test device 100 can using test section in lower half section (it is,
Second subinterval) update test section, and latch critical value is updated using benchmark test value VA42.Whereby, at the 3rd time
In test, latched test device 100 can come according to lesser benchmark test value VA43 (it is, 312.5mA) to test core
Piece 210 is tested.In addition, according to the 3rd test result, latched test device 100 can using benchmark test value VA43 come
Update latch critical value.
And so on, latched test device 100 can be continuously updated test section, and adjust benchmark test value accordingly.This
Outside, latched test device 100 can successively utilize benchmark test value VA44 (it is, 304.6875mA) and base according to test result
Quasi- test value VA45 (it is, 300.78125mA) Lai Gengxin latch critical value.In addition, latch is surveyed in the 9th test
Trial assembly set 100 can benchmark test value VA46 (it is, 299.8203125mA) to test chip 210 test.This
Outside, the 9th test result is that test chip 210 is in latch mode, and the difference of latch critical value and benchmark test value is not
Greater than preset error value (1mA).Therefore, latched test device 100 tests stopping test chip 210, and is finally taken
The latch critical value (it is, 300.78125mA) obtained will can be used to define the anti-latch of the integrated circuit in test chip 210
Ability.
It is noted that existing latched test method is gradually to be incremented by trigger pulse in a linear fashion.Therefore, to existing
For some latched test methods, must successively using 1mA, 2mA, 3mA ..., the trigger pulse of 300mA surveys to be repeated
Try the latched test of chip 210.In other words, 300 latched tests must be repeated in existing latched test method,
It is able to verify that the latch-up immunity of test chip 210.Therefore, for comparing existing latched test method, latched test device 100
The testing time of test chip 210 can be effectively reduced.In addition to this, latched test device 100 can be directly to wafer 200 to be measured
In test chip 210 tested, that is, latched test device 100 can for the chip manufacturing stage integrated circuit into
Row latched test.Therefore, in contrast with existing latched test method, latched test device 100 can also be effectively reduced collection
Production cost and production time at circuit.
In order to cause those of ordinary skill in the art that can know more about the present invention, below for the step S220 in Fig. 2
It is further illustrated with the thin portion step of step S230.For example, Fig. 5 is an embodiment according to the present invention to say
The detailed flowchart of bright step S220 and step S230.
For the thin portion step of step S220, as shown in step S510 and step S520, signal generator 110 be can provide
Supply voltage extremely tests the power supply weld pad of chip 210, and can provide trigger pulse to the input weld pad for testing chip 210.In addition,
As shown in step S530, before trigger pulse is provided and later, signal detection device 120 can be detected respectively and flow through power supply weld pad
Electric current, with obtain an at least detection signal in the first initial current and the first detecting current.
For example, Fig. 6 is the waveform diagram to illustrate latched test of an embodiment according to the present invention.Such as Fig. 6
Shown, in period T61~T63, signal generator 110 can provide the power supply weld pad of supply voltage 610 to test chip 210.
In addition, signal generator 110 can provide the input weld pad of trigger pulse 620 to test chip 210 in period T62.Furthermore
Before trigger pulse 620 is provided, that is, in period T61, signal detection device 120 can detect the electricity for flowing through power supply weld pad
Stream, to obtain the first initial current.After trigger pulse 620 is provided, that is, in period T63, signal detection device 120
The electric current for flowing through power supply weld pad can also be detected, to obtain the first detecting current.In addition, trigger pulse 620 can be for example Yi Zhengmai
Rush electric current.In another embodiment, trigger pulse 620 also can be for example a negative pulse current.
For the thin portion step of step S230, as shown in step S540, controller 130 may compare the first detecting current with
First initial current, to differentiate whether the first detecting current is greater than the first initial current.Furthermore when the first detecting current is greater than the
When one initial current, as shown in step S550, controller 130 can determine that test chip 210 is in latch mode.On the other hand,
When the first detecting current is not more than the first initial current, controller 130 can determine that test chip 210 is not at latch mode.
Fig. 7 is the detailed flowchart to illustrate step S220 Yu step S230 of another embodiment according to the present invention, and
Fig. 8 is the waveform diagram to illustrate latched test of an embodiment according to the present invention.With regard to step S220 thin portion step and
Speech, as shown in step S710, signal generator 110 can provide trigger pulse to the power supply weld pad for testing chip 210.Citing comes
It says, referring to Fig. 8, in period T82, signal generator 110 can provide the power supply weld pad of trigger pulse 810 to test chip 210,
And trigger pulse 810 can be for example a positive pulse voltage.
Furthermore as shown in step S720, before trigger pulse is provided and later, signal detection device 120 can be detectd respectively
Electric current of the flow measurement through power supply weld pad, to obtain initial current and detecting current in an at least detection signal.For example, reference
Fig. 8, before trigger pulse 810 is provided, that is, in period T81, signal detection device 120, which can be detected, flows through power supply weld pad
Electric current, to obtain initial current.After trigger pulse 810 is provided, that is, in period T83, signal detection device 120
The electric current for flowing through power supply weld pad can be detected, to obtain detecting current.
For the thin portion step of step S230, as shown in step S730, controller 130 can compare detecting current and initial
Electric current, to differentiate whether detecting current is greater than initial current.In addition, when detecting current is greater than initial current, such as step S740
Shown, controller 130 can determine that test chip 210 is in latch mode.On the other hand, when detecting current is no more than initial electricity
Stream, as shown in step S750, controller 130 can determine that test chip is not at latch mode.
In conclusion the adjustable test section of the present invention, and corresponding benchmark test value can be selected in response to test section,
To set the trigger pulse to test wafer to be measured whereby.Whereby, it will can be effectively reduced the testing time of wafer to be measured, from
And help to reduce the testing time.In addition, the present invention can carry out latched test for the integrated circuit in the chip manufacturing stage, because
This can be effectively reduced the production cost of integrated circuit and production time.
Although the present invention has been disclosed by way of example above, it is not intended to limit the present invention., any technical field
Middle those of ordinary skill, without departing from the spirit and scope of the present invention, when the change and modification that can make part, thus it is of the invention
Protection scope is subject to view as defined in claim.
Claims (8)
1. a kind of latched test method characterized by comprising
A setting operation is executed, to choose one as a benchmark test value from multiple test values that a test section is covered, and
A trigger pulse is set using the benchmark test value and the test section is divided into one by a preset error value, the benchmark test value
First subinterval and one second subinterval, the test value in first subinterval are greater than benchmark test value, second sub-district
Between in test value be less than benchmark test value；
The test chip in a wafer to be measured is tested using the trigger pulse, to obtain an at least detection signal；
Differentiate whether the test chip is in a latch mode according to an at least detection signal；
When the test chip is not in the latch mode, the test section is updated according to first subinterval, and return to execution
The step of setting operation；
When the test chip is in the latch mode, and the difference of a latch critical value and the benchmark test value is greater than this and default misses
When difference, the latch critical value and the test section are updated respectively according to the benchmark test value and second subinterval, and return to
The step of executing the setting operation；And
When the test chip is in the latch mode, and the difference of the latch critical value and the benchmark test value is default no more than this
When error amount, stop the test of the test chip.
2. latched test method according to claim 1, wherein testing being somebody's turn to do in the wafer to be measured using the trigger pulse
Chip is tested, includes: the step of an at least detection signal to obtain
One power supply weld pad of one supply voltage to the test chip is provided；
The one input weld pad of the trigger pulse to the test chip is provided；And
Before providing the trigger pulse and later, detecting flows through the electric current of the power supply weld pad respectively, and to obtain this, at least one is detectd
Survey one first initial current and one first detecting current in signal.
3. latched test method according to claim 2, wherein differentiating the test chip according to an at least detection signal
Whether be in the latch mode the step of include:
Compare first detecting current and first initial current；
When first detecting current is greater than first initial current, then determine that the test chip is in the latch mode；And
When first detecting current is not more than first initial current, then determine that the test chip is not at the latch mode.
4. latched test method according to claim 1, wherein testing being somebody's turn to do in the wafer to be measured using the trigger pulse
Chip is tested, includes: the step of an at least detection signal to obtain
The one power supply weld pad of the trigger pulse to the test chip is provided；
Before providing the trigger pulse and later, detecting flows through the electric current of the power supply weld pad respectively, and to obtain this, at least one is detectd
Survey the initial current and a detecting current in signal.
5. latched test method according to claim 4, wherein differentiating the test chip according to an at least detection signal
Whether be in the latch mode the step of include:
Compare the detecting current and the initial current；
When the detecting current is greater than the initial current, then determine that the test chip is in the latch mode；And
When the detecting current is not more than the initial current, then determine that the test chip is not at the latch mode.
6. a kind of latched test device characterized by comprising
One controller chooses one as a benchmark test value from multiple test values that a test section is covered, and utilizes the base
Quasi- test value sets a trigger pulse and a preset error value, and the test section is divided into one first son by the benchmark test value
Section and one second subinterval, the test value in first subinterval are greater than benchmark test value, in second subinterval
Test value is less than benchmark test value；
One signal generator generates the trigger pulse according to the benchmark test value, and the trigger pulse is sent to a crystalline substance to be measured
A test chip in circle, to cause the latched test device to carry out the test of the test chip；And
One signal detection device detects the signal from the test chip, to obtain an at least detection signal, and the controller foundation
An at least detection signal differentiates whether the test chip is in a latch mode,
When the test chip is not in the latch mode, which updates the test section according to first subinterval, and
The trigger pulse is reset according to the updated test section, to cause the latched test device to carry out the test core again
The test of piece,
When the test chip is in the latch mode, and the difference of a latch critical value and the benchmark test value is greater than this and default misses
When difference, which updates the latch critical value and the test section according to the benchmark test value and second subinterval respectively
Between, to cause the latched test device to carry out the test of the test chip again,
When the test chip is in the latch mode, and the difference of the latch critical value and the benchmark test value is default no more than this
When error amount, which stops the test of the test chip.
7. latched test device according to claim 6, wherein the signal generator provides a supply voltage to the test
One power supply weld pad of chip, and an input weld pad of the trigger pulse to the test chip is provided,
Before the trigger pulse is provided and later, which detects the electric current for flowing through the power supply weld pad respectively to take
One first initial current and one first detecting current in an at least detection signal are obtained,
The controller compares first detecting current and first initial current, when to be greater than this first initial for first detecting current
When electric current, then the controller determines that the test chip is in the latch mode, when first detecting current is no more than this at the beginning of first
When beginning electric current, then the controller determines that the test chip is not at the latch mode.
8. latched test device according to claim 6, wherein the signal generator provides the trigger pulse to the test
One power supply weld pad of chip,
Before the trigger pulse is provided and later, which detects the electric current for flowing through the power supply weld pad respectively, with
The initial current and a detecting current in an at least detection signal are obtained,
The controller compares the detecting current and the initial current, when the detecting current is greater than the initial current, then the control
Device determines that the test chip is in the latch mode, and when the detecting current is not more than the initial current, then the controller determines to be somebody's turn to do
Test chip is not at the latch mode.
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| CN108169661B (en) * | 2017-12-28 | 2020-07-10 | 天津芯海创科技有限公司 | Integrated circuit design method and integrated circuit latch-up test method |
| CN110501589A (en) * | 2019-08-14 | 2019-11-26 | 中国科学院近代物理研究所 | A kind of simulation of ASIC latch and protection system and method |
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| CN101398468A (en) * | 2008-10-16 | 2009-04-01 | 北京中星微电子有限公司 | Latch effect test method and system for CMOS chip |
| CN103297007A (en) * | 2012-02-28 | 2013-09-11 | 新加坡商格罗方德半导体私人有限公司 | Latch up detection |
| CN104375549A (en) * | 2014-10-30 | 2015-02-25 | 中国电子科技集团公司第三十六研究所 | Latching-preventing circuit of CMOS device |
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