CN106324477A - Latch testing apparatus and method - Google Patents

Abstract

The invention provides a latch testing device and a method, and the latch testing method comprises the following steps: executing a setting operation to set a reference test value according to the test interval, and setting a trigger pulse and a preset error value by using the reference test value; testing a test chip in the wafer to be tested by using the trigger pulse, and judging whether the test chip is in a latch state; determining whether to update the test interval and the latch critical value and whether to return to executing the setting operation according to the judgment result, the latch critical value and the reference test value; and when the test chip is in a latch state and the difference value between the latch critical value and the reference test value is not greater than the preset error value, stopping the test of the test chip.

Description

Latch-up testing device and method

technical field

The present invention relates to a latch-up testing device and method, and in particular to a latch-up testing device and method for testing wafers to be tested.

Background technique

Latch-up effect (Latch-up effect) is an important factor affecting the reliability of integrated circuits. Therefore, most integrated circuits are tested for latch-up resistance before leaving the factory. Generally speaking, the manufacturing process of integrated circuits includes circuit design, chip manufacturing and chip packaging. In addition, the existing latch-up testing method uses linearly increasing trigger pulses to perform latch-up testing on integrated circuits in the chip packaging stage. However, since the trigger pulses are gradually increased in a linear manner, the existing latch-up testing method usually consumes a huge amount of testing time to complete the test of the latch-up resistance of the integrated circuit. In addition, since the existing latch-up test method can only test the integrated circuit at the chip packaging stage, manufacturers often have to wait until the final stage of the integrated circuit manufacturing process before deciding whether to re-make the integrated circuit, which leads to The production cost and production time of integrated circuits increase.

Contents of the invention

The invention provides a latch testing device and method, which can reduce testing time and help to reduce production cost and production time.

The latch testing method of the present invention includes the following steps. Executing a setting operation to select one of a plurality of test values covered by the test interval as a benchmark test value, and use the benchmark test value to set a trigger pulse and a preset error value. Wherein, the benchmark test value divides the test interval into a first subinterval and a second subinterval. The test chip in the wafer to be tested is tested by using the trigger pulse to obtain at least one detection signal. It is judged whether the test chip is in a latched state according to at least one detection signal. When the test chip is not in the latched state, update the test interval according to the first sub-interval, and return to the step of performing the setting operation. When the test chip is in the latch state, and the difference between the latch threshold value and the benchmark test value is greater than the preset error value, update the latch threshold value and the test interval according to the benchmark test value and the second sub-interval respectively, and return to Perform the procedure for setting operations. When the test chip is in the latch state and the difference between the latch threshold value and the benchmark test value is not greater than the preset error value, the test of the test chip is stopped.

The latch testing device of the present invention includes a controller, a signal generator and a signal detector. The controller selects one of the multiple test values covered by the test interval as the benchmark test value, and uses the benchmark test value to set the trigger pulse and the preset error value, and the benchmark test value divides the test interval into the first sub-interval and the second sub-interval. Two sub-intervals. The signal generator generates a trigger pulse according to the reference test value, and transmits the trigger pulse to the test chip in the wafer to be tested, so that the latch test device can test the test chip. The signal detector detects the signal from the test chip to obtain at least one detection signal, and the controller judges whether the test chip is in a latch state according to the at least one detection signal. When the test chip is not in the latch state, the controller updates the test interval according to the first sub-interval, and resets the trigger pulse according to the updated test interval, so that the latch test device tests the test chip again. When the test chip is in the latch state, and the difference between the latch threshold value and the reference test value is greater than the preset error value, the controller updates the latch threshold value and the test interval according to the reference test value and the second sub-interval, so that The latch-up testing device performs the test of the test chip again. When the test chip is in the latch state and the difference between the latch threshold value and the reference test value is not greater than the preset error value, the latch test device stops testing the test chip.

Based on the above, the present invention can adjust the test interval, and select the corresponding benchmark test value according to the test interval, so as to set the trigger pulse for testing the wafer to be tested. Thereby, the test time can be reduced, and the production cost and production time can be reduced.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

Description of drawings

FIG. 1 is a schematic diagram of a latch-up testing device according to an embodiment of the invention.

FIG. 2 is a flowchart of a latch-up testing method according to an embodiment of the invention.

FIG. 3 is a schematic diagram illustrating the adjustment of a test interval according to an embodiment of the present invention.

FIG. 4 is a schematic diagram illustrating changes of benchmark test values with changes in test intervals according to an embodiment of the present invention.

FIG. 5 is a detailed flowchart illustrating step S220 and step S230 according to an embodiment of the present invention.

FIG. 6 is a schematic diagram illustrating waveforms of a latch-up test according to an embodiment of the invention.

FIG. 7 is a detailed flowchart illustrating step S220 and step S230 according to yet another embodiment of the present invention.

FIG. 8 is a schematic diagram of waveforms illustrating a latch-up test according to an embodiment of the invention.

【Symbol Description】

100: Latch-up test device

110: Signal generator

120: Signal Detector

200: Wafer to be tested

210: Test chip

S210～S270: the steps in the embodiment in Figure 2

VH3, VL3, VA31～VA33: test value

310~330: Numerical range

311, 321, 331: the first subinterval

312, 322, 332: the second subinterval

VA41～VA46: Benchmark test value

S510～S560: the steps in the embodiment in Figure 5

T61～T63, T81～T83: period

610: supply voltage

620, 810: trigger pulse

S710～S750: the steps in the embodiment of Figure 7

detailed description

FIG. 1 is a schematic diagram of a latch-up testing device according to an embodiment of the invention. As shown in FIG. 1 , the latch-up testing device 100 may be a testing machine for testing the wafer 200 to be tested. Wherein, the wafer 200 to be tested includes a test chip 210 , and the test chip 210 includes an integrated circuit. The latch-up testing device 100 can be electrically connected to the wafer 200 to be tested through probes on a probe card (not shown), so as to perform various tests on the integrated circuits in the test chip 210 on the wafer 200 to be tested, For example latch-up testing.

The latch-up testing device 100 includes a signal generator 110 , a signal detector 120 and a controller 130 . The signal generator 110 can generate trigger pulses and transmit the trigger pulses to the test chip 210 through the probes. In addition, the controller 130 can adjust the size of the trigger pulse (for example, vibration) according to the reference test value, so as to simulate various trigger sources that may cause the test chip 210 to generate latch-up. The signal detector 120 can detect the signal on the test chip 210 through probes for the controller 130 to analyze the characteristics or status of the test chip 210 , so as to verify the latch-up resistance of the integrated circuits in the test chip 210 .

FIG. 2 is a flowchart of a latch-up testing method according to an embodiment of the present invention, and the latch-up testing performed by the latch-up testing device 100 on the wafer 200 to be tested will be further described below with reference to FIG. 1 and FIG. 2 . As shown in step S210 , the latch-up testing device 100 can perform a setting operation, so as to set the reference test value, the trigger pulse and the preset error value. Specifically, the controller 130 in the latch-up testing device 100 can select one of a plurality of test values covered by a test interval as a reference test value, and use the reference test value to set a trigger pulse and a preset error value. Wherein, the benchmark test value divides the test interval into a first subinterval and a second subinterval.

For example, FIG. 3 is a schematic diagram illustrating the adjustment of the test interval according to an embodiment of the present invention. As shown in FIG. 3 , the test interval can be, for example, a numerical interval 310 from the test value VL3 to the test value VH3 . The controller 130 can set the test value VA31 located in the value range 310 as the reference test value, and then can set the trigger pulse according to the reference test value. In addition, the controller 130 can take the reference test value VA31 into an expression to calculate the preset error value. For example, if VA31=a×10 ^b , the calculated preset error value can be expressed as 10 ^(b−2) , where 1≦a<10 and b is an integer. That is, when VA31=300mA, the preset error value is equal to 1mA. When VA31=20mA, the preset error value is equal to 0.1mA. Furthermore, the benchmark test value VA31 can divide the numerical interval 310 into a first sub-interval 311 and a second sub-interval 312, and the test value in the first sub-interval 311 is greater than the benchmark test value VA31, and the test value in the second sub-interval 312 The value is smaller than the benchmark value VA31.

As shown in step S220, the signal generator 110 can generate a trigger pulse according to the reference test value. In addition, the signal generator 110 can transmit trigger pulses to the test chip 210 so that the latch test device 100 can test the test chip 210 . The signal detector 120 can detect the signal from the test chip 210 and generate at least one detection signal accordingly. Moreover, as shown in step S230 and step S240, the controller 130 can judge whether the test chip 210 is in the latch state according to the at least one detection signal, and can judge whether the difference between the latch threshold value and the reference test value is greater than Default error value.

When the controller 130 determines that the test chip 210 is not in the latched state, that is, when the integrated circuit in the test chip 210 does not produce a latch-up effect, as shown in step S250, the controller 130 may update the test interval according to the first sub-interval, And return to step S210. For example, as shown in FIG. 3 , when the test result obtained by using the test value VA31 is that the test chip 210 does not produce a latch-up effect, the controller 130 can update the test interval according to the first sub-interval 311, thereby causing the test interval It is updated to a numerical interval 320 from the test value VA31 to the test value VH3. In addition, the latch test device 100 can repeat step S210 to select the test value VA32 from the updated test interval (that is, the value interval 320) as a new benchmark test value, and use the new benchmark test value (also That is, test the value VA32) to reset the trigger pulse and preset error value. Wherein, the new benchmark test value (that is, the test value VA32 ) can divide the updated test interval (that is, the numerical interval 320 ) into a first subinterval 321 and a second subinterval 322 .

Furthermore, the latch-up testing device 100 may repeat steps S210 - S230 to test the test chip 210 again by using the reset trigger pulse, and analyze the test result of the test chip 210 again. On the other hand, when the controller 130 determines that the test chip 210 is in a latched state (that is, the integrated circuit in the test chip 210 produces a latch-up effect), and the difference between the latch threshold value and the reference test value is greater than the preset error value At this time, as shown in steps S260 and S270, the controller 130 may update the latch threshold value according to the benchmark test value, and may update the test interval according to the second sub-interval.

For example, as shown in FIG. 3 , when the test result obtained by using the test value VA32 produces a latch-up effect for the test chip 210, and the difference between the latch-up threshold value and the reference test value is greater than a preset error value, the controller 130 can update the latch threshold value according to the reference test value (that is, the test value VA32), and can update the test interval according to the second sub-interval 322, thereby causing the test interval to be updated to a value from the test value VA31 to the test value VA32 Interval 330. In addition, the latch test device 100 can repeat step S210 to select the test value VA33 from the updated test interval (that is, the numerical interval 330) as a new benchmark test value, and use the new benchmark test value (that is, , test value VA33) to reset the trigger pulse and preset error value. Wherein, the new benchmark test value (that is, the test value VA33 ) can divide the updated test interval (that is, the numerical interval 330 ) into a first subinterval 331 and a second subinterval 332 .

By analogy, the latch test device 100 can continuously update the test interval, and use the updated test interval to reset the trigger pulse, and then test the test chip 210 again. In addition, when the test result of the test chip 210 is that the test chip 210 is in the latch state, and the difference between the latch threshold value and the reference test value is not greater than the preset error value, as shown in step S280, the latch test device 100 Testing of the test chip 210 will be stopped. In addition, the latch-up threshold finally obtained by the latch-up testing device 100 can be used to define the protection capability of the integrated circuits in the test chip 210 against the latch-up effect.

It is worth mentioning that since the latch-up testing device 100 can continuously update the test interval, the latch-up testing device 100 can complete the testing of the test chip 210 with less testing times. For example, FIG. 4 is a schematic diagram illustrating the change of the benchmark test value as the test interval changes according to an embodiment of the present invention. In the embodiment of FIG. 4 , the initial test interval may be, for example, from 0 to 500 mA. In the first test, the latch test device 100 tests the test chip 210 according to the reference test value VA41 (that is, 250mA), and the analyzed test result shows that the test chip 210 is not in the latch state, so the latch The lock testing device 100 uses the upper half of the test interval (ie, the first sub-interval) to update the test interval. Thereby, in the second test, the latch-up test device 100 can test the test chip 210 according to a larger reference test value VA42 (ie, 375mA).

In addition, the result of the second test is that the test chip 210 has a latch-up effect, and the difference between the latch-up threshold value and the reference test value is greater than a preset error value. Therefore, the latch-up testing device 100 may use the lower half of the test interval (ie, the second sub-interval) to update the test interval, and use the reference test value VA42 to update the latch threshold. Thereby, in the third test, the latch-up test device 100 can test the test chip 210 according to the smaller reference test value VA43 (ie, 312.5mA). In addition, according to the third test result, the latch-up testing device 100 can use the reference test value VA43 to update the latch-up threshold.

By analogy, the latch test device 100 can continuously update the test interval and adjust the benchmark test value accordingly. In addition, the latch-up testing device 100 may sequentially use the reference test value VA44 (ie, 304.6875mA) and the reference test value VA45 (ie, 300.78125mA) to update the latch-up threshold according to the test results. In addition, in the ninth test, the latch-up test device 100 can test the test chip 210 according to the reference test value VA46 (ie, 299.8203125 mA). In addition, the ninth test result is that the test chip 210 is in a latched state, and the difference between the latched threshold value and the reference test value is not greater than a preset error value (1mA). Therefore, the latch-up testing device 100 will stop the testing of the test chip 210 , and the finally obtained latch-up threshold value (ie, 300.78125 mA) can be used to define the latch-up resistance capability of the integrated circuits in the test chip 210 .

It is worth mentioning that the existing latch-up testing method is to gradually increase the trigger pulse in a linear fashion. Therefore, for the existing latch-up testing method, the trigger pulses of 1mA, 2mA, 3mA, . In other words, in the existing latch-up testing method, the latch-up test must be repeated 300 times to verify the latch-up resistance of the test chip 210 . Therefore, compared with the existing latch-up testing method, the latch-up testing device 100 can effectively reduce the testing time of the testing chip 210 . In addition, the latch-up testing device 100 can directly test the test chip 210 in the wafer 200 to be tested, that is, the latch-up testing device 100 can perform a latch-up test on integrated circuits in the chip manufacturing stage. Therefore, compared with the existing latch-up testing method, the latch-up testing device 100 can also effectively reduce the production cost and production time of the integrated circuit.

In order to enable those skilled in the art to better understand the present invention, the detailed steps of step S220 and step S230 in FIG. 2 will be further described below. For example, FIG. 5 is a detailed flowchart for illustrating step S220 and step S230 according to an embodiment of the present invention.

As for the detailed steps of step S220 , as shown in steps S510 and S520 , the signal generator 110 may provide a power supply voltage to the power pad of the test chip 210 , and may provide a trigger pulse to the input pad of the test chip 210 . In addition, as shown in step S530, before and after the trigger pulse is provided, the signal detector 120 can respectively detect the current flowing through the power supply pad, so as to obtain the first initial current and the first initial current in at least one detection signal. detect current.

For example, FIG. 6 is a schematic diagram of waveforms for illustrating a latch-up test according to an embodiment of the present invention. As shown in FIG. 6 , during the period T61 - T63 , the signal generator 110 can provide a power supply voltage 610 to the power pads of the test chip 210 . In addition, during the period T62 , the signal generator 110 may provide a trigger pulse 620 to the input pad of the test chip 210 . Furthermore, before the trigger pulse 620 is provided, that is, within the period T61 , the signal detector 120 can detect the current flowing through the power pad to obtain the first initial current. After the trigger pulse 620 is provided, that is, within the period T63, the signal detector 120 can also detect the current flowing through the power pad to obtain the first detection current. In addition, the trigger pulse 620 can be, for example, a positive pulse current. In another embodiment, the trigger pulse 620 may also be, for example, a negative pulse current.

Regarding the detailed steps of step S230, as shown in step S540, the controller 130 can compare the first detection current with the first initial current to determine whether the first detection current is greater than the first initial current. Furthermore, when the first detection current is greater than the first initial current, as shown in step S550 , the controller 130 may determine that the test chip 210 is in a latch state. On the other hand, when the first detection current is not greater than the first initial current, the controller 130 can determine that the test chip 210 is not in the latch state.

FIG. 7 is a detailed flow chart illustrating step S220 and step S230 according to another embodiment of the present invention, and FIG. 8 is a schematic waveform diagram illustrating a latch test according to an embodiment of the present invention. Regarding the detailed steps of step S220 , as shown in step S710 , the signal generator 110 may provide trigger pulses to the power pads of the test chip 210 . For example, referring to FIG. 8 , during the period T82 , the signal generator 110 may provide a trigger pulse 810 to the power pad of the test chip 210 , and the trigger pulse 810 may be, for example, a positive pulse voltage.

Furthermore, as shown in step S720, before and after the trigger pulse is provided, the signal detector 120 can respectively detect the current flowing through the power supply pad, so as to obtain the initial current and the detection current in at least one detection signal . For example, referring to FIG. 8 , before the trigger pulse 810 is provided, that is, during the period T81 , the signal detector 120 can detect the current flowing through the power pad to obtain the initial current. After the trigger pulse 810 is provided, that is, within the period T83, the signal detector 120 can detect the current flowing through the power pad to obtain the detection current.

Regarding the detailed steps of step S230, as shown in step S730, the controller 130 compares the detected current with the initial current to determine whether the detected current is greater than the initial current. In addition, when the detected current is greater than the initial current, as shown in step S740 , the controller 130 may determine that the test chip 210 is in a latched state. On the other hand, when the detected current is not greater than the initial current, as shown in step S750 , the controller 130 can determine that the test chip is not in the latch state.

To sum up, the present invention can adjust the test interval, and can select the corresponding benchmark test value according to the test interval, so as to set the trigger pulse for testing the wafer to be tested. Thereby, the times of testing the wafer to be tested can be effectively reduced, thereby helping to reduce the testing time. In addition, the present invention can perform latch-up test on the integrated circuit in the chip manufacturing stage, so the production cost and production time of the integrated circuit can be effectively reduced.

Although the present invention has been disclosed as above with the embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make partial changes and modifications without departing from the spirit and scope of the present invention. Therefore, this The scope of protection of the invention should be defined by the claims.

Claims (8)

1. A latch-up testing method, characterized in that, comprising: Executing a setting operation to select one of a plurality of test values covered by a test interval as a benchmark test value, and using the benchmark test value to set a trigger pulse and a preset error value, the benchmark test value will be The test interval is divided into a first sub-interval and a second sub-interval; using the trigger pulse to test a test chip in a wafer to be tested to obtain at least one detection signal; judging whether the test chip is in a latch state according to the at least one detection signal; When the test chip is not in the latch state, update the test interval according to the first sub-interval, and return to the step of performing the setting operation; When the test chip is in the latch state and the difference between a latch threshold value and the reference test value is greater than the preset error value, the latch threshold value is updated according to the reference test value and the second sub-interval respectively and the test interval, and return to the step of performing the set operation; and When the test chip is in the latch state and the difference between the latch threshold value and the benchmark test value is not greater than the preset error value, the test of the test chip is stopped. 2. The latch-up testing method according to claim 1, wherein using the trigger pulse to test the test chip in the wafer to be tested to obtain the at least one detection signal comprises: providing a power supply voltage to a power pad of the test chip; providing the trigger pulse to an input pad of the test chip; and Before and after the trigger pulse is provided, the current flowing through the power pad is respectively detected to obtain a first initial current and a first detection current in the at least one detection signal. 3. The latch-up testing method according to claim 2, wherein the step of judging whether the test chip is in the latch-up state according to the at least one detection signal comprises: comparing the first detection current with the first initial current; When the first detection current is greater than the first initial current, it is determined that the test chip is in the latch state; and When the first detection current is not greater than the first initial current, it is determined that the test chip is not in the latch state. 4. The latch-up testing method according to claim 1, wherein the step of using the trigger pulse to test the test chip in the wafer to be tested to obtain the at least one detection signal comprises: providing the trigger pulse to a power pad of the test chip; Before and after the trigger pulse is provided, the current flowing through the power pad is respectively detected to obtain an initial current and a detection current in the at least one detection signal. 5. The latch-up testing method according to claim 4, wherein the step of judging whether the test chip is in the latch-up state according to the at least one detection signal comprises: comparing the detected current with the initial current; When the detection current is greater than the initial current, it is determined that the test chip is in the latch state; and When the detection current is not greater than the initial current, it is determined that the test chip is not in the latch state. 6. A latch test device, characterized in that it comprises: A controller selects one of a plurality of test values covered by a test interval as a benchmark test value, and uses the benchmark test value to set a trigger pulse and a preset error value, and the benchmark test value will test the The interval is divided into a first subinterval and a second subinterval; a signal generator, which generates the trigger pulse according to the reference test value, and transmits the trigger pulse to a test chip in a wafer to be tested, so as to cause the latch test device to test the test chip; and A signal detector detects a signal from the test chip to obtain at least one detection signal, and the controller judges whether the test chip is in a latch state according to the at least one detection signal, When the test chip is not in the latch state, the controller updates the test interval according to the first sub-interval, and resets the trigger pulse according to the updated test interval, so that the latch test device performs again The test chip is tested, When the test chip is in the latch state and the difference between a latch threshold value and the reference test value is larger than the preset error value, the controller updates the latch according to the reference test value and the second sub-interval respectively. lock critical value and the test interval, so that the latch test device performs the test of the test chip again, When the test chip is in the latch state and the difference between the latch threshold value and the reference test value is not greater than the preset error value, the latch test device stops testing the test chip. 7. The latch-up testing device according to claim 6, wherein the signal generator provides a power supply voltage to a power pad of the test chip, and provides the trigger pulse to an input pad of the test chip, Before and after the trigger pulse is provided, the signal detector respectively detects the current flowing through the power pad to obtain a first initial current and a first detection current in the at least one detection signal, The controller compares the first detection current with the first initial current. When the first detection current is greater than the first initial current, the controller determines that the test chip is in the latch state. When the first When the detection current is not greater than the first initial current, the controller determines that the test chip is not in the latch state. 8. The latch-up testing device according to claim 6, wherein the signal generator provides the trigger pulse to a power pad of the test chip, Before and after the trigger pulse is provided, the signal detector respectively detects the current flowing through the power supply pad to obtain an initial current and a detection current in the at least one detection signal, The controller compares the detection current with the initial current, and when the detection current is greater than the initial current, the controller determines that the test chip is in the latch state, and when the detection current is not greater than the initial current, then The controller determines that the test chip is not in the latch state.