CN106324477A - Latch testing device and method - Google Patents
Latch testing device and method Download PDFInfo
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- CN106324477A CN106324477A CN201510392652.9A CN201510392652A CN106324477A CN 106324477 A CN106324477 A CN 106324477A CN 201510392652 A CN201510392652 A CN 201510392652A CN 106324477 A CN106324477 A CN 106324477A
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Abstract
The invention provides a latch testing device and method. The testing method comprises: a setting operation is executed, a reference testing value is set based on a testing zone, and a trigger pulse and a preset error are set based on the reference testing value; a testing chip of a to-be-measured wafer is tested by using the trigger pulse and whether the testing chip is in a latching state is determined; according to a determination result, a latching critical value, and the reference testing value, whether the testing zone and the latching critical value are updated and whether returning to execution of the setting operation is carried out is decided; and when the testing chip is in the latching state and a difference value between the latching critical value and the reference testing value is not larger than a preset error value, testing of the testing chip is stopped.
Description
Technical field
The invention relates to a kind of latched test apparatus and method, and can use in particular to one
To test the latched test apparatus and method of wafer to be measured.
Background technology
Latch-up (Latch-up effect) is a key factor of the reliability affecting integrated circuit,
Therefore integrated circuit all can carry out the test of latch-up immunity before dispatching from the factory mostly.It is said that in general, it is integrated
The manufacturing process of circuit includes circuit design, chip manufacturing and chip package.Additionally, existing breech lock
Method of testing is to utilize the triggering pulse of linear increment, carries out the integrated circuit in the chip package stage
Latched test.But, it is the most gradually to be incremented by owing to triggering pulse, the most existing breech lock
Method of testing often must expend the huge testing time and just can complete integrated circuit latch-up immunity
Test.Additionally, due to existing latched test method is only capable of for the integrated electricity in the chip package stage
Road is tested, and therefore manufacturer often must wait until integrated circuit final stage in the fabrication process,
Just can decide whether to again make integrated circuit, and then cause production cost and the production of integrated circuit
The increase of time.
Summary of the invention
The present invention provides a kind of latched test apparatus and method, it is possible to decrease the testing time, and contributes to contracting
Subtract production cost and production time.
The latched test method of the present invention, comprises the following steps.Perform setting operation, with from test section
Between multiple test values of being contained choose one as benchmark test value, and utilize benchmark test value to set to touch
Send out pulse and preset error value.Wherein, benchmark test value test interval is divided into the first subinterval with
Second subinterval.Utilize the test chip triggered in pulse test wafer to be measured, detect with acquirement at least
Survey signal.Differentiate whether test chip is in latch mode according at least one detection signal.When test core
When sheet is not in latch mode, updates test interval according to the first subinterval, and return to perform to set behaviour
The step made.When test chip is in latch mode, and the difference of breech lock marginal value and benchmark test value
During more than preset error value, benchmark test value and the second subinterval update respectively breech lock marginal value with
This test is interval, and returns to perform the step of setting operation.When test chip is in latch mode, and
When the difference of breech lock marginal value and benchmark test value is not more than preset error value, stop the survey of test chip
Examination.
The latched test device of the present invention, including controller, signal generator and signal detection device.Control
Device processed chooses one as benchmark test value from multiple test values that test interval is contained, and utilizes benchmark
Test value sets and triggers pulse and preset error value, and test interval is divided into first by benchmark test value
Subinterval and the second subinterval.Signal generator benchmark test value produces and triggers pulse, and will touch
Send out the test chip that pulse is sent in wafer to be measured, test chip to cause latched test device to carry out
Test.The detecting of signal detection device carrys out the signal of self-test chip, to obtain at least one detection signal,
And according at least one detection signal, controller differentiates whether test chip is in latch mode.When test core
When sheet is not in latch mode, controller updates test interval according to the first subinterval, and according to updating
After test interval reset triggering pulse, with cause latched test device again carry out test chip
Test.When test chip is in latch mode, and breech lock marginal value is big with the difference of benchmark test value
When preset error value, it is critical that controller benchmark test value and the second subinterval update breech lock respectively
Value and test interval, test the test of chip to cause latched test device again to carry out.When test core
Sheet is in latch mode, and when the difference of breech lock marginal value and benchmark test value is not more than preset error value,
Latched test device stops the test of test chip.
Based on above-mentioned, adjustable of the present invention test interval, and correspondence can be selected in response to test interval
Benchmark test value, to set to test the triggering pulse of wafer to be measured whereby.Whereby, can reduce
Testing time, and contribute to reducing production cost and production time.
For the features described above of the present invention and advantage can be become apparent, special embodiment below, and join
Close appended accompanying drawing to be described in detail below.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the latched test device according to one embodiment of the invention.
Fig. 2 is the flow chart of the latched test method according to one embodiment of the invention.
Fig. 3 be according to one embodiment of the invention in order to the interval schematic diagram on adjusting of test to be described.
Fig. 4 be according to one embodiment of the invention in order to illustrate that benchmark test value is along with interval the changing of test
The variation schematic diagram become.
Fig. 5 is the thin portion in order to step S220 and step S230 to be described according to one embodiment of the invention
Flow chart.
Fig. 6 is the waveform diagram in order to latched test to be described according to one embodiment of the invention.
Fig. 7 be according to further embodiment of this invention in order to the thin of step S220 and step S230 to be described
Portion's flow chart.
Fig. 8 is the waveform diagram in order to latched test to be described according to one embodiment of the invention.
[symbol description]
100: latched test device
110: signal generator
120: signal detection device
200: wafer to be measured
210: test chip
Step in S210～S270: Fig. 2 embodiment
VH3, VL3, VA31～VA33: test value
310～330: numerical intervals
311,321,331: the first subinterval
312,322,332: the second subinterval
VA41～VA46: benchmark test value
Step in S510～S560: Fig. 5 embodiment
T61～T63, T81～T83: period
610: supply voltage
620,810: trigger pulse
Step in S710～S750: Fig. 7 embodiment
Detailed description of the invention
Fig. 1 is the schematic diagram of the latched test device according to one embodiment of the invention.As it is shown in figure 1,
Latched test device 100 can be in this way in order to test the tester table of wafer 200 to be measured.Wherein, to be measured
Wafer 200 includes integrated circuit in including testing chip 210, and test chip 210.Latched test
Device 100 can be electrically connected to wafer 200 to be measured by the probe passed through in probe card (not showing),
So that the integrated circuit in the test chip 210 on wafer 200 to be measured is carried out various test, such as, fasten with a bolt or latch
Lock test.
Latched test device 100 includes signal generator 110, signal detection device 120 and controller 130.
Signal generator 110 can produce triggering pulse, and can transmit triggering pulse to testing chip by probe
210.Additionally, (such as, controller 130 can adjust the size of triggering pulse by benchmark test value
Shake good fortune), to emulate the various trigger sources that test chip 210 can be caused to produce latch-up whereby.Letter
Number detector 120 can be by probe detecting signal on test chip 210, for controller 130
The characteristic of analysis test chip 210 or state etc., thus the integrated electricity in validation test chip 210
The latch-up immunity on road.
Fig. 2 is the flow chart of the latched test method according to one embodiment of the invention, and below will simultaneously
Illustrate that with reference to Fig. 1 with Fig. 2 wafer 200 to be measured is carried out by latched test device 100 further
Latched test.As shown in step S210, latched test device 100 can perform setting operation, with
Set benchmark test value whereby, trigger pulse and preset error value.Specifically, latched test device
Controller 130 in 100 can choose one as benchmark from multiple test values that a test interval is contained
Test value, and utilize benchmark test value to set triggering pulse and preset error value.Wherein, benchmark test
Test interval is divided into the first subinterval and the second subinterval by value.
For example, Fig. 3 be according to one embodiment of the invention in order to illustrate that test is interval on adjusting
Schematic diagram.As it is shown on figure 3, test interval can be for example from test value VL3 to test value VH3
Numerical intervals 310.The test value VA31 that controller 130 can will be located in numerical intervals 310 sets
It is set to benchmark test value, and then triggering pulse can be set by benchmark test value.Additionally, controller
Benchmark test value VA31 can be brought into an expression formula to calculate preset error value by 130.Such as, if
If VA31=a × 10b, the preset error value calculated is represented by 10(b-2), wherein 1≤a ＜ 10 and
B is integer.It is, as VA31=300mA, preset error value is equal to 1mA.When
During VA31=20mA, preset error value is equal to 0.1mA.Furthermore, benchmark test value VA31 can
Numerical intervals 310 is divided into the first subinterval 311 and the second subinterval 312, and the first subinterval
Test value in 311 is more than benchmark test value VA31, and the test value in the second subinterval 312 is less than base
Quasi-test value VA31.
As shown in step S220, signal generator 110 can produce triggering pulse by benchmark test value.
Additionally, signal generator 110 can be sent to test chip 210 by triggering pulse, in order to latched test
Device 100 carries out testing the test of chip 210.Signal detection device 120 can detect self-test chip
The signal of 210 also produces at least one detection signal according to this.Furthermore, such as step S230 and step S240
Shown in, according to described at least one detection signal, controller 130 can differentiate whether test chip 210 is in
Latch mode, and can differentiate that whether the breech lock marginal value difference with benchmark test value is more than preset error value.
When controller 130 discriminating test chip 210 is not in latch mode, namely test chip
When integrated circuit in 210 does not produces latch-up, as shown in step S250, controller 130 can depend on
Update test interval according to the first subinterval, and return to step S210.For example, as it is shown on figure 3,
When utilizing the test result acquired by test value VA31 not produce latch-up for test chip 210,
Controller 130 can update test interval according to the first subinterval 311, and then causes the interval quilt of test
It is updated to the numerical intervals 320 from test value VA31 to test value VH3.Additionally, latched test dress
Put 100 repeatable steps S210, interval (it is, numerical intervals 320) with the test after updating
In select test value VA32 and be used as new benchmark test value, and utilize new benchmark test value (also
It is exactly, test value VA32) reset triggering pulse and preset error value.Wherein, new base
Quasi-test value (it is, test value VA32) can be interval by the test after updating (it is, count
Value interval 320) it is divided into the first subinterval 321 and the second subinterval 322.
Furthermore, repeatable step S210 of latched test device 100～S230, after resetting with utilization
Trigger pulse again carry out test chip 210 test, and again analyze test chip 210 survey
Test result.On the other hand, (the most just it is in latch mode when controller 130 discriminating test chip 210
It is that the integrated circuit in test chip 210 produces latch-up), and breech lock marginal value and benchmark survey
When the difference of examination value is more than preset error value, as shown in step S260 and step S270, controller
130 can update breech lock marginal value by benchmark test value, and can be according to the second renewal test section, subinterval
Between.
For example, as it is shown on figure 3, work as and utilize the test result acquired by test value VA32 for surveying
Examination chip 210 produces latch-up, and breech lock marginal value is missed more than default with the difference of benchmark test value
During difference, controller 130 can update door bolt by benchmark test value (it is, test value VA32)
Lock marginal value, and test interval can be updated according to the second subinterval 322, and then cause test interval
It is updated to the numerical intervals 330 from test value VA31 to test value VA32.Additionally, breech lock is surveyed
Repeatable step S210 of electricity testing device 100, interval (it is, numerical intervals with the test after updating
330) select test value VA33 in as new benchmark test value, and utilize new benchmark test value (also
It is exactly, test value VA33) reset triggering pulse and preset error value.Wherein, new base
Quasi-test value (it is, test value VA33) can be interval by the test after updating (it is, count
Value interval 330) it is divided into the first subinterval 331 and the second subinterval 332.
By that analogy, latched test device 100 can be continuously updated test interval, and after utilizing renewal
Test interval reset triggering pulse, and then again carry out testing the test of chip 210.This
Outward, when the test result of test chip 210 is in latch mode for test chip 210, and breech lock faces
When the difference of dividing value and benchmark test value is not more than preset error value, then as shown in step S280, door bolt
Lock test device 100 will stop the test of test chip 210.Additionally, latched test device 100 is
Breech lock marginal value acquired by end defines the integrated circuit in test chip 210 for breech lock by may be used to
The protective capacities of effect.
It is noted that owing to latched test device 100 can be continuously updated test interval, therefore
Latched test device 100 can expend the test that less testing time to complete to test chip 210.
For example, Fig. 4 be according to one embodiment of the invention in order to illustrate that benchmark test value is along with test section
Between the variation schematic diagram of change.In Fig. 4 embodiment, initial test interval can be for example from
0～500mA.In the test of the 1st time, latched test device 100 benchmark test value VA41
Test chip 210 is tested by (it is, 250mA), and the test result analyzed is
Test chip 210 is not in latch mode, during therefore latched test device 100 utilizes test interval
Upper half interval (it is, first subinterval) updates test interval.Whereby, the survey of the 2nd time
In examination, latched test device 100 is by can be according to bigger benchmark test value VA42 (it is, 375mA)
Test chip 210 is tested.
Additionally, the test result of the 2nd time produces latch-up for test chip 210, and breech lock is critical
Value is more than preset error value with the difference of benchmark test value.Therefore, latched test device 100 may utilize
Lower half interval (it is, second subinterval) in test interval updates test interval, and utilizes
Benchmark test value VA42 updates breech lock marginal value.Whereby, in the test of the 3rd time, breech lock is surveyed
Electricity testing device 100 will be able to come survey according to less benchmark test value VA43 (it is, 312.5mA)
Examination chip 210 is tested.Additionally, according to the test result of the 3rd time, latched test device 100
Available benchmark test value VA43 updates breech lock marginal value.
By that analogy, latched test device 100 can be continuously updated test interval, and adjusts base according to this
Quasi-test value.Additionally, latched test device 100 can utilize benchmark test value successively according to test result
VA44 (it is, 304.6875mA) and benchmark test value VA45 (it is, 300.78125mA)
Update breech lock marginal value.Additionally, in the test of the 9th time, latched test device 100 can foundation
Test chip 210 is tested by benchmark test value VA46 (it is, 299.8203125mA).
Additionally, the test result of the 9th time is in latch mode for test chip 210, and breech lock marginal value with
The difference of benchmark test value is not more than preset error value (1mA).Therefore, latched test device 100
Stopping test chip 210 is tested, and final acquired breech lock marginal value (it is,
300.78125mA) will may be used to define the latch-up immunity of the integrated circuit in test chip 210.
It is noted that existing latched test method is the most gradually to be incremented by triggering pulse.
Therefore, for existing latched test method, its must utilize successively 1mA, 2mA, 3mA ...,
The pulse that triggers of 300mA is repeated the latched test of test chip 210.In other words, existing
Latched test method the latched test of 300 time must be repeated, could validation test chip 210
Latch-up immunity.Therefore, for comparing existing latched test method, latched test device 100
The testing time of test chip 210 can be effectively reduced.In addition, latched test device 100 can
Directly the test chip 210 in wafer 200 to be measured is tested, namely latched test device 100
Latched test can be carried out for the integrated circuit in the chip manufacturing stage.Therefore, survey with existing breech lock
By contrast, latched test device 100 also can be effectively reduced the production cost of integrated circuit to method for testing
With the production time.
In order to cause those of ordinary skill in the art can know more about the present invention, below in Fig. 2
The thin portion step of step S220 and step S230 be further illustrated.For example, Fig. 5
For the thin portion flow chart in order to step S220 and step S230 to be described according to one embodiment of the invention.
For the thin portion step of step S220, as shown in step S510 and step S520, signal
Generator 110 can provide supply voltage extremely to test the power supply weld pad of chip 210, and can provide triggering arteries and veins
Punching is to the input weld pad testing chip 210.Additionally, as shown in step S530, triggering pulse quilt
With afterwards before offer, signal detection device 120 can detect the electric current flowing through power supply weld pad respectively, to take
Obtain the first initial current at least one detection signal and the first detecting current.
For example, Fig. 6 be according to one embodiment of the invention in order to illustrate that the waveform of latched test shows
It is intended to.As shown in Figure 6, in period T61～T63, signal generator 110 can provide supply voltage
610 to the power supply weld pad testing chip 210.Additionally, in period T62, signal generator 110
Can provide and trigger pulse 620 to the input weld pad testing chip 210.Furthermore, triggering pulse 620
Before being provided, namely in period T61, signal detection device 120 can be detected and flow through power supply weld pad
Electric current, to obtain the first initial current.After triggering pulse 620 and being provided, namely in the phase
Between in T63, signal detection device 120 also can detect the electric current flowing through power supply weld pad, detects obtaining first
Survey electric current.Additionally, trigger pulse 620 to can be for example a positive pulse electric current.In another embodiment,
Trigger pulse 620 and also can be for example a negative pulse current.
For the thin portion step of step S230, as shown in step S540, controller 130 may compare
First detecting current and the first initial current, initial the most electric more than first to differentiate the first detecting current
Stream.Furthermore, when the first detecting current is more than the first initial current, as shown in step S550, control
Device 130 processed can determine that test chip 210 is in latch mode.On the other hand, when the first detecting current
When being not more than the first initial current, controller 130 can determine that test chip 210 is not at latch mode.
Fig. 7 be according to further embodiment of this invention in order to the thin of step S220 and step S230 to be described
Portion's flow chart, and the waveform signal in order to latched test to be described that Fig. 8 is foundation one embodiment of the invention
Figure.For the thin portion step of step S220, as shown in step S710, signal generator 110 can
There is provided and trigger pulse to the power supply weld pad testing chip 210.For example, with reference to Fig. 8, in period
In T82, signal generator 110 can provide trigger pulse 810 to test chip 210 power supply weld pad,
And triggering pulse 810 can be for example a positive pulse voltage.
Furthermore, as shown in step S720, triggering before pulse is provided with afterwards, signal detection
Device 120 can detect the electric current flowing through power supply weld pad respectively, initial with obtain at least one detection signal
Electric current and detecting current.For example, with reference to Fig. 8, before triggering pulse 810 is provided, also
Being exactly in period T81, signal detection device 120 can detect the electric current flowing through power supply weld pad, to obtain
Initial current.After triggering pulse 810 and being provided, namely in period T83, signal detection
Device 120 can detect the electric current flowing through power supply weld pad, to obtain detecting current.
For the thin portion step of step S230, as shown in step S730, controller 130 can compare
Detecting current and initial current, to differentiate that whether detecting current is more than initial current.Additionally, when detecting
When electric current is more than initial current, as shown in step S740, controller 130 can determine that test chip 210
It is in latch mode.On the other hand, when detecting current is not more than initial current, such as step S750 institute
Showing, controller 130 can determine that test chip is not at latch mode.
In sum, adjustable of the present invention test interval, and correspondence can be selected in response to test interval
Benchmark test value, to set to test the triggering pulse of wafer to be measured whereby.Whereby, can be effective
Ground reduces the testing time of wafer to be measured, thus contributes to reducing the testing time.Additionally, the present invention can
Carry out latched test for the integrated circuit in the chip manufacturing stage, therefore can be effectively reduced integrated electricity
The production cost on road and production time.
Although the present invention is disclosed above with embodiment, so it is not limited to the present invention, Ren Hesuo
Belong to those of ordinary skill in technical field, without departing from the spirit and scope of the present invention, when making portion
The change divided and modification, therefore protection scope of the present invention is when being as the criterion depending on as defined in claim.
Claims (8)
1. a latched test method, it is characterised in that including:
Perform a setting operation, to choose one as one from the interval multiple test values contained of test
Benchmark test value, and utilize this benchmark test value to set a triggering pulse and a preset error value, this base
This test interval is divided into one first subinterval and one second subinterval by quasi-test value；
Utilize the test chip in this triggering pulse test one wafer to be measured, to obtain at least one detecting
Signal；
Differentiate whether this test chip is in a latch mode according to this at least one detection signal；
When this test chip is not in this latch mode, update this test section according to this first subinterval
Between, and return to perform the step of this setting operation；
When this test chip is in this latch mode, and the difference of a breech lock marginal value and this benchmark test value
When value is more than this preset error value, update this door bolt respectively according to this benchmark test value and this second subinterval
Lock marginal value is interval with this test, and returns to perform the step of this setting operation；And
When this test chip is in this latch mode, and the difference of this breech lock marginal value and this benchmark test value
When value is not more than this preset error value, stop the test of this test chip.
Latched test method the most according to claim 1, wherein utilizes this triggering pulse test to be somebody's turn to do
This test chip in wafer to be measured, includes obtaining the step of this at least one detection signal:
There is provided a supply voltage to a power supply weld pad of this test chip；
There is provided this triggering pulse to an input weld pad of this test chip；And
With afterwards before providing this triggering pulse, detecting flows through the electric current of this power supply weld pad respectively, with
Obtain one first initial current in this at least one detection signal and one first detecting current.
Latched test method the most according to claim 2, wherein according to this at least one detection signal
Differentiate that the step whether this test chip is in this latch mode includes:
Relatively this first detecting current and this first initial current；
When this first detecting current is more than this first initial current, then judge that this test chip is in this
Latch mode；And
When this first detecting current is not more than this first initial current, then judge that this test chip is not located
In this latch mode.
Latched test method the most according to claim 1, wherein utilizes this triggering pulse test to be somebody's turn to do
This test chip in wafer to be measured, includes obtaining the step of this at least one detection signal:
There is provided this triggering pulse to a power supply weld pad of this test chip；
With afterwards before providing this triggering pulse, detecting flows through the electric current of this power supply weld pad respectively, with
Obtain the initial current in this at least one detection signal and a detecting current.
Latched test method the most according to claim 4, wherein according to this at least one detection signal
Differentiate that the step whether this test chip is in this latch mode includes:
Relatively this detecting current and this initial current；
When this detecting current is more than this initial current, then judge that this test chip is in this latch mode；
And
When this detecting current is not more than this initial current, then judge that this test chip is not at this breech lock
State.
6. a latched test device, it is characterised in that including:
One controller, chooses one as a benchmark test from multiple test values that a test interval is contained
Value, and utilize this benchmark test value to set a triggering pulse and a preset error value, and this benchmark test
This test interval is divided into one first subinterval and one second subinterval by value；
One signal generator, produces this triggering pulse according to this benchmark test value, and by this triggering pulse
The test chip being sent in a wafer to be measured, to cause this latched test device to carry out this test core
The test of sheet；And
One signal detection device, detects the signal from this test chip, to obtain at least one detection signal,
And according to this at least one detection signal, this controller differentiates whether this test chip is in a latch mode,
When this test chip is not in this latch mode, this controller updates according to this first subinterval
This test is interval, and resets this triggering pulse, to cause this according to this test interval after updating
Latched test device carries out the test of this test chip again,
When this test chip is in this latch mode, and the difference of a breech lock marginal value and this benchmark test value
When value is more than this preset error value, this controller is according to this benchmark test value with this second subinterval respectively
Update this breech lock marginal value interval with this test, to cause this latched test device again to carry out this test
The test of chip,
When this test chip is in this latch mode, and the difference of this breech lock marginal value and this benchmark test value
When value is not more than this preset error value, this latched test device stops the test of this test chip.
Latched test device the most according to claim 6, wherein this signal generator provides an electricity
Source voltage is to a power supply weld pad of this test chip, and provides this triggering pulse to the one of this test chip
Input weld pad,
With afterwards before this triggering pulse is provided, this signal detection device is detected respectively and is flowed through this power supply
The electric current of weld pad is to obtain one first initial current in this at least one detection signal and one first detecting
Electric current,
This controller compares this first detecting current and this first initial current, when this first detecting current
During more than this first initial current, then this controller judges that this test chip is in this latch mode, when
When this first detecting current is not more than this first initial current, then this controller judges this test chip not
It is in this latch mode.
Latched test device the most according to claim 6, wherein this signal generator provides this to touch
Send out pulse to a power supply weld pad of this test chip,
With afterwards before this triggering pulse is provided, this signal detection device is detected respectively and is flowed through this power supply
The electric current of weld pad, to obtain the initial current in this at least one detection signal and a detecting current,
This controller compares this detecting current and this initial current, when this detecting current is the most electric more than this
During stream, then this controller judges that this test chip is in this latch mode, when this detecting current is not more than
This initial current, then this controller judges that this test chip is not at this latch mode.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108169661A (en) * | 2017-12-28 | 2018-06-15 | 天津芯海创科技有限公司 | Method of designing integrated circuit and integrated circuit latching effect test method |
| CN110501589A (en) * | 2019-08-14 | 2019-11-26 | 中国科学院近代物理研究所 | A kind of simulation of ASIC latch and protection system and method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108169661A (en) * | 2017-12-28 | 2018-06-15 | 天津芯海创科技有限公司 | Method of designing integrated circuit and integrated circuit latching effect test method |
| CN110501589A (en) * | 2019-08-14 | 2019-11-26 | 中国科学院近代物理研究所 | A kind of simulation of ASIC latch and protection system and method |
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| CN106324477B (en) | 2019-03-12 |
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