CN100395555C - Latching effect detecting method for CMOS circuit - Google Patents
Latching effect detecting method for CMOS circuit Download PDFInfo
- Publication number
- CN100395555C CN100395555C CNB2004100511499A CN200410051149A CN100395555C CN 100395555 C CN100395555 C CN 100395555C CN B2004100511499 A CNB2004100511499 A CN B2004100511499A CN 200410051149 A CN200410051149 A CN 200410051149A CN 100395555 C CN100395555 C CN 100395555C
- Authority
- CN
- China
- Prior art keywords
- voltage
- current
- test
- cmos circuit
- test method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Tests Of Electronic Circuits (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
Abstract
The present invention relates to a latching effect detecting method for a CMOS circuit, which can be used for detecting accuracy values of the trigger voltage / current and the sustain voltage / current of a CMOS integrated circuit and anti-latching ability parameters of secondary breakdown voltage / current. When in detection, firstly, all the input ends of devices to be detected are grounded, and the output ends are hung; then, making the following steps: firstly, making direct current voltage sweep detection for ends to be detected until the ends to be detected are conducted to the ground and obtaining the trigger voltage Von of the ends to be detected; then, making pulse current Ipulse detection for the ends to be detected until latching appears and obtaining the trigger current and the sustain voltage / current; finally, making pulse voltage Vpulse detection for the ends to be detected until secondary breakdown appears and obtaining the secondary breakdown voltage / current.
Description
[technical field]
The present invention relates to a kind of method of testing, refer in particular to a kind of latch effect test method that is used for cmos circuit.
[background technology]
At present, before dispatching from the factory, the CMOS integrated circuit mostly need carry out the test of anti-breech lock ability, with the influence of judging that breech lock produces integrated circuit.The standard of the anti-breech lock ability of test CMOS integrated circuit mainly is JEDEC78, the external at present existing instrument and equipment that manufactures and designs according to this standard, the anti-breech lock ability that is used to test the CMOS integrated circuit.The test flow chart of the complete anti-breech lock ability of CMOS integrated circuit of JEDEC78 regulation sees also shown in Figure 1.Wherein, the ATE test is meant ATE (automatic test equipment) (Auto TestEquipment) test, function and the parameter that can test device under test.The ATE test is carried out once respectively before and after real anti-breech lock aptitude tests, to guarantee the accuracy of anti-breech lock aptitude tests, carry out the ATE test and guarantee that device under test is before anti-breech lock aptitude tests, carrying out the ATE test after anti-breech lock aptitude tests is to see whether anti-breech lock aptitude tests damage device under test.Real anti-breech lock aptitude tests comprise that mainly positive current test, negative current are tested and superpotential is tested three parts, and the each several part test need all not carried out in each anti-breech lock aptitude tests, but select specific test to carry out according to pilot project.Describe the testing procedure of positive current test, negative current test and superpotential test below in detail.
The step of positive current test is as follows:
Step 1: biasing device under test.See also input pin shown in Figure 2, all, comprise and be in input attitude or the two-way I/O pin of high-impedance state, the I/O pin that does not preset, all be connected to the largest logical high level.The I/O pin that has preset is then setovered according to its defined state, and the pin that promptly needs to connect high level is connected under the high logic state, needs to connect low level pin and then is connected under the low logic state.Device under test remains under the equilibrium temperature.At this moment, test the Inom of each Vsupply pin.
Step 2: pin to be measured is applied the pulse of triggering source.Pulse height please refer to table 1, and the duration please refer to table 2, and waveform as shown in Figure 3.
Step 3: after removing the triggering source, pin to be measured is returned apply triggering source pulse state before, test the Isupply of each Vsupply pin again.If any one Isupply is more than or equal to the failure criteria of defined in the table 3, then the decidable breech lock takes place, then remove added power supply on the device under test, stop anti-breech lock aptitude tests to this device under test, change new device under test, return step 1, carry out the anti-breech lock aptitude tests of new device under test.
Step 4:, then after cool time, all test pin are repeated repeating step 2-step 3 through necessity if breech lock does not take place.
Step 5: all input pins, comprise the two-way I/O pin that is in input attitude or high-impedance state, the I/O pin that does not preset all is connected to the largest logical low level.The I/O pin that has preset is then setovered according to its defined state, and the pin that promptly needs to connect high level is connected under the high logic state, needs to connect low level pin and then is connected under the low logic state repeating step 2-step 4.
The anti-breech lock aptitude tests of table 1 condition
| Trigger pulse width(tw) | 50m sec. | Trigger pulse width(tw) | 10m sec. |
| Duty factor | 20％ | Duty factor | 30％ |
| Current step：starting current | 0A | Voltage step：starting voltage | 0.0V |
| Increasement | 0.01A | Increasement | 0.1V |
The definition of time parameter in the anti-breech lock aptitude tests of table 2
The failure criteria of the anti-breech lock aptitude tests of table 3
The step of negative current test is identical with the step of positive current test, and wherein step 1 sees also shown in Figure 4ly when setovering device under test, and the triggering source pulse waveform that step 2 applied sees also shown in Figure 5.
The step 1 of superpotential test is identical with the step of positive current test to step 4, and wherein step 1 sees also shown in Figure 6ly when setovering device under test, and the triggering source pulse waveform that step 2 applied sees also shown in Figure 7.Step 5 is for all to carry out step 1-step 4 to each Vsupply pin, and this is because need all the other Vsupply are received on the power supply of requirement again after changing a Vsupply.And the superpotential test is to carry out at each Vsupply pin.In order to ensure the parameter that can access effective anti-breech lock ability, input high level should remain in the high logic scope of device regulation (usually test than superpotential big by 70%).If in effective high logic scope, the state variation of device can not cause the change of Inom to incoming level yet, thereby may obtain invalid data.
But according to the anti-breech lock ability of this method test CMOS integrated circuit, whether trigger voltage/the electric current that only can obtain this CMOS integrated circuit (for electric current, gets 100mA or 1.5 times of source currents (getting big value wherein) by a certain nominal value; For voltage, be generally 1.5 times of supply voltages), and can not obtain the anti-breech lock ability parameter of this CMOS integrated circuit reality.The anti-breech lock ability parameter of CMOS integrated circuit reality is meant the circuit triggers voltage/current, keeps the accurate numerical value and the secondary breakdown voltage/electric current of voltage/current, these numerical value are significant concerning circuit designers and circuit factory, can instruct design and production.And, the triggering source pulse waveform more complicated that is applied in testing process that this method adopted and the test process, not too convenient in actual use.
[summary of the invention]
Fundamental purpose of the present invention is to provide the latch effect test method of a kind of parameter that can accurately test the anti-breech lock ability of CMOS integrated circuit and cmos circuit easy to use.
The objective of the invention is to be achieved through the following technical solutions: a kind of latch effect test method of cmos circuit, can be used for testing the trigger voltage/electric current of CMOS integrated circuit, the accurate numerical value of keeping voltage/current and the anti-breech lock ability parameter of secondary breakdown voltage/electric current, at first that device under test is all input ends are connected to ground during test, output terminal is unsettled, carries out as follows then:
A, end to be measured is carried out DC voltage sweep test,, obtain the trigger voltage Von of end to be measured up to end to be measured conducting over the ground.
B, end to be measured is carried out pulse current Ipulse test,, obtain trigger current and keep voltage/current up to breech lock occurring.
C, end to be measured is carried out pulse voltage Vpulse test,, obtain secondary breakdown voltage/electric current up to second breakdown occurring.
Compared with prior art, the latch effect test method of cmos circuit of the present invention can obtain CMOS integrated circuit trigger voltage/electric current, keep actual anti-breech lock ability parameters such as the accurate numerical value of voltage/current and secondary breakdown voltage/electric current, these parameters are significant concerning circuit designers and circuit factory, can instruct design and produce the risk of reduction design cost and use.And the triggering source pulse waveform that is applied in testing process that this method adopted and the test process is fairly simple, and is more convenient in actual use.
[description of drawings]
The present invention is further described below in conjunction with drawings and Examples.
Fig. 1 is the process flow diagram of the latch effect test method of present cmos circuit.
Fig. 2 is positive current test circuit biasing figure.
Positive pulse current waveform when Fig. 3 tests for positive current.
Fig. 4 is negative current test circuit biasing figure.
Negative pulse current waveform when Fig. 5 tests for negative current.
Fig. 6 is superpotential test circuit biasing figure.
Voltage waveform when Fig. 7 tests for superpotential.
Fig. 8 is the process flow diagram of the latch effect test method of cmos circuit of the present invention.
Fig. 9 is the latch effect test method test result figure of cmos circuit of the present invention.
[embodiment]
See also shown in Figure 8, the latch effect test method of cmos circuit of the present invention, can be used for testing the trigger voltage/electric current of CMOS integrated circuit, the accurate numerical value of keeping voltage/current and the anti-breech lock ability parameter of secondary breakdown voltage/electric current, at first that device under test is all input ends are connected to ground during test, output terminal is unsettled, carries out as follows then:
Step 1: at first end to be measured is carried out the DC voltage sweep test,, obtain the trigger voltage Von of end to be measured up to end to be measured conducting over the ground.In the specific implementation, the sweep limit of DC voltage can be from 0V, and step-length is 0.5V, and electric current is restricted to 50mA.Can see that from the IV characteristic of power end electric current is very little when voltage is worth less than certain, electric current increased suddenly when voltage reached certain value.Pairing voltage value was exactly a trigger voltage when electric current increased suddenly, saw also shown in Figure 9ly, and Von is trigger voltage.
Step 2: end to be measured is carried out pulse current Ipulse test,, obtain trigger current and keep voltage/current up to breech lock occurring.In the specific implementation, pulse current can be from 0mA, pulse width 50ms, and dutycycle is 20%, and step-length is provided with as required, and voltage range is restricted to Von+1V.Increase voltage with electric current also increases always, voltage descends suddenly when electric current reaches certain value, illustrate that then device under test enters breech lock, descend suddenly time institute's corresponding current of voltage is trigger current, first voltage/current of back that descends is keeps voltage/current, see also shown in Figure 9ly, Vh/Ih is and keeps voltage/current.
Step 3: end to be measured is carried out pulse voltage Vpulse test,, obtain secondary breakdown voltage/electric current up to second breakdown occurring.After device enters breech lock, if certain current limiting measures are not arranged, its electric current will increase sharply, and up to thermoelectric the puncture taken place, device be burnt, and the thermoelectric current/voltage that punctures take place just be called the second breakdown current/voltage.The second breakdown electric current is the tolerant maximum breech lock electric current of device.In the specific implementation, pulse voltage can be from 0V, pulse width 50ms, dutycycle is 20%, step-length is provided with as required, range of current is as the criterion and can produces second breakdown based on damage equipment not, can be provided with when testing first than low value, increase as required then, secondary breakdown voltage/electric current that the record test obtains, see also shown in Figure 9ly, Vt2/It2 is secondary breakdown voltage/electric current.
An embodiment who is to use the latch effect test method of cmos circuit of the present invention to test below.Losing efficacy appears in certain EPROM circuit, and failure phenomenon has three kinds, is respectively: memory cell signal is all lost, part is lost, certain pin of address code is zero always.Find that by failure analysis the power end of inefficacy sample all is subjected to the impact of too high voltages pulse, suspection is the breech lock Damage and Failure, the anti-breech lock characteristic of decision test non-defective unit.Table 4 is a test result.
The anti-breech lock aptitude tests of table 4EPROM circuit power end result
| The measurement project | Trigger current (mA) | Keep voltage (V) |
| |
350 | 2.296 |
| |
200 | 8.764 |
According to the technical indicator of this sample, the ratings of breech lock trigger current is greater than 200mA.Sample 1 meets the regulation of technical indicator, and sample 2 is just up to standard.Yet the voltage of keeping of sample 1 is 2.296V, and is on the low side.In case the generation breech lock, because the supply voltage ratings is 7V, this value is more much bigger than keeping voltage.Under the situation that power supply does not turn-off, breech lock can not withdraw from automatically.Test result shows that the anti-breech lock ability of this kind device is general, and is more consistent with the result of failure analysis.
Compared with prior art, the latch effect test method of cmos circuit of the present invention can obtain CMOS integrated circuit trigger voltage/electric current, keep the actual anti-breech lock ability parameters such as the accurate numerical value of voltage/current and secondary breakdown voltage/electric current, these parameters are significant concerning circuit designers and circuit factory, can design and production, reduce the risk of design cost and use. And the trigger source impulse waveform that applies in the testing process that the method adopts and the test process is fairly simple, and is more convenient in actual use.
Claims (7)
1. the latch effect test method of a cmos circuit, it is characterized in that: described method of testing can be used for testing the trigger voltage/electric current of CMOS integrated circuit, the accurate numerical value of keeping voltage/current and the anti-breech lock ability parameter of secondary breakdown voltage/electric current, at first that device under test is all input ends are connected to ground during test, output terminal is unsettled, carries out as follows then:
A, at first end to be measured is carried out DC voltage sweep test,, obtain the trigger voltage Von of end to be measured up to end to be measured conducting over the ground;
B, end to be measured is carried out pulse current Ipulse test,, obtain trigger current and keep voltage/current up to breech lock occurring;
C, end to be measured is carried out pulse voltage Vpulse test,, obtain secondary breakdown voltage/electric current up to second breakdown occurring.
2. the latch effect test method of cmos circuit as claimed in claim 1, it is characterized in that: the sweep limit of steps A DC voltage can be from 0V, and step-length is 0.5V.
3. the latch effect test method of cmos circuit as claimed in claim 1, it is characterized in that: the steps A electric current is restricted to 50mA.
4. the latch effect test method of cmos circuit as claimed in claim 1, it is characterized in that: step B pulse current can be from 0mA, pulse width 50ms, dutycycle is 20%, step-length is provided with as required.
5. the latch effect test method of cmos circuit as claimed in claim 1, it is characterized in that: step B voltage range is restricted to Von+1V.
6. the latch effect test method of cmos circuit as claimed in claim 1, it is characterized in that: step C pulse voltage can be from 0V, pulse width 50ms, dutycycle is 20%, step-length is provided with as required.
7. the latch effect test method of cmos circuit as claimed in claim 1 is characterized in that: step C range of current is as the criterion and can produces second breakdown based on damage equipment not.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100511499A CN100395555C (en) | 2004-08-19 | 2004-08-19 | Latching effect detecting method for CMOS circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100511499A CN100395555C (en) | 2004-08-19 | 2004-08-19 | Latching effect detecting method for CMOS circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1588107A CN1588107A (en) | 2005-03-02 |
| CN100395555C true CN100395555C (en) | 2008-06-18 |
Family
ID=34602384
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100511499A Active CN100395555C (en) | 2004-08-19 | 2004-08-19 | Latching effect detecting method for CMOS circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100395555C (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8174480B2 (en) * | 2008-06-12 | 2012-05-08 | Himax Technologies Limited | Gate driver and display panel utilizing the same |
| CN101398468B (en) * | 2008-10-16 | 2013-04-17 | 北京中星微电子有限公司 | Latch effect test method and system for CMOS chip |
| CN102955124B (en) * | 2011-08-31 | 2015-04-22 | 北京中电华大电子设计有限责任公司 | Test method for burr interference trigger chip latch-up effect |
| CN102608410B (en) * | 2011-12-12 | 2015-03-25 | 中国电力科学研究院 | Pulse generation circuit, voltage measuring circuit and voltage measuring method |
| CN106324477B (en) * | 2015-07-07 | 2019-03-12 | 旺宏电子股份有限公司 | Latched test apparatus and method |
| CN108169661B (en) * | 2017-12-28 | 2020-07-10 | 天津芯海创科技有限公司 | Integrated circuit design method and integrated circuit latch-up test method |
| CN110045204B (en) * | 2019-04-26 | 2021-09-07 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | Single event latch-up holding current test method, device and system |
| CN110501589A (en) * | 2019-08-14 | 2019-11-26 | 中国科学院近代物理研究所 | A kind of simulation of ASIC latch and protection system and method |
| CN114152857A (en) * | 2021-12-07 | 2022-03-08 | 华东师范大学 | Preparation method of two-dimensional material field effect transistor failure sample |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1378112A (en) * | 2001-04-03 | 2002-11-06 | 华邦电子股份有限公司 | Current source device for latching detection |
-
2004
- 2004-08-19 CN CNB2004100511499A patent/CN100395555C/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1378112A (en) * | 2001-04-03 | 2002-11-06 | 华邦电子股份有限公司 | Current source device for latching detection |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1588107A (en) | 2005-03-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110763981B (en) | Integrated circuit chip inspection system and method | |
| US8054085B2 (en) | Programmable gain trans-impedance amplifier overload recovery circuit | |
| US9411016B2 (en) | Testing of a transient voltage protection device | |
| CN100395555C (en) | Latching effect detecting method for CMOS circuit | |
| US20110140732A1 (en) | Circuit for testing inrush current | |
| CN215768857U (en) | Device for testing reliability of semiconductor power electronic device | |
| CN112275667A (en) | Chip ESD diode process defect detection method based on difference comparison method | |
| CN113125930A (en) | Device for testing reliability of semiconductor power electronic device | |
| CN110361613B (en) | Device and method for testing pulse curve of electrostatic discharge protection device | |
| US7333311B2 (en) | Method and structure for AC coupled insitu ESD protection | |
| CN104502115A (en) | High precision detector | |
| US10944259B2 (en) | System and method for over voltage protection in both positive and negative polarities | |
| CN108051737B (en) | switch device screening system and method | |
| CN102590762A (en) | Information entropy principle-based method for fault diagnosis of switch power supply | |
| CN115144719A (en) | Power device testing device | |
| CN103197238A (en) | Automotive relay coil energy releasing testing method | |
| CN112964983A (en) | Protection circuit, control method of protection circuit and test equipment | |
| CN108169661B (en) | Integrated circuit design method and integrated circuit latch-up test method | |
| Smedes et al. | Characterization methods to replicate EOS fails | |
| CN2844936Y (en) | IC testing circuits | |
| CN219162337U (en) | Test platform for service life of lamp | |
| CN214622955U (en) | Protection circuit and test equipment | |
| CN110007162A (en) | For monitoring the circuit of the transient time in simulation system and digital display circuit | |
| CN113049921B (en) | TDDB test structure, TDDB test system and test method thereof | |
| CN117607659A (en) | Chip aging test system with short circuit test and test method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP03 | "change of name, title or address" |
Address after: No. 78, Zhucun Avenue West, Zhucun street, Zengcheng District, Guangzhou, Guangdong 511300 Patentee after: CHINA ELECTRONIC PRODUCT RELIABILITY AND ENVIRONMENTAL TESTING Research Institute (THE FIFTH ELECTRONIC Research Institute OF MIIT)(CEPREI LABORATORY)) Address before: 510610 No. 110 Zhuang Road, Tianhe District, Guangdong, Guangzhou, Dongguan Patentee before: The 5th Research Institute of the Electronics Ministry of Information Industry |
|
| CP03 | "change of name, title or address" |