CN102955124B

CN102955124B - Test method for burr interference trigger chip latch-up effect

Info

Publication number: CN102955124B
Application number: CN201110255011.0A
Authority: CN
Inventors: 杨利华
Original assignee: Beijing CEC Huada Electronic Design Co Ltd
Current assignee: HUADA SEMICONDUCTOR CO., LTD.
Priority date: 2011-08-31
Filing date: 2011-08-31
Publication date: 2015-04-22
Anticipated expiration: 2031-08-31
Also published as: CN102955124A

Abstract

The invention provides a test method for a burr interference trigger chip latch-up effect, and aims to test whether a chip has a trigger latch-up effect aiming at different high-frequency oscillation burr signals. During test, three parameters, namely a maximum peak voltage value, a maximum pulse width Twidth and the burr density of a burr pulse wave, are required to be selected as a test point; one test point executes one trigger latch-up effect test; different maximum peak voltage values, different maximum pulse widths Twidth and different burr densities are used as different test points; a plurality of test points are respectively used for executing the trigger latch-up effect test; and finally, three-dimensional burr trigger Latch-Up Test result distribution can be formed.

Description

A kind of method of testing of burr interference trigger chip latch-up

Technical field

The present invention relates to a kind of method of testing of burr interference trigger chip latch-up, be particularly applicable to having the chip latch-up of high reliability request to test.

Background technology

At present, the test basic skills of chip latch-up, has clear stipulaties at disclosed international standard JEDEC IC Latch-UpTest JESD78B.

As shown in Figure 1, the test that JESD78B specifies triggers waveform 3 kinds, is respectively the positive current of interruption, negative current, power supply overvoltage pulse waveform.

Specify according to IC standard Latch-Up Test JESD78B, these 3 kinds of trigger waveforms, its pulse width is 10 μ s ~ 1s, current trigger pulse height is that running current adds 100mA or is 1.5 times of running current, and power supply overvoltage trigger pulse amplitude is 1.5 times of normal working power voltage.

Chip is in the system applied environment of reality, the interference sources such as thunder and lightning, relay, controllable silicon, motor, high-frequency element, the random high frequency vibration burr waveform of the similar damped oscillation of interference waveform produced, by spatial electromagnetic coupling scheme or conduction pattern, enter chip internal, thus the latch-up of flip chip.

The random high frequency vibration burr signal produced in real system applied environment completely can the latch-up of flip chip, the width of this random high frequency vibration burr signal is but far below the width that IC Latch-Up Test JESD78B standard testing waveform specifies, substantially, not within the scope of the waveform widths 10 μ s ~ 1s of its regulation, the potential pulse of the random high frequency vibration burr signal produced in real system applied environment and current impulse amplitude are also substantially far above the amplitude that IC Latch-Up Test JESD78B standard specifies.

Like this, some chip is according to the regulation of IC standard Latch-Up Test JESD78B, although have passed the latch-up test of higher level, but in actual use, run into the random high frequency vibration burr waveform that the interference sources such as thunder and lightning, relay, controllable silicon, motor, high-frequency element produce, be but easy to trigger latch effect.The IC latch-up test of the regulation of obvious IC standard Latch-Up Test JESD78B, can not meet the real system application testing demand of chip.

Summary of the invention

Object of the present invention, propose a kind of new method of testing, is used for testing the latch-up distribution situation of different higher-order of oscillation burr signal flip chip.

In the method for testing of the chip latch-up that the present invention proposes, except trigger waveform different from JEDEC ICLatch-Up Test JESD78B except, other all adopts the content identical with JEDEC IC Latch-Up Test JESD78B as aspects such as probe temperature rank, sample specification, triggering test condition, fail-ure criterion conditions.

It is as shown in Figure 21 of the generation of damped oscillation wave producer or the burr pulsating wave of multiple intervals one fixed width that the latch-up that the present invention adopts triggers ripple.Damped oscillation waveform after single burr pulse amplifying as shown in Figure 3, is made up of maximum forward pulse, maximum negative-going pulse and the repercussions of decaying gradually.

The testing process implementing method of testing of the present invention carries out according to the regulation of IC standard Latch-Up Test JESD78B completely, unlike, test after needing first to select these 3 parameter values of the maximum sharpness magnitude of voltage of burr pulse, maximum pulse Twidth, burr closeness during test.

Often select burr maximum sharpness magnitude of voltage, maximum pulse Twidth, a burr closeness, just carry out a trigger latch effect test as a test point, finally can form three-dimensional glitch trigger Latch-Up Test test result distribution plan.But the maximum pulse Twidth of any one test point is all lower than the triggering waveform minimum width 10 μ s of the regulation of IC Latch-Up Test JESD78B.

The method of testing of a kind of burr interference trigger chip latch-up disclosed by the invention, waveform for trigger latch effect is the burr pulsating wave of multiple intervals one fixed width, using a burr pulsating wave as a test point, according to order from small to large respectively with regard to the maximum sharpness magnitude of voltage of each test point, maximum pulse, burr closeness is carried out latch-up and is triggered test, and by maximum sharpness magnitude of voltage, maximum pulse, the glitch trigger test result distribution plan of the three-dimensional of burr closeness composition triggers test result to the latch-up of each test point mark, according to the maximum sharpness magnitude of voltage of different test point, maximum pulse, the test result distribution of burr closeness, obtain the reaction result that chip is tested different burr interference triggered latch-ups.

According to different applied environments, select suitable chip, avoid the chip application of easy trigger latch effect in some test point in the applied environment having corresponding burr to disturb.

Accompanying drawing explanation

Fig. 1 is that 3 kinds of tests of JESD78B regulation trigger waveform, comprises positive current, negative current, power supply overvoltage pulse.

Fig. 2 is 1 of trigger latch effect or the burr pulsating wave of multiple intervals one fixed width.

Fig. 3 is the schematic diagram after the single burr pulsating wave of trigger latch effect amplifies.

Fig. 4 is the three-dimensional distribution map of glitch trigger latch-up test result.

Embodiment

Below citing illustrates the latch-up test process of burr pulsating wave as test triggering waveform of employing 1 or multiple intervals one fixed width.

As shown in Figure 2, the burr quantity in the burr pulsating wave of multiple intervals one fixed width in the unit interval is called burr closeness, and maximum sharpness magnitude of voltage, the maximum pulse Twidth mark of single burr pulsating wave are shown in Fig. 3.

Before latch-up test is carried out to chip, the burr closeness test specification of predetermined trigger burr ripple is 1/10ms ~ 10000/10ms, the maximum sharpness magnitude of voltage test specification of predetermined trigger burr ripple is 7.5V ~ 127.5V, and the maximum pulse Twidth test specification of predetermined trigger burr ripple is 1ns ~ 2.88 μ s.When chip under test working power voltage is for being 5V to the maximum, the center voltage of the triggering burr ripple of setting damped oscillation wave producer is 5V.

It is 1/10ms that setting tests burr closeness first, and maximum sharpness magnitude of voltage 7.5V is tested in setting first, and setting maximum pulse Twidth is first 1ns.Then carry out triggering test, and carry out fail-ure criterion according to the method for IC standard Latch-Up Test JESD78B.When being judged to latch-up does not occur, Fig. 4 marking round dot, when judging latch-up occurs, Fig. 4 marking square.Then according to setting the maximum sharpness magnitude of voltage of each test point from small to large respectively, maximum pulse Twidth, burr closeness carry out latch-up and trigger test.Finally obtain glitch trigger Latch-Up Test test result three-dimensional distribution map as shown in Figure 4.

From glitch trigger Latch-Up Test test result three-dimensional distribution map as shown in Figure 4, according to the test result of the test point of different maximum sharpness magnitude of voltage, maximum pulse Twidth, burr closeness, the reaction result that chip is tested different burr interference triggered latch-ups just can be obtained.Like this, according to different applied environments, suitable chip can be selected, throw in different market, thus avoid the chip application of easy trigger latch effect in some test point at the applied environment having corresponding burr to disturb.

Claims

1. the method for testing of a burr interference trigger chip latch-up, it is characterized in that, waveform for trigger latch effect is the burr pulsating wave of multiple intervals one fixed width, using a burr pulsating wave as a test point, respectively with regard to the maximum sharpness magnitude of voltage of each test point, maximum pulse, burr closeness is carried out latch-up according to order from small to large and is triggered test, and by maximum sharpness magnitude of voltage, maximum pulse, the glitch trigger test result distribution plan of the three-dimensional of burr closeness composition triggers test result to the latch-up of each test point mark, according to the maximum sharpness magnitude of voltage of different test point, maximum pulse, the test result distribution of burr closeness, obtain the reaction result that chip is tested different burr interference triggered latch-ups.

2. the method for claim 1, is characterized in that, according to different applied environments, selecting suitable chip, avoids the chip application of easy trigger latch effect in some test point in the applied environment having corresponding burr to disturb.