JPH052620A - Device and method for circuit fault simulation test - Google Patents

Abstract

PURPOSE:To facilitate the evaluation of fault detection and to reduce the capacity of a memory and the burden of CPU by detecting and judging the presence or absence of fault propagation as to the respective logical gates of a circuit having gate delay time and a state storage based on fault information in which a fault mode is previously defined. CONSTITUTION:This test device is provided with a first storage means 11 storing fault mode information Sa0, and Sa1, and control data D1 on a tested semiconductor device 16, which are previously defined, a second storage means 12 storing test data DT executing the fault simulation of the tested semiconductor device 16, a third storage means 13 storing fault information fSa0, fSa1, DSa0, DSa1, MSa0 and MSa1 which are calculated on fault transmission in the respective logical gates LG1-LGn by test data DT, an information detection means 14 detecting fault information fSa0, fSa1, DSa0, DSa1, MSa0 and MSa1 based on a definition processing, and a control means 15 controlling the input/output of the first to third storage means 11-13 and the information detection means 14.

Description

Detailed Description of the Invention

[Table of Contents] Industrial applications Conventional technology (Figs. 23, 24) Problems to be Solved by the Invention Means for Solving the Problems (FIGS. 1 to 3) Action Example (1) Description of the first embodiment (FIGS. 4-9) (2) Description of the second embodiment (FIGS. 10 to 16) (3) Description of the third embodiment (17th to 22nd) The invention's effect

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit failure pseudo test apparatus and a circuit failure test method, and more specifically, it tests a semiconductor device under test (hereinafter referred to as LSI under test) having a failure point set therein. The present invention relates to simplification of an apparatus and method for supplying data and performing failure simulation.

In recent years, ultra-high integration of semiconductor integrated circuit devices,
In the field of LSI automatic design, with the increase in ultra-high density, failure simulation of a LSI under test in which logic gates are assembled is under way using a large-scale computer.

According to this, by performing a failure simulation for each failure of logic gates including a failure set inside the LSI under test based on the test data, the failure detection rate, undetected failure, etc. Information is obtained.

Therefore, it is necessary to calculate the output value of the logic gate for each of the logic gate not including the fault and the logic gate including the fault, and to compare the respective results at the output points of the respective logic gates. Further, it is necessary to judge each failure point whether or not the failure result is transmitted to the signal output section of the LSI under test.

As a result, the LSI under test can be highly integrated,
With ultra-high density, failure detection and evaluation becomes more and more difficult, leading to a longer logic gate design period. In addition, the central processing unit (hereinafter CP
(U) is used (occupied) for a long time, and the memory capacity of the data storage device is inevitably increased in order to calculate the output value of each logic gate and compare them.

Therefore, the presence / absence of failure propagation is determined for each logic gate such as a circuit having a gate delay time or a state memory based on the failure information in which the failure mode is defined in advance to simplify the failure detection evaluation. What is desired is a device and method that can reduce the memory capacity and the load on the CPU in addition to the above.

[0008]

2. Description of the Related Art FIGS. 23 and 24 are explanatory views of a conventional example. FIG. 23 is a configuration diagram for explaining a failure simulation according to the conventional example, and FIG. 24 shows a processing flowchart of the comparison / determination editor.

In FIG. 23, a plurality of logic gates LG1, L
An apparatus for simulating a failure of the LSI under test 7 in which G2, LGi ... LGn are incorporated is a failure simulation control memory 1, a test data file memory 2, a failure information memory 3, a comparison / judgment editor 4, a CPU 5, a display 6, a keyboard 9 And a system bus 8 for transmitting data between them.

The function of the device is, for example, the logic gate L.
G1, LG2, LGi ... LGn assembled LS under test
Comparison of Figure 24 when performing I7 failure simulation
/ As shown in the processing flow chart of the judgment editor,
First, at step P1, a failure point FLT is set in the LSI under test 7, and the test data DT is set in the signal input section IN of the LSI 7.
Supply processing. At this time, the LSI under test 7 is displayed on the display 6 or the like based on the display data D3.

Further, the operator inputs the input data D2 relating to the fault point FLT via the keyboard 9, and sets the fault point FLT in the signal input section IN of the logic gate LG1, for example. Further, the test data DT is read from the test data file memory 2 via the CPU 5.

Next, in step P2, the output values of the respective logic gates LG1, LG2, LGi ... LGn of the LSI to be tested 7 which have been set as failures are compared with the output values under normal conditions. At this time, the comparison / judgment editor 4, based on the control data D1 read from the failure simulation control memory 1, etc.
The CPU 5 performs arithmetic processing.

In this arithmetic processing, the influence of the fault point FLT is affected by the fault point FLT for each logic gate LG1, LG2, LGi ... LGn.
The failure simulation is performed by comparing the output value at the normal time when the value is not set and the output value at the failure when the failure point FLT is set one by one. The normal output value, the failure output value, and the comparison result data are stored in the failure information memory 3.

Thereafter, in step P3, it is determined whether or not the influence of the fault point FLT is transmitted to the signal output unit OUT.
At this time, if the influence of X is transmitted to the signal output unit OUT (YES), the process proceeds to step P4 and it is determined that "the influence of the fault point FLT can be observed by the test data DT".

When the influence of X does not propagate to the signal output unit OUT (NO), the process shifts to step P5 and "the influence of the fault point FLT cannot be observed in the test data DT".
To determine. The above processing of steps P1 to P5 is performed for all the faults and all the test data DT to be the targets of fault detection.

As a result, it is possible to perform a failure simulation for all the failure points set in the LSI under test 7 which are targets of the failure detection, and information such as the failure detection rate and the undetected failure for the LSI under test 7 can be obtained. can get.

[0017]

By the way, according to the conventional example, the failure point FLT set in the LSI under test 7 is subjected to a failure simulation for each failure based on the test data DT, so that the LSI under test 7 is tested. Information such as the failure detection rate and undetected failures is obtained.

Therefore, the output value of the logic gate for each of the logic gates LG1, LG2, LGi ... LGn of the logic circuit not including the fault point FLT and the logic gates LG1, LG2, LGi ... LGn of the logic circuit including the fault point FLT. Must be arithmetically processed by the comparison / judgment editor 4 and the CPU 5, and each must be compared at each logic gate output point.

Further, in order to judge whether or not the failure result is transmitted to the failure detection judgment point of the LSI under test, the result data of each arithmetic processing is stored in the failure information memory 3 in order to judge each failure point. I have to do it. That is,
LSI under test with failure points set for test data
Then, it is confirmed whether or not the difference in the output value of each logic gate between the LSI under test having no failure point is transmitted to the signal output section of the LSI under test.

As a result, the LSI to be tested is highly integrated,
With ultra-high density, fault detection and evaluation becomes more and more difficult, and, for example, the gate delay time and the logic gate design period of a circuit having state memory are prolonged. In addition, there is a problem that the CPU 5 is used (occupied) for a long time in the fault simulation, and the memory capacity of the fault information memory 3 for calculating the output value of each logic gate and comparing them is inevitably increased. There is.

The present invention was created in view of the problems of the conventional example, and a failure mode is defined in advance for each logic gate such as a circuit having a gate delay time and a state memory so as to determine whether or not there is a failure transfer. To provide a circuit failure pseudo test apparatus and a circuit failure test method capable of making a detection judgment based on failure information and simplifying failure detection evaluation, and at the same time, reducing a load on a memory capacity and a CPU. To aim.

[0022]

Means for Solving the Problems FIG. 1, FIG. 2 (a),
FIG. 3B is a principle diagram (1 and 2) of the circuit fault pseudo test apparatus according to the present invention, and FIGS. 3A and 3B are principle diagrams of the circuit fault test method according to the present invention. ing.

The circuit failure test apparatus of the present invention is an apparatus for simulating a failure of a semiconductor device 16 under test in which a plurality of logic gates LG1, LG2, LGi ... LGn are incorporated as shown in FIG. First storage means 11 for storing the failure mode information Sa0, Sa1 and control data D1 of the tested semiconductor device 16 under test, and the semiconductor device 1 under test
Second storage means 12 for storing the test data DT for performing the fault simulation of No. 6, and fault information fSa0, fSa1, calculated regarding the fault propagation at each logic gate LG1, LG2, LGi ... LGn by the test data DT. DSa0, DSa1
Third storage means 13 for storing MSa0, MSa1 and failure information fSa0, fSa1, DSa0, DSa1 M based on the definition process.
An information detecting means 14 for detecting Sa0 and MSa1 and a control means 15 for controlling input / output of the first, second and third storage means 11, 12, 13 and the information detecting means 14 are provided. Characterize.

In the circuit fault pseudo test apparatus, the third storage means 13 is used to store logic gates LG1, LG2, L of the semiconductor device 16 under test as shown in FIG. 2 (a).
It is characterized in that the scheduled propagation times ts0 and ts1 for each of the failure information fSa0 and fSa1 of Gi ... LGn are stored.

Further, in the circuit fault pseudo test apparatus, as shown in FIG. 2B, the third storage means 13 starts the test from the final fault detection judgment time T1 one cycle before the test data DT. Failure information f up to an arbitrary failure detection determination time TX related to the current cycle of the data DT
It is characterized in that Sa0, fSa1 and failure information DSa0, DSa1 relating to the above-mentioned scheduled transfer times ts0, ts1 are stored.

Furthermore, the first circuit fault pseudo-test method of the present invention uses a plurality of logic gates LG as shown in FIG.
1, LG2, LGi ... LGn is a method for simulating a failure of a semiconductor device 16 under test, which is shown in FIG.
As shown in the flowchart of FIG.
In step 1, the failure modes M0 and M1 of the semiconductor device under test 16 are defined to define the failure information fSa0 and fSa1 indicating the failure transfer. Then, in step P2, the semiconductor device under test 16 is tested.
Supply the test data DT to the signal input section IN of
Next, in step P3, the calculation storage processing of the failure information fSa0, fSa1 regarding the failure propagation in each logic gate LG1, LG2, LGi ... LGn is performed based on the test data DT, and then the signal of the semiconductor device under test 16 is processed. It is characterized in that the failure information fSa0, fSa1 is detected from the output unit OUT toward the signal input unit IN.

In the first circuit fault pseudo test method, the process of defining the fault modes M0 and M1 is performed by the logic gates LG1 and LG2 when a fault point FLT is set in the semiconductor device 16 under test. , LGi ... LGn is a first stuck-at fault in which an output signal or an input signal of LGn is fixed to logic “0”, and the first stuck-at fault exists only once in the semiconductor device 16 under test. The stuck-at fault M0 is a second stuck-at fault in which the output signal or the input signal of the logic gates LG1, LG2, LGi ... LGn is fixed to logic "1", and the second stuck-at fault causes the semiconductor device 16 to be tested. It is characterized in that it is defined as a second single stuck-at fault M1 which exists only one.

Further, in the first circuit fault pseudo test method, the definition process of the fault information fSa0, fSa1 indicating the fault propagation is performed by the logic gate LGj of the next stage for the first single stuck-at fault M0. Is defined as the first failure information fSa0 = 1 or 0 indicating the presence / absence of transmission to the logic gate LGj of the next stage for the second single stuck-at fault M1. The failure information fSa1 of 2 is defined as 1 or 0.

Further, a second circuit fault pseudo test method of the present invention is the same as the first circuit fault pseudo test method shown in FIG.
In the calculation storage process of step P3 in the flowchart of (b), when the fault point FLT is set in the logic gates LG1, LG2, LGi ... LGn, the logic gates LG1, LG2, LGi ... LGn failure information fSa0, fSa1
The storage processing of the scheduled transfer times ts0 and ts1 for each time, and the failure information fSa0 and fSa1 at the time of the last signal change related to the scheduled transfer times ts0 and ts1 and the failure information fSa0 at the time of the signal change related to the current time tc. , fSa1 based on the comparison process with the scheduled transmission time ts0, ts1 that has passed the current time tc, the failure information fSa0, fSa1 is validated. To do.

A third circuit fault pseudo test method of the present invention is the same as the first circuit fault pseudo test method shown in FIG.
In the calculation storage process of step P3 of the flowchart of (b), when the semiconductor device under test 16 includes the memory element MEM, the latest failure detection determination time T1 one cycle before the test data DT is updated. Failure information fSa0, fSa1
And an arbitrary failure detection determination time TX relating to the current cycle of the test data DT from the last failure detection determination time T1.
To the failure information fSa0, fSa1 and failure information MSa0, MSa between the final failure detection determination time T1 and any failure detection determination time TX related to the current cycle.
1 and the latest failure information fSa0, fSa1 at the arbitrary failure detection determination time TX relating to the current cycle are included.

In the third circuit failure pseudo test method, when the semiconductor device under test 16 includes the memory element MEM, the detection process of step P4 in the flowchart of FIG. First search processing from the signal output section OUT of the test semiconductor device 16 to the storage element MEM, and from the input section of the storage element MEM to the semiconductor device under test 1
The second search processing up to the signal input unit IN of 6 is included.

Further, in the third circuit fault pseudo test method, when the memory device MEM is included in the semiconductor device under test 16, the calculation memory process of step P3 of the flowchart of FIG. Failure information fSa relating to the final failure detection determination time T2 of the current cycle of the test data DT
After the detection processing of 0, fSa1, DSa0, DSa1, MSa0, MSa1, from the final failure detection determination time T1 one cycle before the relevant test data DT to the final failure detection determination time T2 relating to the current cycle of the relevant test data DT. All the failure information MSa0, MSa1, DSa0, DSa1 up to
The present invention is characterized in that it includes a calculation process for matching the latest failure information fSa0, fSa1 at the final failure detection determination time T2 related to the current cycle of T to achieve the above object.

[0033]

According to the circuit failure pseudo-testing apparatus of the present invention, as shown in FIG.
, The first, second, and third storage means 11, 12,
13, information detecting means 14 and control means 15 are provided.

For example, a plurality of logic gates LG1, LG2, L
When the failure point FLT is set in the semiconductor device 16 to be tested in which Gi ... LGn is incorporated and the circuit failure simulation is performed, the failure mode information Sa0 and Sa1 of the semiconductor device 16 to be tested, which are defined in advance, are the first storage means. The second storage means 12 stores the test data DT which is stored in the memory 11 and which simulates the failure of the semiconductor device 16 under test.
In addition, each logic gate LG1, LG based on the test data DT
2, LGi ... Failure information fSa0, concerning failure propagation in LGn
fSa1 is stored in the third storage means 13 via the control means 15, and failure information fSa0, fSa based on the definition processing is stored.
1 is detected by the information detecting means 14.

Therefore, the output values of the logic gates LG1, LG2, LGi ... LGn are calculated by a logic circuit having a fault point for the test data DT and a logic circuit having no fault point FLT, respectively, until the two values match. , Until the external output point is reached, the comparison / judgment editor 4 and CPU as in the conventional example
5, the comparison and arithmetic processing are eliminated. As a result, the load on the control means 15 is increased by each logic gate LG1, LG2,
Failure information fSa0, fSa1 remaining at the input point of LGi ... LGn
Is calculated and stored in the third storage unit 13.

Further, regarding whether or not the influence of the fault point FLT is transmitted to the signal output section (fault detection judgment point) of the semiconductor device 16 under test (fault propagation), each logic gate for each fault. Since it is not determined for each output point of LG1, LG2, LGi ... LGn, each logic gate LG as in the conventional example.
It becomes unnecessary to store the calculation result data of the output values of 1, LG2, LGi ... LGn.

As a result, the control means 15 is different from the conventional example.
It is possible to shorten the use (occupancy) time of the memory and to reduce the memory capacity of the third storage unit (fault information memory 3).

As shown in FIG. 2A, the expected propagation times ts1 and ts0 for the failure information fSa0 and fSa1 of the logic gates LG1, LG2, LGi ... By storing in the storage means 13, it becomes possible to perform a highly accurate failure simulation including the gate delay time td of the logic gates LG1, LG2, LGi ... LGn.

Further, as shown in FIG. 2B, the final failure detection determination time T1 one cycle before the test data DT.
From the failure information DSa0, DSa1 based on the failure information fSa0, fSa1 up to the arbitrary failure detection determination time TX related to the current cycle of the test data DT in the third storage means 13 to store the storage element MEM. It is possible to perform a highly accurate failure simulation for the semiconductor device 16 under test including the above.

Further, according to the first circuit fault pseudo-test method of the present invention, as shown in the flowchart of FIG. 3B, the first and second single stuck-at faults M0 and M at step P1.
The failure information fSa0, fSa1 indicating the failure transfer of 1 etc. is defined, the test data DT is supplied in step P2, and the logic gates LG1, LG2, LGi ... L are processed in step P3.
The failure information fSa0, fSa1 output from Gn is stored.

Therefore, a plurality of logic gates LG1, LG2,
When a failure point FLT is set in the semiconductor device 16 under test in which LGi ... LGn is incorporated and a failure simulation is performed,
In step P4, the final fault information fSa0 = 1 or 0 indicating the possibility of transmitting the first single stuck-at fault M0 from the signal output unit OUT to the signal input unit IN or the second single stuck-at fault M1.
The failure detection evaluation of the semiconductor device 16 under test can be easily performed by performing the detection processing of arbitrary failure information fSa1 = 1 or 0 indicating the propagation possibility of the semiconductor device 16 under test.

As a result, even when there is a demand for ultra-high integration and ultra-high density of the semiconductor device 16 under test, failure detection and evaluation can be simplified, and the design period of the logic gate can be shortened. It will be possible.

Further, according to the second circuit fault pseudo test method of the present invention, step P in the flow chart of FIG.
In the calculation storage processing of 3, the storage processing of the scheduled propagation times ts1 and ts0 relating to the failure information fSa0 and fSa1 and the failure information fSa0 whose current time tc has passed the scheduled propagation times ts1 and ts0,
A calculation process for determining the failure information DSa0, DSa1 with fSa1 valid is executed.

Therefore, the logic gates LG1, LG2, LGi ...
When the fault point FLT is set in LGn, for example, even if a signal change (event) occurs in the input net, no event occurs in the output net of the normal circuit, that is, the logic gates LG1, LG2, LGi. ... When a signal change is scheduled to be propagated at a time after the gate delay time of LGn, it is necessary to detect a fault in which the current time tc has passed until the scheduled propagation time ts1, ts0, not the signal generation time of the input net. Is possible. In other words, when the influence of the fault point is transmitted to the output net after the gate delay time, it is assumed that the fault information fSa0, fSa1 at that time is transmitted by the fault "f.
Sa0, fSa1 = 1 ”can be set.

As a result, the logic gates LG1, LG2, L
It becomes possible to execute a fault simulation in accordance with an actual fault circuit in consideration of the gate delay time td of Gi ... LGn with high accuracy.

Further, according to the third circuit fault pseudo test method of the present invention, step P in the flow chart of FIG.
In the calculation storage process of 3, the latest failure information fSa0, fSa1 related to the final failure detection determination time T1 one cycle before the test data DT and an arbitrary failure detection determination time related to the current cycle of the test data DT. Failure information f up to TX
The logical sum operation processing with Sa0 and fSa1 is performed.

Therefore, even if the memory element MEM is included in the logic gates LG1, LG2, LGi ... LGn of the semiconductor device under test 16, the internal state of the memory element MEM which changes with time is, for example, The latest failure information fSa0, fSa1 related to the final failure detection determination time T1 one cycle before the test data DT and the arbitrary failure detection determination time TX related to the current cycle of the test data DT from the final failure detection determination time T1. To determine the fault propagation property related to the memory element MEM by performing an OR operation with "fSa0, fSa1 = 1", which is assumed that the fault information fSa0, fSa1 up to the above has been transmitted even once. Is possible.

In step P4, the memory element M
The detection processing of the failure information fSa0, fSa1 of the logic gates LG1, LG2, LGi ... LGn including EM is executed by the first and second search processing, and after the detection processing, the test data D concerned.
The latest failure information fSa0, fSa1 related to the final failure detection determination time T1 one cycle before T and the final failure detection determination time T1
To all of the failure information MSa0, M from the end to the final failure detection determination time T2 related to the current cycle of the test data DT
The failure information fSa0, f at the final failure detection determination time T2 related to the current cycle of the test data DT is set to Sa1, DSa0, DSa1.
Matches Sa1.

Therefore, even if the influence of the failure of the input net of the memory element MEM is not reflected in the output net by one-time arithmetic processing, the failure information fSa0, fSa1 remaining in the memory element MEM is retained. The failure information fSa0, fSa1 can be detected with good reproducibility without ignoring it.

As a result, it becomes possible to perform a highly accurate failure simulation of the semiconductor device under test 16 including the memory element MEM.

[0051]

Embodiments of the present invention will now be described with reference to the drawings. 4 to 22 are views for explaining the circuit fault pseudo test apparatus and the circuit fault test method according to the embodiment of the present invention.

(1) Description of the First Embodiment FIG. 4 is a block diagram of a circuit failure pseudo test apparatus according to each embodiment of the present invention, and FIGS. 5 and 6 show supplementary explanatory views thereof.

For example, a device for simulating a failure of a semiconductor device under test (hereinafter referred to as LSI under test) 16 having a plurality of logic gates LG1, LG2, LG3 as shown in FIG. Control memory 21, test data file memory 22, failure information memory 23, data search editor 24, CPU 2
5, a display 26, a keyboard 27, and a system bus 28 for transmitting data between them.

That is, the failure simulation control memory 21 is an embodiment of the first storage means 11, and stores the failure mode information Sa0, Sa1 and control data D1 of the LSI under test 16 which are defined in advance. The definition process will be described with reference to FIGS.

The test data file memory 22 is an embodiment of the second storage means 12, and stores the test data DT for performing the failure simulation of the LSI under test 16.

The fault information memory 23 is the third storage means 13.
This is one embodiment of the present invention, and stores the failure information fSa0, fSa1 calculated regarding the failure propagation at each logic gate LG1, LG2, LGi ... LGn by the test data DT (see FIG. 5). In the circuit fault pseudo test method according to the second embodiment, the fault information memory 23 has fault information fSa0, f of the logic gates LG1, LG2, LGi ... LGn of the LSI under test 16.
The scheduled delivery times ts1 and ts0 for each Sa1 are stored.

Further, in the fault information memory 23, in the circuit fault pseudo test method according to the third embodiment, the latest fault information fSa0, fSa1 relating to the final fault detection judgment time T1 one cycle before the test data DT is obtained. And failure information f from the final failure detection determination time T1 to an arbitrary failure detection determination time TX related to the current cycle of the test data DT.
The failure information MSa0, MSa1 based on Sa0, fSa1 is stored.

The data search editor 24 is the information detecting means 1
4 is an embodiment of the present invention, and detects the failure information fSa0, fSa1, MSa0, MSa1 calculated for the failure propagation at each logic gate gate LG1, LG2, LGi ... LGn based on the definition process.

The CPU 25 is an embodiment of the control means 15, and controls the input / output of the failure simulation control memory 21, the test data file memory 22, the failure information memory 23, the data search editor 24, the display 26 and the like. For example, the CPU 25 manages the time of the test data DT, that is, the final failure detection determination time T1 one cycle before the latest information of the failure information fSa0, fSa1 or the test data DT from the final failure detection determination time T1. Failure detection determination time TX relating to the current cycle of
Counting process and so on are performed until.

Further, the CPU 25 sends the test data DT
Failure information DSa0 obtained by performing the OR operation based on the failure information fSa0, fSa1 from the last failure detection determination time T1 one cycle before to the arbitrary failure detection determination time TX related to the current cycle of the test data DT. , DSa1 is output.

The display 26 displays the display data D3.
Based on the above, the LSI under test 16 being designed is displayed. The keyboard 27 is used by an operator or the like to input the input data D2 relating to the failure point FLT when performing the failure simulation. For example, logic gate LG1
The fault point FLT is set in the signal input portion IN of the.

FIG. 5 shows the contents of the failure mode memory table according to the first embodiment of the present invention. Figure 5
, Mi is a failure mode and is classified into the first and second single stuck-at faults M0 and M1. The first single stuck-at fault M0 is a first fixed fault M0 in which the output signal or the input signal of the logic gates LG1, LG2, LGi ... LGn is fixed to the logic "0" when the fault point FLT is set in the LSI under test 16. The stuck-at fault is a failure mode in which only one first stuck-at fault exists in the LSI under test 16.

For example, a two-input OR logic gate (hereinafter OR
This is a mode in which the output value of the logic 1 gate LG i such as a circuit) and a 2-input AND logic gate (hereinafter referred to as an AND circuit) is fixed to logic “0”. This is because a line of the signal input section of the OR circuit or the AND circuit touches the ground line GND, for example, and a "0" level is always applied to one signal input section of the circuit. . As a result, when "1" is input to the other signal input section, the output value of the OR circuit or AND circuit becomes "0". This failure mode information is defined as SaO.

Further, fSaO is failure information indicating the propagation property of the first single stuck-at failure M0 which is an example of the final failure information. For example, fSaO = 0 is defined when the first single stuck-at fault M0 does not propagate to the next-stage logic gate LGi. Further, the case where the first single stuck-at fault M0 propagates to the logic gate LGi of the next stage is defined as fSaO = 1.

The second single stuck-at fault M1 is the LSI under test.
When the fault point FLT is set in 16, the logic gate LG
It is a failure mode in which the output signal or the input signal of 1, LG2, LGi ... LGn is the second stuck-at fault fixed to the logic "1", and only one second stuck-at fault exists in the LSI under test 16. For example, this is a mode in which the output value of the logic gate LG i of the OR circuit, the AND circuit, or the like is fixed to the logic “1”.

This is because one line of the signal input section of the OR circuit or AND circuit is opened due to a failure such as disconnection, and the "1" level is always applied to one signal input section of the circuit. It is something. As a result, when "1" is input to the other signal input section, the output value of the OR circuit or AND circuit becomes "1". This failure mode information is defined as Sa1. Further, fSa1 is failure information indicating the propagation property of the second single stuck-at failure M1 which is an example of the second failure information. For example, fSa1 = 0 is defined when the second single stuck-at fault M1 does not propagate to the next-stage logic gate LGi. Further, fSa1 = 1 is defined when the second single stuck-at fault M1 propagates to the logic gate LGi at the next stage.

The defined failure mode information Sa0, S
a1, first and second failure information fSa0, fSa1 are stored in the failure simulation control memory 21 as control data D1.

FIG. 6 shows the contents of the failure information memory table according to the first embodiment of the present invention. In FIG. 6, m is the content of the failure information memory table, for example, failure information storage when the failure point FLT is set in either of the input nets A and B of the logic gate LGi such as an OR circuit and an AND circuit. It shows the situation.

For example, the failure information fSa0 = 1 for the input net A of the OR circuit is stored in the first net A.
In this case, the single stuck-at fault M0 exists and is propagated to the logic gate LG i at the next stage. The output value of the OR circuit at this time is different from the output value at the normal time. Also,
Similarly, the failure information fSa1 = 0 for A is stored when the second single stuck-at failure M1 exists in the net A and is not transmitted to the logic gate LGi at the next stage. The output value of the OR circuit at this time is the same as the output value at the normal time.

Further, the failure information fSa0 = 0 for the input net B of the OR circuit is stored in the first net B.
This is the case where the single stuck-at fault M0 exists and the signal is not propagated to the logic gate LG i at the next stage. The output value of the OR circuit at this time is the same as the output value at the normal time.
Similarly, the failure information fSa1 = 0 for the net B is stored only when the second single stuck-at failure M1 exists in the net B and is not propagated to the logic gate LGi at the next stage. is there. The output value of the OR circuit at this time is the same as the output value at the normal time.

The fault information fSa0 = 0 is stored for the input net A of the AND circuit only when the first single stuck-at fault M0 exists in the net B, and the logic gate LGi of the next stage is stored. This is the case when you don't spread to. AN at this time
The output value of the D circuit is different from the output value at the normal time.

Similarly, failure information fSa1 for A =
0 is stored when the second single stuck-at fault M1 exists in the net A and is not transmitted to the logic gate LGi at the next stage. This is a case where the output value of the AND circuit at this time becomes the same as the output value at the normal time.

Further, the fault information fSa0 = 0 is stored for the input net B of the AND circuit only when the first single stuck-at fault M0 exists in the net B, and the logic gate LGi of the next stage is stored. This is the case when you don't spread to. A at this time
This is the case where the output value of the ND circuit becomes the same as the output value at the normal time.

Similarly, the failure information f for the net B is
Sa1 = 0 is stored when the second single stuck-at fault M1 exists in the net B and is propagated to the logic gate LGi at the next stage. This is a case where the output value of the AND circuit at this time becomes the same as the output value at the normal time.

The failure information fSa0 = 0, fS
By supplying the test data DT to the LSI under test 16, a1 = 0, fSa1 = 1, fSa0 = 1 are calculated regarding the failure propagation in each logic gate LGi and obtained as a failure flag. This failure information fSa0 = 0, fSa1 = 0, fSa1
= 1 and fSa0 = 1 are stored in the failure information memory 23.
The amount of data is determined by the circuit configuration of the LSI under test 16. Therefore, compared with the conventional example, the failure information memory 23
The amount of failure information stored in is greatly reduced.

As described above, according to the circuit fault pseudo test apparatus of each embodiment of the present invention, as shown in FIG. 4, the fault simulation control memory 21, the test data file memory 22, the fault information memory 23, the data retrieval editor. Two
4, CPU 25, etc. are provided.

For example, a plurality of logic gates LG1, LG2, L
Failure point FLT on LSI under test 16 in which Gi ... LGn is incorporated
Is set and a failure simulation is performed, failure mode information Sa0 and Sa1 of the LSI under test 16 which is defined in advance is stored in the failure simulation control memory 21,
The test data DT for simulating the failure of the LSI under test 16 is stored in the test data file memory 22.

Fault information fSa0, fSa1 output from each logic gate LG1, LG2, LGi ... LGn based on the test data DT is stored in the fault information memory 23 via the CPU 25.
Failure information fSa0, fSa stored by
1 is detected by the data search editor 24.

Therefore, the output values of the logic gates LG1, LG2, LGi ... LGn are calculated in the logic circuit having the fault point and the logic circuit having no fault point with respect to the test data DT, respectively, until the two coincide with each other, or Until the external output point is reached, the comparison / judgment editor 4 and the CPU 5 do not have to perform comparison and arithmetic processing as in the conventional example.

As a result, the burden on the CPU 25 is to calculate the fault information fSa0, fSa1 obtained from the input points of the respective logic gates LG1, LG2, LGi ... LGn, and to store it in the fault information memory 2
The processing to be stored in 3 is reduced.

Further, the influence of the fault point FLT depends on the LSI 1 under test.
Regarding whether to propagate to the signal output unit (fault detection determination point) 6 (fault propagation property), it is determined for each output point of each logic gate LG1, LG2, LGi ... LGn for each fault. Since it is not performed, each logic gate LG1 as in the conventional example,
It becomes unnecessary to store the calculation result data of the output values of LG2, LGi ... LGn.

The logic gate LG of the LSI under test 16
By storing the scheduled transfer time ts1, ts0 for each of the failure information fSa0, fSa1 of 1, LG2, LGi ... LGn in the failure information memory 23, the gate delay time td of the logic gate LG1, LG2, LGi ... It is possible to perform a highly accurate failure simulation that includes this (see Fig. 11). .

Further, the latest failure information fSa related to the final failure detection determination time T1 one cycle before of the test data DT.
0, fSa1 and failure information MSa0, MSa1 based on all the failure information fSa0, fSa1 from the final failure detection determination time T1 to an arbitrary failure detection determination time TX related to the current cycle of the test data DT. By storing in the failure information memory 23, it is possible to perform a highly accurate failure simulation for the LSI under test 16 including the flip-flop circuit FF having state storage.

As a result, it is possible to reduce the use (occupancy) time of the CPU 25 and the memory capacity of the failure information memory 23 as compared with the conventional example. Next, a circuit fault pseudo test method according to an embodiment of the present invention will be described with supplementing the operation of the device.

FIG. 7 is a process flow chart of the circuit fault pseudo test according to the first embodiment of the present invention, and FIG. 8 shows its supplementary explanatory diagram.

For example, in the case of performing the failure simulation of the LSI under test 16 in which the three-stage logic gates LG1 = AND circuit, LG2 = OR circuit, LG3 = AND circuit as shown in FIG. 8 are incorporated, in FIG. In step P1, the failure modes M0 and M1 of the LSI under test 16 are defined and the failure information fSa0 and fSa1 indicating the failure transfer is defined.
In the embodiment of the present invention, it is assumed that the fault point FLT [fSa1 = 1] is set in the input net A of the LSI under test 16.

The definition processing of the failure modes M0 and M1 at this time is the first stuck-at failure in which the output signal or the input signal of the logic gates LG1, LG2, LGi ... LGn is fixed to the logic "0". The first single stuck-at fault M0 having only one stuck-at fault in the LSI under test 16 and the logic gates LG1, LG
2, a second stuck-at fault in which an output signal or an input signal of LGn is fixed to a logic "1", and only one stuck-at second fault exists in the LSI under test 16. Define as M1.

Also, the failure information fSa0, fSa indicating the failure transfer.
The definition process of 1 is as follows for the first single stuck-at fault M0.
It is defined as the first failure information fSa0 = 1 or 0 indicating the presence / absence of transfer to the logic gate LGj in the next stage. Further, the second single stuck-at fault M1 is defined as the second fault information fSa1 = 1 or 0 indicating the presence / absence of transmission to the logic gate LGj of the next stage (see FIGS. 5 and 6).

Then, in step P2, the test data DT is supplied to the signal input portion IN of the LSI under test 16.
At this time, the test data DT for simulating the failure of the LSI under test 16, for example, “0, 1, 1, 1” is read by the test data file memory 22 via the CPU 25.

Then, in step P3, the test data DT
Based on each logic gate LG1 = AND circuit, LG2 = OR
The circuit, LG3 = AND circuit, calculates and stores the failure information fSa0, fSa1 regarding the failure transfer. At this time, the failure information fSa0, fSa1 calculated by the respective logic gates LG1, LG2, LG3 based on the test data DT is stored in the failure information memory 23 via the CPU 25.

In the embodiment of the present invention, each net C, D,
It shows a case where E, F, and G have the failure information fSa0 = 1. Thereafter, in step P4, the failure information fSa0, fSa1 defined for each net is detected from the signal output unit OUT of the LSI under test 16 toward the signal input unit IN. At this time, the failure information fSa0, fSa based on the definition process
1 is detected by the data search editor 24.

For example, it is checked whether or not there is a signal change inside the circuit at a preset failure detection determination time, and the failure information fSa0, fSa1 for each net is output from the signal output unit OUT which becomes the failure detection determination point G. Tracking is started.

Then, in step P5, the failure information fSa0, f
It is determined whether any one of Sa1 is "1" and both fSa0 and fSa1 are "1" or both of fSa0 and fSa1 reach "0" and the signal input unit IN.
At this time, if any of the failure information fSa0, fSa1 is "1" and both fSa0, fSa1 are "1" (YES), the process proceeds to step P6.

If both of the failure information fSa0 and fSa1 reach "0" and the signal input section IN (NO), the process proceeds to step P7 to interrupt the detection processing of the failure information fSa0 and fSa1. It is determined that "the test data DT cannot detect a failure". In the embodiment of the present invention, the net A has fSa1 = 1, but the failure information fSa0, fSa1 of the net E from the failure detection determination point G to the net A is "0".
Therefore, the failure information fSa0, fSa1 is net E
Is interrupted by.

Therefore, "test data DT =" 0, 1,
"1,1", the "1" stuck-at fault cannot be observed at the fault detection determination point G ". In step P6, it is determined that "the influence of the fault point FLT can be observed by the test data DT". That is, the test data DT = “0,1,1,1” makes it possible to observe the “0” stuck-at faults of the input nets C, D, E, F, G from the fault detection judgment point G.

The above steps P1 to P7 are performed for all the faults and all the test data DT to be the targets of fault detection. As a result, the logic gate LG1 = AND circuit, LG2 =
Tested LS incorporating OR circuit, LG3 = AND circuit
I16 failure simulation is performed to obtain information such as the failure detection rate and undetected failure for all failure points targeted for failure detection. In addition, this failure simulation result is
If the LSI 16 to be tested is actually manufactured and there is a failure point inside, it is possible to confirm the existence of the failure point by supplying the test data DT.

As described above, according to the circuit fault pseudo test method of the first embodiment of the present invention, as shown in the flowchart of FIG. 7, in step P1, the first and second single stuck-at faults M0 are generated. Information fSa0, f indicating failure propagation of M1, M1 etc.
Sa1 is defined and the test data DT is processed in step P2.
Supply processing is performed, and at step P3, each logic gate LG1, LG
2. Calculates and stores the failure information fSa0, fSa1 related to failure propagation at LG3.

Therefore, a plurality of logic gates LG1, LG2,
If a failure point FLT is set in the LSI under test 16 that is incorporated into LG3 and a failure simulation is performed, step P4
And signal output section OUT = fault detection judgment point G to signal input section I
The first failure information fSa0 = 1 or 0 indicating the propagation possibility of the first single stuck-at fault M0 toward the N and the second failure information indicating the propagation possibility of the second single stuck-at fault M1. By performing the detection process of fSa1 = 1 or 0, the LSI under test 16
It becomes possible to easily carry out the failure detection evaluation.

As a result, even if the LSI under test 16 becomes extremely highly integrated and highly dense, failure detection evaluation can be simplified and the design period of the logic gate can be shortened.

FIG. 9 shows a flow chart of the LSI logic design method according to each embodiment of the present invention. In FIG. 9, for example, when developing an ultra-high-integrated logic gate array or the like, first, a logic design is performed in step P1, and then a circuit fault pseudo test process according to the present invention is performed in step P2.

After that, in step P3, a process for judging whether the fault coverage is high or low is performed. At this time, when the failure detection rate is high (YES), the process proceeds to step P5 and the failure simulation is performed. If the fault coverage is low (NO)
In step S4, the process moves to step P4 to add or review the test pattern, and step P2 is executed again.

As a result, although it takes a longer time than the logic simulation, it becomes possible to evaluate the fault coverage with a small computer, and the ultra-high integration logic gate array in the design stage is compared with the conventional example in the test data. DT
Based on the above, the failure detection rate and the like can be easily obtained, and the failure detection evaluation can be easily performed. With this,
It is possible to design logic considering test.

(2) Description of Second Embodiment FIGS. 10 to 16 are explanatory views of a circuit fault pseudo test method according to the second embodiment of the present invention, and FIG. 10 shows the circuit fault pseudo test process. 11 is a flowchart, and FIGS. 11 to 16 show supplementary explanatory diagrams thereof.

In FIG. 10, the difference from the first embodiment is that, in the second embodiment, when the failure information fSa0, fSa1 is calculated and stored, the scheduled transmission time t related to the failure information fSa0, fSa1.
It includes a storage process of s1 and ts0 and a calculation process of validating the failure information fSa0 and fSa1 whose scheduled transmission times ts1 and ts0 have passed the present time tc.

This is because even if a signal change (hereinafter referred to as an event) occurs in the input net of the logic gate, the event may not occur in the output net D of the normal circuit due to the gate delay time td. The circuit fault pseudo test method according to the embodiment is supplemented. The scheduled transfer time ts1 is the scheduled time at which the "1" stuck-at failure will be transmitted, and the scheduled transfer time ts0 is the scheduled time at which the "0" stuck-at failure will be transmitted.

For example, as shown in FIG.
When 6 is a 3-input AND circuit (hereinafter simply referred to as a 3-input AND circuit) 26, a failure point FLT is set in the input net A, and the scheduled transfer time ts1 at which 1 stuck-at failure is transferred will be explained. For example, in the process flow chart of FIG. 10 which is a subroutine of step P3 of the process flow chart of FIG. 7, first, in step P1, normal / failure circuit case classification (mode) process is performed.

At this time, in the case of a normal circuit (YES),
Control goes to step P2. In the case of a faulty circuit (N
For (O), the process proceeds to step P5. Therefore, in the case of a normal circuit (YES), the current time tc = 0 in step P2.
Scheduled processing of signal changes related to (hereinafter referred to as event scheduling processing). At this time, in the state transition diagram (a) of the LSI under test shown in FIG. 11, the signal value of the input net (A,
B, C) = (0, 0, 1) for the output net D signal value = “0” is calculated and stored (see FIG. 12).

Next, in step P3, the event scheduling process for the current time tc = 5 is performed. At this time,
At time tc = 5 in FIG. 11B, the signal value of the input net B changes from “0” to “1”, and the signal value of the input net is (A, B, C) = (0, 1, 1 ). In addition, "1"
When the stuck-at failure is transmitted, the scheduled transfer time ts1 is stored, and when the stuck-at failure is "0", the scheduled transfer time ts0 is stored. At this time, the signal value of the output net D remains "0" and does not change (see FIG. 12).

Next, at step P4, the current time tc = 13
Event scheduling processing according to. At this time, the signal value of the input net C changes from “1” to “0” at time tc = 13, which is delayed by 8 hours from the change of the input net in FIG. A, B,
C) = (0,1,0). Also at this time, output net D
The signal value of is still "0" (see FIG. 12).

On the other hand, in the case of a faulty circuit at step P1 (N
For (O), the process proceeds to step P5. Here, 3 inputs A
Assuming that the gate delay time of the ND circuit is set to td = 10 and 1 stuck-at fault = sa1 is set in the input net A, the current time tc has passed the scheduled transfer time (hereinafter referred to as event schedule time) ts1 and ts0. Explain the cases where it is and when it is not.

Therefore, in step P5, the event scheduling process for the current time tc = 0 at which the failure is set is performed. At this time, in the state transition diagram of the LSI under test of FIG. 11A, the signal value (A, B, C) of the input net at time tc = 0, which is the first state, is (1, 0, 1). The signal value of the output net D = “0” is calculated and stored as in the normal circuit (see FIG. 13).

Next, in step P6, the event scheduling process for the current time tc = 5 is performed. At this time,
At time tc = 5 in FIG. 11B, the signal value of the input net B changes from “0” to “1”, and the signal value of the input net is (A, B, C) = (1, 1, 1 ). The signal value of the output net D at this time changes to "1". This allows
The event schedule time ts1 = 15 obtained by adding the gate delay time td = 10 and the current time tc = 5 is stored (see FIG. 13).

Next, at step P7, the current time tc = 13
Event scheduling processing according to. At this time, the signal value of the input net C changes from “1” to “0” at the time tc = 13 eight hours after the change of the input net in FIG. A, B,
C) = (0,1,0). Also at this time, output net D
The signal value of is still "0" (see FIG. 13).

Further, in step P8, the current time tc is compared with the event schedule time ts1. At this time, if the current time tc has passed the event schedule time ts1 (YES), the process proceeds to step P9,
If it has not passed (NO), step P
Move to 10.

For example, when the current time tc has not passed the event schedule time ts1 (NO) as shown in the content transition diagram of the failure information memory of FIG. 13, the event schedule processing is invalidated in step P10.

This is because when the rising delay time td of the previously set logic gate is 10, the output net D
The signal value of “0” changes from “1” to the event schedule when the signal value of the output net D = “1” at the event schedule time ts1 = 15, which is 10 time behind the change of the input net B. It is based on what has been processed.

As a result, since the signal value of the output net D at the current time tc = 13 has not changed, the event schedule processing at the event schedule time ts1 = 15 becomes invalid. Note that FIG. 15 is a content transition diagram of the failure information memory under normal conditions.

When the current time tc has passed the event schedule time ts1 (YES) as shown in the content transition diagram of the failure information memory of FIG. 16, the event schedule processing is validated in step P9. Here, the failure information fSa0, fSa1 related to the event schedule time ts1 and the failure information fSa0, fSa1 related to the current time tc are compared. Further, calculation processing is performed to validate the failure information fSa0, fSa1 whose event schedule time ts1 has passed the current time tc.

In the state transition diagram (b) of the LSI under test of FIG. 14, this is input at the current time tc = 17 12 hours after the event occurs in the input net B as shown in FIG. 14 (c). Assuming that an event in which the signal value changes from "1" to "0" occurs in the net C, the event occurrence of the input net B in FIG. 14 (b) has already occurred at the current time tc = 17 at this time. Event schedule time of output net D = 1 set at the time, that is, scheduled delivery time ts1
= 15 has passed, the previously set failure information fSa0, fSa1 is fSa0, f that the failure is transmitted.
Sa1 = 1 is valid. This is defined as failure information DSa0, DSa1 based on the scheduled delivery time ts1 and ts0 (see FIG. 16).

As described above, according to the circuit fault pseudo test method of the second embodiment of the present invention, the calculation storage process of steps P3 and P6 of the process flowchart of FIG.
The event schedule times ts1 and ts0 related to the failure information fSa0 and fSa1 are stored, and the current time t is set in Step P9.
The calculation processing for validating the failure information fSa0, fSa1 having passed c is executed.

Therefore, when the fault point FLT is set in the 3-input AND circuit 26, for example, even if a signal change (event) occurs in the input net, the output net D of the normal circuit is output.
If no event occurs in, ie, the 3-input AN
In the case where a signal change is expected to be transmitted at a time after the gate delay time td of the D circuit 26, the current time tc is not the signal generation time of the input net, but the current propagation time ts1, t.
It becomes possible to detect failures that have passed up to s0.

In other words, when the influence of the fault point FLT is transmitted to the output net D after the gate delay time td, it is assumed that the fault information fSa0, fSa1 at that time is transmitted by the fault "DSa0, DSa1 =". 1 ”.

As a result, as compared with the first embodiment, the failure information fSa0, fSa1 is set in the second embodiment in consideration of the event schedule time, so that the logic gates LG1, LG2, shown in FIG. Gate delay time t of LGi ... LGn
It is possible to execute a failure simulation in accordance with an actual failed circuit including d with high accuracy. With this,
As in the first embodiment, it is possible to improve the practicality of the failure detection evaluation.

(3) Description of Third Embodiment FIGS. 17 to 22 are explanatory diagrams of a circuit fault pseudo test method according to the third embodiment of the present invention, and FIG. 17 is a process of the circuit fault pseudo test. It is a flowchart and FIGS. 18-22 has shown the supplementary explanatory drawing.

In FIG. 17, the difference from the first and second embodiments is that in the third embodiment, when the failure information fSa0, fSa1 is calculated and stored, the final failure one cycle before the test data DT is concerned. The latest failure information fSa0, f related to the detection determination time T1
The storage processing of the failure information fSa0, fSa1 up to the failure detection determination time TX of the current cycle of Sa1 and the test data DT, and the failure information fSa0, fSa related to both times T1, TX.
The logical sum operation processing of 1 is included.

Note that, in order to simplify the explanation, this flowchart is based on steps P3 and P of the flowchart of FIG.
The sub-run processing according to No. 4 is shown, and the LSI under test 36 with a flip-flop (hereinafter referred to as FF circuit) circuit is shown.
The failure detection judgment time of is assumed to be set at only one place within one cycle of the test data DT, and the state change is
It is assumed that no state other than the state transition diagrams (a) to (b) of the LSI under test with 21 FF circuits has occurred.

For example, a buffer circuit B as shown in FIG.
1 to B5, LSI under test consisting of inverters IN1 and IN2
36 includes an FF circuit 36A as shown in FIG. 18,
In the process flow chart of FIG. 17, first, step P
1, the latest failure information fSa0, fSa1 related to the final failure detection determination time T1 one cycle before the test data DT of the LSI under test 36 and the arbitrary failure related to the current cycle of the test data DT from the final failure detection determination time T1. The failure information fSa0, fSa1 up to the failure detection determination time TX is stored (see FIGS. 19 and 20).

FIG. 18 shows 27 kinds of outputs for the signal input states XPR (reset), D (data), CK (clock), XCL (clear), internal state M and output state Q of the FF circuit 36A. The state is organized, and the output state in which an indefinite value "X" is involved in addition to the input logic signals "1" and "0" is shown.

At this time, the LSI under test with the FF circuit of FIG.
In the state transition diagram (a) and the time chart of Fig. 21,
The input net (A,
The failure information fSa0, fSa1 of each net based on the signal values (1, 0, 1, 1) of (B, C, D) is stored in the failure information memory 23.

Further, in the state transition diagram (b) of the LSI under test with the FF circuit of FIG. 20, similarly, the signal value (1) of the input net (A, B, C, D) related to the arbitrary failure detection determination time T2 is also set. , 1, 0, 1) failure information fSa0 of each net based on
fSa1 is stored in the failure information memory 23.

Next, in step P2, the failure information fSa0, fSa1 between the final failure detection determination time T1 and the arbitrary failure detection determination time TX and the latest failure information fSa0, fSa1 related to the final failure detection determination time T1. Performs a logical sum operation with.

For example, the latest failure information fsa1 and fsa0 at the failure detection determination time T1 and the failure detection determination times T1 to n
The fault information fsa1 and fsa0 is "1" even once during the fault detection determination time T2 related to the + 1st test pattern cycle.
The logical sum is calculated with the failure information fsa1 and fsa0 that have become.

Failure information fsa1 and fsa0 related to this logical sum
Is the final failure detection determination time T2 of the test data DT.
It is defined as failure information Msa1 and Msa0 related to. Similarly, the latest f at the failure detection determination time T1 is stored in the failure information memory 23 during the failure detection determination processing at the failure detection determination time T3.
Fault information Msa1 related to the logical sum of sa1 and fsa0 and the fault information fsa1 and fsa0 that has become “1” even once between the fault detection determination time T1 and the fault detection determination time T3.
Msa0 is stored.

In step P3, the first search processing from the signal output unit OUT of the LSI under test 36 to the FF circuit 36A is performed. At this time, for example, in the state transition diagram (b) of the LSI under test with the FF circuit of FIG. 20, assuming that the failure detection determination process is performed at the failure determination time T2 of FIG. 22B for explaining the detection processing of FIG. 22, the FF circuit 36A retrieves the latest failure information fsa1, fsa0 in the net on the external output terminal side A.

As a result, the stuck-at-1 fault sa1 existing in the nets J and K and the stuck-at-0 fault sa0 existing in the net L can be detected. Further, in step P4, the FF circuit 36
The second search processing from the input section of A to the signal input section IN of the LSI under test 36 is performed. At this time, for example,
22 is a state transition diagram (a) of the LSI under test with FF circuit 20 and assuming that the failure detection determination process is performed at the failure determination time T1 of FIG. 21, the second search process of FIG.
In the diagram (a) for explaining the detection processing of, the FF circuit 36A
For the net on the external input terminal (signal input unit IN) side B, the second search processing for detecting the latest and other than the latest failure information Msa1 and Msa0 held in the failure information memory 23 is performed.

For example, in the time chart of FIG.
Failure detection determination time T related to the nth test pattern cycle
The latest and non-latest failure information fsa1 and fsa0 held in the failure information memory 23 in No. 1 are searched.

Then, in step P5, the latest failure information fSa0, fSa1 relating to the final failure detection determination time T1 one cycle before the test data DT and the current test data DT from the final failure detection determination time T1. Failure information MSa0, M until an arbitrary failure detection determination time TX related to a cycle is reached
Performs calculation processing to match Sa1.

The contents of the failure information memory 23 at the end of the failure detection determination process at the failure detection determination time T3 are as follows:
It is used for the failure detection determination process related to the (n + 2) th test pattern cycle.

As a result, the latest failure information fsa1, fsa0 in the net on the external output terminal side A is retrieved, and by checking the failure information fsa1, fsa0, the first
In this embodiment, the 1 stuck-at fault sa1 existing in the undetected net B can be detected.

As described above, according to the circuit fault pseudo-test method of the third embodiment of the present invention, an arbitrary fault detection determination time TX from the last fault detection determination time T1 in step P2 of the flowchart of FIG. Failure information fSa up to
The logical sum operation processing with 0 and fSa1 is performed.

Therefore, the LSI to be tested 36 is provided with the FF circuit 36.
Even if A is included, it changes with time F
Regarding the internal state of the F circuit 36A, for example, the latest failure information fSa0, fSa1 relating to the final failure detection determination time T1 one cycle before the relevant test data DT and the current test data DT from the final failure detection determination time T1 Failure information fSa0, f up to an arbitrary failure detection determination time TX related to the cycle
Assuming that the failure of Sa1 is transmitted even once, "fSa0, fSa1 =
By performing the logical sum operation of
It becomes possible to judge the failure propagation property of the F circuit 36A.

In steps P3 and P4, FF
Failure information fSa0 of the LSI under test 36 including the circuit 36A,
fSa1 is executed by the first and second search processing, and after the detection processing, the latest failure information fSa0, fSa1 related to the final failure detection determination time T1 one cycle before the test data DT is determined in step P5. Failure information MSa0, MSa at the final failure detection determination time T2 related to the current cycle of the test data DT
Matches 1

Therefore, depending on one calculation process, F
Even when the influence of the failure of the input net of the F circuit 36A is not reflected in the output net D, the "0" stuck-at fault M0 and the "1" stuck-at fault M1 remaining in the FF circuit 36A are not ignored. The faults M0 and M1 can be detected with good reproducibility.

As a result, the 1 stuck-at fault sa1 existing in the net B, which has not been detected in the first embodiment, can be detected. Therefore, the LSI 36 under test including the flip-flop circuit 36A and the like having the state memory can be detected. It becomes possible to perform a highly accurate failure simulation of.

[0145]

As described above, according to the apparatus of the present invention, the first, second and third storage means, the information detection means and the control means are provided, and each of them is based on the test data of the LSI under test. Failure information calculated regarding failure propagation in the logic gate is stored in the third storage means via the control means,
Failure information based on the failure mode information defined in advance is detected by the information detecting means.

Therefore, the output value at the output point of each logic gate with respect to the test data becomes the failure information which has been defined in advance when the failure is propagated. As a result, the burden on the control means is reduced to the storage processing of the failure information remaining at the input points of the respective logic gates. Further, with respect to the failure transfer from the failure point to the failure detection determination point, the determination of each failure point is not made for each output point of each logic gate, so that a large-capacity memory as in the conventional example is unnecessary.

By storing the expected transfer time relating to the failure information for each logic gate of the semiconductor device under test in the third storage means, a highly accurate failure simulation including the delay time of the logic gate is performed. It becomes possible.

Further, the calculation result based on the latest failure information related to the failure detection determination time of one cycle before the test data and the failure information from the failure detection determination time to the failure detection determination time of the current cycle. Based on the data, it becomes possible to perform a highly accurate failure simulation of the semiconductor device under test including the memory element having the state memory.

As a result, it is possible to reduce the use (occupancy) time of the control means and the memory capacity of the failure information memory as compared with the conventional example. Further, according to the first to third circuit fault pseudo test methods of the present invention, the definition process of the fault information indicating the fault propagation such as the first and second single stuck-at faults, the process of supplying the test data, Failure processing such as storage processing of scheduled time of failure related to failure information, judgment of validity of the failure information based on the current time, and OR operation processing of latest failure information and failure information related to past failure detection determination time I am doing the calculation and memory processing for Hata.

Therefore, when a failure point is set in the LSI under test in which a plurality of logic gates including memory elements are incorporated and a circuit failure simulation is carried out, the first failure detection judgment point is moved toward the signal input section. By detecting the final failure information 1 or 0 indicating the propagation possibility of the single stuck-at fault or any failure information 1 or 0 indicating the propagation possibility of the second single stuck-at fault, the failure is detected. It becomes possible to easily carry out the failure detection evaluation of the LSI under test based on the failure judgment.

Further, based on the storage processing of the scheduled transfer time relating to the failure information, the failure simulation in accordance with the actual failure circuit including the delay time of the logic gate is executed with the processing time of about 5 times that of the logic simulation. It becomes possible.

Furthermore, even when the semiconductor device under test includes a memory element, the validity judgment of the failure information based on the current time, the latest failure information, and the failure information relating to the past failure detection judgment time are performed. It becomes possible to judge the failure propagation property related to the memory element by executing the logical sum operation processing and the like. As a result, it becomes possible to perform a highly accurate failure simulation of the semiconductor device under test including the memory element using a small computer.

As a result, even when there is a demand for manufacturing a semiconductor integrated circuit device having several million gates including a memory element, failure detection and evaluation can be simplified, which contributes to shortening the design period of the logic gate. However, it is big.

[Brief description of drawings]

FIG. 1 is a principle diagram (1) of a circuit failure pseudo test apparatus according to the present invention.

FIG. 2 is a principle diagram (No. 2) of the circuit fault pseudo test apparatus according to the present invention.

FIG. 3 is a principle diagram of a circuit fault pseudo test method according to the present invention.

FIG. 4 is a configuration diagram of a failure simulation system according to each embodiment of the present invention.

FIG. 5 is an explanatory diagram of contents of a failure mode memory table according to each embodiment of the present invention.

FIG. 6 is an explanatory diagram of contents of a failure information memory table according to each embodiment of the present invention.

FIG. 7 is a process flowchart of a circuit fault pseudo test according to the first embodiment of the present invention.

FIG. 8 is a supplementary explanatory diagram of the circuit fault pseudo test method according to the first embodiment of the present invention.

FIG. 9 is a flowchart of an LSI logic design method according to each embodiment of the present invention.

FIG. 10 is a processing flowchart of a circuit failure pseudo test according to a second embodiment of the present invention.

FIG. 11 is a state transition diagram (part 1) of the LSI under test according to the second embodiment of the present invention.

FIG. 12 is a content transition diagram (part 1) of the failure information memory at a normal time according to the second embodiment of the present invention.

FIG. 13 is a content transition diagram (1) of a failure information memory at the time of failure according to the second embodiment of the present invention.

FIG. 14 is a state transition diagram (part 2) of the LSI under test according to the second embodiment of the present invention.

FIG. 15 is a content transition diagram (part 2) of the failure information memory at the normal time according to the second embodiment of the present invention.

FIG. 16 is a content transition diagram (part 2) of the failure information memory at the time of a failure according to the second embodiment of the present invention.

FIG. 17 is a processing flowchart of a circuit failure pseudo test according to a third embodiment of the present invention.

FIG. 18 is an explanatory diagram of a flip-flop circuit according to a third embodiment of the present invention.

FIG. 19 is a supplementary explanatory diagram of the circuit fault pseudo test method according to the third embodiment of the present invention.

FIG. 20 is a state transition diagram of an LSI under test with an FF circuit according to a third embodiment of the present invention.

FIG. 21 is a time chart illustrating a failure determination time according to the third embodiment of the present invention.

FIG. 22 is an explanatory diagram of a detection process of the LSI under test with the FF circuit according to the third embodiment of the present invention.

FIG. 23 is a configuration diagram illustrating a failure simulation according to a conventional example.

FIG. 24 is a processing flowchart of a comparison / determination editor according to a conventional example.

[Explanation of symbols]

11 ... First storage means, 12 ... Second storage means, 13 ... Third storage means, 14 ... Information detecting means, 15 ... Control means, LG1, LG2, LGi, LGn ... Logic gate, MEM ... Storage element , DT ... Test data, D1 ... Control data, Sa0, Sa1 ... Failure mode information, fSa0, fSa1, DSa0, DSa1, MSa0, MSa1 ... Failure information, FLT ... Failure point, ts1, ts0 ... Scheduled time, tc ... Current time, td ... Gate delay time, IN ... Signal input section, OUT ... Signal output section.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location G06F 11/26 310 9072-5B

Claims (10)

[Claims] 1. A plurality of logic gates (LG1, LG2, LGi ...
LGn) is a device for simulating a failure of a semiconductor device under test (16), in which failure mode information (Sa0, Sa) of the semiconductor device under test (16) defined in advance is provided.
1) and first storage means (11) for storing control data (D1), and second storage means (12) for storing test data (DT) for simulating a failure of the semiconductor device under test (16). And the failure information (fSa0, fSa1, MSa0, calculated by the test data (DT) regarding the failure propagation in each logic gate (LG1, LG2, LGi ... LGn).
Third storage means (1 for storing MSa1, DSa0, DSa1)
3) and failure information (fSa0, fSa1 based on the definition process).
, MSa0, MSa1, DSa0, DSa1), and information input / output of the first, second, third storage means (11, 12, 13) and information detection means (14). And a control means (15) for controlling the circuit fault simulation test apparatus. 2. The circuit failure pseudo test apparatus according to claim 1, wherein the third storage means (13) has failure information of logic gates (LG1, LG2, LGi ... LGn) of the semiconductor device under test (16). Scheduled time (ts) for each fSa0, fSa1
0, ts1) is stored in the circuit fault pseudo test apparatus. 3. The circuit fault pseudo test apparatus according to claim 1, wherein the third storage means (13) has a final fault detection determination time (T) one cycle before the test data (DT).
Failure information (fSa0, fSa1) from 1) to an arbitrary failure detection determination time (TX) related to the current cycle of the test data (DT) and the scheduled transfer time (ts0, ts1).
A circuit failure pseudo-testing device characterized by storing failure information (DSa0, DSa1) relating to the above. 4. A plurality of logic gates (LG1, LG2, LGi ...
A method of simulating a failure of a semiconductor device under test (16) in which LGn) is incorporated, wherein a failure mode (M0, M1) of the semiconductor device under test (16) is defined in advance to indicate a failure propagation. Information (fSa0, fSa1) is defined, and the signal input unit (I) of the semiconductor device under test (16) is tested.
N) is supplied with test data (DT), and each logic gate (LG1, LG) is supplied based on the test data (DT).
2. Fault information (fSa for LGi ... LGn) regarding fault transfer
0, fSa1) is calculated and stored, and the signal output unit (OUT) of the semiconductor device under test (16) is connected to the signal input unit (I).
A circuit fault pseudo-testing method, characterized in that the fault information (fSa0, fSa1) is detected toward N). 5. The circuit fault pseudo-test method according to claim 4, wherein the fault mode (M0, M1) definition process is:
When a failure point (FLT) is set in the semiconductor device under test (16), the logic gates (LG1, LG2, LGi ... L)
Gn) is a first stuck-at fault in which the output signal or the input signal is fixed to logic "0", and the first stuck-at fault exists only once in the semiconductor device under test (16). The stuck-at fault (M0) and the logic gates (LG1, LG2, LGi ...
LGn) is a second stuck-at fault in which the output signal or the input signal is fixed to logic "1", and the second stuck-at fault exists only once in the semiconductor device under test (16). A circuit fault pseudo-testing method characterized in that it is defined as a stuck-at fault (M1). 6. The circuit fault pseudo test method according to claim 4, wherein the fault information (fSa0, fSa1) indicating the fault propagation.
The definition processing of the first single stuck-at fault (M0) is defined as the first fault information (fSa0 = 1 or 0) indicating the presence or absence of transmission to the logic gate (LGj) of the next stage. However, for the second single stuck-at fault (M1), the second fault information (f) indicating the presence / absence of transfer to the logic gate (LGj) at the next stage.
Sa1 = 1 or 0) is defined as a circuit fault pseudo test method. 7. The circuit fault pseudo-testing method according to claim 4, wherein the calculation storage process includes the logic gate (LG).
When a fault point (FLT) is set to 1, LG2, LGi ... LGn), the logic gate (LG) of the semiconductor device under test (16) is tested.
1, LG2, LGi ... LGn) failure storage information (fSa0, fSa1) for each failure information scheduled time (ts0, ts1) storage processing, and the previous signal change time related to the scheduled propagation time (ts0, ts1). Based on the comparison processing of the failure information (fSa0, fSa1) of the above and the failure information (fSa0, fSa1) at the time of the signal change related to the current time (tc), the scheduled transfer time (ts0, ts1) is the current time (tc). ) Has passed, failure information (fSa0, fSa1) is validated and failure information (DSa0, DSa1) calculation processing is included. 8. The circuit failure pseudo test method according to claim 4, wherein the semiconductor memory device under test (1
When the memory element (MEM) is included in 6), the latest failure information (fSa0, fSa1) relating to the final failure detection determination time (T1) one cycle before the test data (DT) and the final Of the failure information (fSa0, fSa1) from the failure detection determination time (T1) to the arbitrary failure detection determination time (TX) related to the current cycle of the test data (DT), and the final failure. Failure information (MSa0, MSa1) between the detection determination time (T1) and the arbitrary failure detection determination time (TX) related to the current cycle, and the latest failure at the arbitrary failure detection determination time (TX) related to the current cycle. Information (fSa0,
fSa1) and a circuit fault pseudo test method including a logical sum operation process. 9. The circuit failure pseudo-testing method according to claim 4, wherein the detection processing includes a semiconductor device under test (16).
When the memory element (MEM) is included in the memory element (MEM), the memory element (M
The first search processing up to EM) and the storage element (M
A circuit failure pseudo-test method including a second search process from the input part of (EM) to the signal input part (IN) of the semiconductor device under test (16). 10. The circuit failure pseudo-testing method according to claim 4, wherein when the memory device (MEM) is included in the semiconductor device under test (16), the test data (DT) is included in the calculation memory process. ) Failure information (fSa0, fSa1, DSa0, DSa) related to the final failure detection determination time (T2) in the current cycle.
After the detection process of 1, 1, MSa0, MSa1), the final failure detection determination time (T
All failure information (MSa0, MSa1, DSa0, DSa1) from 1) to the final failure detection determination time (T2) related to the current cycle of the relevant test data (DT) is the current cycle of the relevant test data (DT). The circuit fault pseudo test method including a calculation process for matching the latest fault information (fSa0, fSa1) at the final fault detection determination time (T2) according to the above.