JPH01240939A - Fault simulation system - Google Patents

Abstract

PURPOSE:To process fault simulation at high speed by setting fault information flags on the input/output pins of all logic gates in a logic circuit, and finding a faulty part on a path through which a fault is propagated to the output pin of the logic circuit. CONSTITUTION:A fault detecting part decision processing 16 is performed in such a way that a fault propagation type set on each logic in a fault input processing 17 and the fault information flag set on the output pin of the logic circuit by a fault information propagation rule in a fault information propagation rule file 15 are propagated from an output side to an input side and converted. And the fault information flags are set on the input/output pins of all of the logic gates in the logic circuit, and the processing to find the fault detecting part on the path through which the fault is propagated to the output pin of the logic circuit is performed. The processing to find the fault detecting part on the path through which the fault is propagated to the output pin of the logic circuit is performed only in such a way that the fault information flag is decided advancing from the output pin to the input pin according to the fault information propagation rule. In such a way, a processing procedure required for the judgement of fault detection can be simplified, and the parts where all of the faults are detected for given input patterns can be found at high speed.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a fault simulation method, and in particular, generates an input cover pattern of an input signal sequence for testing a logic circuit, and uses the generated input cover pattern to simulate a fault simulation method in a logic circuit. Evaluate what kind of failures can be inspected, and
Fault simulation method% formula% for analyzing the behavior of logic circuits when they fail [Prior technology] Traditionally, when simulating faults in logic circuits, a single stuck-at fault is assumed in the target logic circuit, and all possible Several methods have been proposed to efficiently process fault simulations and normal logic circuit simulations as many times as the number of faults. For example, such failure simulation methods include a parallel method, a concurrent method, and a destructive method.

However, no matter which method is used, if the number of logic gates in the target logic circuit exceeds several thousand gates, the simulation processing time will increase dramatically.
It's not practical.

To deal with this, there is a simulation method called the critical path tracing method, which directly finds the location where a fault is detected in a single search. This method does not assume failures in advance, but instead uses information from normal logic circuit simulation results to determine what kind of failures will occur at the input pins of each logic gate when the failures are propagated to the output pins of the logic gates. Information on whether the fault has been propagated is obtained in advance, and this information is used to search the path by which the fault is propagated to the output pin, from the output side of the logic circuit to the input side, and the fault is detected. This is a method that directly determines the location where the search will occur in a single search. (M,
Abramoviei et al., “Cr1-t
ical Path Tracing: A
n Alternative to Fault
"Simulation", IEEE Design
and Te5t of Computers, V
ol, 1. No, 1. Feb. 1984. pp83-9
3. ).

[Problem to be solved by the invention]

By the way, the critical path tracing method does not perform processing related to simulation in the case that the set fault does not ultimately reach the output pin, so simulation processing is more efficient and faster than the other methods mentioned above. The method is such that it can be processed. However, on the other hand, the critical path tracing method
Assuming only the case where there is a single fault input through which a fault is propagated to the output in each logic gate, processing is performed to determine the path through which the fault propagates until it is output. That is, multiple fault inputs are not assumed in each logic gate, and the path through which the fault propagates until it is output is determined. Therefore, for example, as shown in FIG. 7, it may be impossible to detect a fault in a circuit section 70 (this circuit section is called a fan-out branch) where a signal is divided into multiple parts in a logic circuit. In addition, there was a problem that the processing procedure required for determining detection was long.

The present invention has been made to solve the above problems.

An object of the present invention is to provide a fault simulation method that requires short processing steps to determine whether to detect a fault and is capable of high-accuracy and high-speed processing.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a system that includes a logic connection description file and an input pattern file and performs normal logic simulation and failure simulation of logic circuits. One of multiple types of fault propagation types is set for each logic gate of the logic circuit from the combination of the fault signal and normal signal applied to the input pin of the logic gate when the fault signal is propagated to the output pin of the logic gate. A fault input processing means and multiple types of fault information flags indicating whether or not to propagate a fault to the output are specified, and the fault information flag on the output pin side is changed to the fault information flag on the input pin side in correspondence with each fault propagation type. Fault information set to output pins of logic circuits using a fault information propagation rule file with fault information propagation rules that define rules for converting to flags, and the fault propagation type and fault information propagation rules set for each logic gate. Converts the flag by propagating it from the output side to the input side, sets the fault information flag to the input/output pins of all logic gates in the logic circuit, and detects faults on the path where the fault is propagated to the output pin of the logic circuit. The method is characterized by comprising a processing means for determining a hot water place.

[Effect]

According to the means, a fault input processing means, a fault information propagation rule file, and a processing means for determining a fault detection hot spot are provided. Fault input processing means.

One of multiple fault propagation types based on the combination of the fault signal and normal signal applied to the input pin of the logic gate when the fault signal is propagated to the output pin of the logic gate using the result information of the normal logic simulation. is set for each logic gate in the logic circuit. The fault information propagation rule file defines multiple types of fault information flags that indicate whether or not to propagate a fault to the output. Corresponding to each fault propagation type, the fault information flag on the output pin side is changed to the fault information flag on the input pin side. Failure information propagation rules are provided that define the rules for converting into failure information flags. The processing means for determining the fault detection location propagates and converts the fault information flag set to the output pin of the logic circuit from the output side to the input side according to the fault propagation type and fault information propagation rule set for each logic gate. , a fault information flag is set to the input/output pins of all logic gates in the logic circuit, and the fault detection location on the path where the fault is propagated to the output pin of the logic circuit is determined.

In this way, the process of determining the fault detection location on the path where the fault is propagated to the output pin of the logic circuit is simply to determine the fault information flag from the output pin to the input pin according to the fault information propagation rule. , the processing procedure required for determining fault detection is shortened, and all locations where faults are detected can be quickly discovered for a given input button.

In addition, since the fault information propagation rules also specify the propagation rules for the fan-out branch, there is no case where fault detection is impossible in the fan-out branch, and no matter what logic circuit configuration, given input It is possible to quickly find the locations where all faults are detected.

〔Example〕

Hereinafter, one embodiment of the present invention will be specifically described using the drawings.

FIG. 1a and FIGS. 1 and 1b are block diagrams showing the flow of processing in a failure simulation system according to an embodiment of the present invention. In FIG. 1a, 1 is a logical connection description file, 2 is an input pattern file, 3 is a detection process for the output logic gate of a reconvergent circuit, 4 is a normal logic circuit simulation process, 5 is a fault input cover turn setting process, and 6 is a process for setting a fault input cover pattern. This is a process for detecting gates with no possibility of fault propagation. In FIG. 1b, 7 is a process for determining whether or not there is an unsearched output pin, 8 is a process for specifying an output pin to start propagating a failure information flag, and 9 is a failure information flag that has not reached an input pin. Judgment process of whether or not there is, 10
11 is a process for propagating a failure information flag from an output pin of a logic gate to an input pin; 11 is a process for propagating a failure information flag from an input pin of a logic gate to an output pin of a preceding logic gate connected to the input pin; 12 is a process for determining a fan-out branch failure; 13 is a process for detecting a 0/1 stuck-at fault at each point of the logic circuit; and 14 is a failure list file of the failure simulation results. Further, 15 is a failure information propagation rule file, 16 is a failure detection location determination process, and 17 is a failure input process.

The fault input processing 17 has the fault input cover turn setting processing 5 and the detection processing 6 of gates with no possibility of fault propagation as main components, and uses the result information of the normal logic simulation to determine the output pin of the logic gate. One of multiple fault propagation types is determined from the combination of the fault signal and normal signal applied to the input pin of the logic gate when the fault signal is propagated to the logic gate.
A process is performed to set one for each logic gate of the logic circuit.

Further, the failure detection location determination process 16 includes reference numbers 7 to 13.
Each process is the main component, and the fault propagation type set for each logic gate in the fault input processing 17 and the fault information propagation rule in the fault information propagation rule file 15 are set for the output pin of the logic circuit. Propagate and convert the fault information flag from the output side to the input side, set the fault information flag to the input/output pins of all logic gates in the logic circuit, and set the fault information flag to the input/output pins of all logic gates in the logic circuit. Performs processing to find the failure detection location.

Next, each process of the processing elements in the failure simulation system shown in FIGS. 1a and 1b will be explained.

Detection processing of output logic gate of reconvergent circuit 3
, a process of detecting an output logic gate 25 of a logic circuit including a reconvergence end circuit from the logic connection description data of the logic connection description file 1, for example, in the logic circuit 20 to be processed as shown in FIG. 2a. I do.

This process is executed by performing the following steps 1 to 6. The processing procedure is shown below.

Step 1: Set the FOB flag 23 on the logic gate 22 whose output pin is connected to the fan array 1-branch 21 (FIG. 2a).

Step 2: Select one of the logic gates 22 with the FOB flag set and change the FOB flag to the SEL flag 24 (FIG. 2b).

Step 3: Propagate the flag along possible paths from the output pin 26 of the logic gate with the SEL flag set to the external output pin 27, and set the R O flag on the input pin of each logic gate passed through (Second c. figure).

Step 4: Determine whether or not a logic gate with the FOB flag set exists. If so, return to step 2; if not, proceed to step 5.

Step 5: Detect the logic gate with the RO flag set to two or more input pins, register it as the output logic gate 25 of the reconvergent circuit, and proceed to the next step 6 (2nd d
figure).

Step 6: Clear the FOR flag of the logic gate targeted for processing, and check whether any other FOB flags remain. If the FOB flag remains, the process returns to step 2; if no FOB flag remains, the process ends.

In the normal logic circuit simulation process 4, logic simulation is performed on the configuration of the logic circuit based on the logic connection description data of the logic connection description file 1 according to the input cover pattern of the input pattern file 2, and the input/output of each logic gate is calculated. Determine the signal value on the pin.

In the fault input cover turn setting process 5, from the signal values on the input/output pins of each logic gate obtained in the normal logic circuit simulation process 4, a fault propagation type fault as shown in FIG. Performs processing to set input cover pattern.

When a fault signal is propagated to the output pin of the logic gate, from the combination of the fault signal and normal signal applied to the input pin of the logic gate, there are AND gates, NAND gates, OR gates, NOR gates, NOT gates, and two-man power X0R. (Exclusive OR) It is possible to classify the fault input cover patterns that each basic logic gate can take, and based on the fault propagation type, it can be classified into four types of logic gates as shown in Figure 3. . In Fig. 3, the type 1 and type 2 marks identify the input pins into which the fault signal necessary for propagating the fault signal to the output pin of this logic gate is used as the f flag. shall be. The meaning of each of the four fault propagation types is shown below.

Type 1: A fault is propagated to the output only when the fault is propagated to any one input pin for which the f flag is set. This type of logic gate is called a type 1 gate.

Type 2: A fault is propagated to the output only when a fault is simultaneously propagated to all two or more arbitrary input pins with the f flag set. Logic games 1 to 1 of this type are called type 2 gates.

Type 3: No matter what pattern the fault is input, the fault is always propagated to the output.

This type of logic gate is type 3 It is called a gate.

Type 4: A fault is propagated to the output only when a fault is input to one of the two human operators.

This type of logic gate is type 4 It is called a gate.

AND gate, NAND gate, OR gate.

In the process of setting a failure cut turn for each basic logic gate such as a NOR gate, a NoT gate, and a two-man XOR gate, and setting the fault propagation type for each logic gate, the next fault input cut (turn setting Follow the rules.

[Setting rules (i-1) In the case of an A N gate, when all inputs are 1, it is a type 3 gate. When the input is other than that, the f flag is set to the pin whose input is O.

(i~2) In the case of an OR gate, when all inputs are 0.

It will be a type 3 gate. When the input is other than that, the f flag is set to the pin whose input is 1.

(i-3) In the case of N OT gate, it is a type 1 gate.

(i-4) In the case of a two-man powered XOR gate, it shall be a type 4 gate.

Further, each logic gate in the logic circuit includes a logic gate in which there is no possibility of propagation of a fault signal due to the circuit configuration. Therefore, in a series of processes of setting the fault input cover turn and setting the fault propagation type of each logic gate, processing is performed to set logic gates with no possibility of fault signal propagation as type O gates. This process is performed by the detection process 6 of the logic game 1-, which has no possibility of fault propagation.

In the logic gate detection process 6 where there is no possibility of fault propagation,
By using the information on the fault propagation type obtained in the fault input cover turn processing 5 and the information obtained in the detection processing 3 of the output logic gate of the reconvergent circuit, each flag is propagated according to the propagation rule 1 shown below. By performing the processing to determine the state of each flag, processing is performed to detect a type O gate, which is a logic gate with no possibility of fault propagation. This process is executed by the following process procedure of step 7 and step 8.

Step 7: As shown in FIG. 4a, information on the R○ flag of each logic gate set in the output logic gate detection process 3 of the reconvergent circuit and information on the fault propagation type obtained in the fault input cover turn setting process 5. Accordingly, in a logic gate having a type 2 fault propagation type, a logic gate 41 that has at least one input pin for which the RO flag is not set among the input pins for which the f flag is set is defined as a type O gate. .

Step 8: As shown in Figure 4b, two types of flags (T flag, B flag) are propagated from the input terminal according to the following propagation rule 1, and when either flag is propagated to all output pins. After completing the propagation process, the logic gate 42 for which no f flag is set is newly set as a type 0 gate,
Finish the process.

[Propagation rule 1] (p-1) A T flag is output from the input terminal.

(p-2) In the fan-out branch, go to each branch destination B
Output flags.

(p-3) A T flag is output from the type 0 gate.

(P~4) When the T flag enters the input pin to which the f flag of the type 1 gate is set, the T flag is output, and when the B flag enters, the B flag is output.

(p-5) When the T flag enters at least one of the input pins of the type 2 gate to which the f flag is set, all the f flags of that gate are erased and the T flag is output. Otherwise, the B flag is output.

(p-6) When the B flag is input to at least one of the input pins of the type 3 gate, the B flag is output. Otherwise, the T flag is output.

(p-7) When the B flag is input to at least one of the input pins of the type 4 gate, the B flag is output. Otherwise, the T flag is output.

Through such processing (fault input processing 17), processing for setting one of the plurality of fault propagation types for each logic gate of the logic circuit has been performed. Next, fault detection location determination processing 16 (fault detection location determination processing 16) Figure 1b).

First, in the failure detection location determination process 16, a determination process 7 is performed to determine whether there is an unsearched output pin.

If there is an unsearched output pin in this determination process, a process 8 for specifying a start output pin for failure information flag propagation is performed. In this failure information flag propagation start output pin designation process 8, an output pin to start failure information flag propagation is arbitrarily designated. Next, a determination process 9 is performed to determine whether there is a failure information flag that has not reached the input pin, and if there is no failure information flag that has not reached the input pin, it is determined whether or not there is an unsearched output pin. The process returns to determination process 7. Furthermore, if there is a failure information flag that has not reached the input pin, then a process 10 for propagating the failure information flag from the output pin to the input pin of the logic gate is performed.

In the process 10 of propagating the fault information flag from the output pin to the input pin of the logic gate, the following six types of fault information flags and the fault Processing is performed to propagate the failure information flag from the output pin determined in the start output pin designation process 8 from the output side to the input side of each logic gate according to propagation rule 2 that defines the propagation rule for the information flag. At this time, the D flag is first set on the output pin. Note that when the failure information flag is propagated from the output pin to all input pins for this output pin, the next output pin is specified by the start output pin specification process 8, and the failure information flag for the next output pin is transmitted. Perform propagation processing. The six types of failure information flags are flags indicating whether or not to propagate a failure to the output, and are as shown below. A priority is set for each flag as follows.

X flag: Set priority 1.

D flag: Set priority 2.

M flag: Set priority 3.

R flag: Set priority 4.

E flag: Set priority 4.

P flag: Set priority 5.

A propagation rule 2 that defines the propagation rule for this failure information flag is provided in the failure information propagation rule file 15.

[Propagation rule 2] (g-1) When the D flag is input to the output pin of a type 1 gate, the D flag is output from the input pin where the f flag is set, and the reconvergent circuit is output from the other input pins. The logic gate outputs the E flag, and the other logic gates output the P flag.

(g-2) When the D flag is input to the output pin of the type 2 gate, the R flag is output from the input pin where the f flag is set, and the E flag is output from the other input pins.

(g-3) When the D flag is input to the output pin of a type 3 gate, the D flag is output from all input pins.

(g-4) When the D flag is input to the output pin of a type 4 gate, the output logic gate of the reconvergent circuit outputs the X flag from all input pins, and the other logic gate outputs the D flag from all input pins. Output flags.

(g-5) When the R flag is input to the output pin of the type 1 gate, the R flag is output from the input pin where the f flag is set, and from the other input pins, the logic gate of the output of the reconvergent circuit is output. outputs the E flag, and other logic gates output the P flag.

(g-6) When the R flag is input to the output pin of the type 2 gate, the R flag is output from the input pin where the f flag is set, and the E flag is output from the other input pins.

(g-7) When the R flag is input to the output pin of a type 3 gate, the R flag is output from all input pins.

(g-8) When the R flag is input to the output pin of a type 4 gate, the R flag is output from all input pins.

(g-9) When the E flag is input to the output pin of the type 1 gate, the E flag is output from the input pin to which the f flag is set, and the P flag is output from the other input pins.

(g-10) When the E flag is input to the output pin of the type 2 gate, the E flag is output from the input pin to which the f flag is set, and the P flag is output from the other input pins.

(g-11) When the E flag is input to the output pin of a type 3 gate, the E flag is output from all input pins.

(g-12) When the E flag is input to the output pin of a type 4 gate, the E flag is output from all input pins.

(g-13) When the M flag is input to the output pin of the type 1 gate, the M flag is output from the input pin where the f flag is set, and from the other input pins, the logic gate of the output of the reconvergent circuit outputs the E flag, and other logic gates output the P flag.

(g-14) When the M flag is input to the output pin of the type 2 gate, the M flag is output from the input pin where the f flag is set, and the E flag is output from the other input pins.

(g-15) When the M flag is input to the output pin of a type 3 gate, the M flag is output from all input pins.

(g-16) When the M flag is input to the output pin of a type 4 gate, the M flag is output from all input pins.

(g-17) When a P flag is input to the output pin of a type 1 gate, the P flag is output from all input pins.

(g-18) When a P flag is input to the output pin of a type 2 gate, the P flag is output from all input pins.

(g-19) When a P flag is input to the output pin of a type 3 gate, the P flag is output from all input pins.

(g-20) When a P flag is input to the output pin of a type 4 gate, the P flag is output from all input pins.

(g-21) When the X flag is input to the output pin of the type 1 gate, the X flag is output from the input pin where the f flag is set, and from the other input pins, the For other logic gates, the E flag is output, and for other logic gates, the P flag is output.

(g-22) When the X flag is input to the output pin of the type 2 game 1-, the X flag is output from the input pin where the f flag is set, and the E flag is output from the other input pins.

(g-23) When the X flag is input to the output pin of the type 3 gate, the X flag is output from all input pins.

(g-24) When the X flag is input to the output pin of a type 4 gate, the X flag is output from all input pins.

(g-25) Type 1 gates output P flags from all input pins, regardless of the type of flags input to the output pins.

In this way, the failure information flag is propagated using the propagation rules,
Each failure information flag is set to the input/output pin of each logic gate. In the subsequent processing, as a result, a fault is detected on the path along which the X flag and D flag obtained here are propagated, and the fault simulation cannot be performed.

Next, a process 11 of propagating the failure information flag from the input pin of the logic gate to the output pin of the logic gate connected to the input pin is performed. In this propagation process 11, if the connection from the input pin to the output pin of the previous stage logic gate is a fan-out branch, the propagation rule for the failure information flag in the fan-out branch is the following propagation rule 3.
Determined according to. In other cases, the failure information flag propagation process is performed assuming that the flag information of the input pin is transmitted to the output pin as is. Note that when failure detection is performed according to the fan-out branch propagation rule shown in propagation rule 3, a failure information flag is determined in the next fan-out branch failure determination process 12.

[Propagation Rule 3] (s-0) If the flags propagated to each fan-out branch are one R flag and one or more E flags,
The M flag is output to the fan-out branch.

(s-1) If the flags propagated to each fan-out branch are as follows, it is determined whether a failure of the fan-out branch is detected.

The determination is made in the fan error 1 to branch failure determination processing 12.

(s-1a) A case where multiple X flags exist and no D flag exists.

(s-1b) When there are multiple M flags and no D flag.

(s-1c) A case where there are multiple R flags and no D flag.

(s-1d) When a set of X flag and E flag or a set of X flag and M flag exists.

(s-1e) When a set of D flag and E flag or a set of D flag and M flag exists.

(s-2) If a failure is detected as a result of the judgment, (
Except for cases s-1b) and (s-1e),
Among the failure detection flags propagated to each fan-out branch, the flag with a higher priority is output.

In the case of (s-1b), the D flag is output. (s-1e
), the X flag is output.

(s-3) If no failure is detected as a result of the determination.

Among the failure non-detection flags propagated to each fan-out branch, the flag with the highest priority is output.

(s-4) In cases other than (s-i), the flag with the highest priority among the failure information flags propagated to each fan-out branch is output. However, (s-0
), when the R flag and the E flag exist as the highest flags, the M flag is output.

Next, a fan-out branch failure determination process 12 is performed.

This failure determination process 12 is performed as failure information flag propagation process 1.
1 for fan-out branches that could not be determined in 1.
A failure information flag is determined by following steps 9 to 12 as shown below.

Step 9: Set a failure in the fan-out branch to be determined.

Step 10 Propagate the fault from the fault set point set in step 9 to the input of the same network.

Step 11: Determine whether or not a fault has been detected according to the following fault detection rule. If no determination is made according to this failure detection rule, the process proceeds to the next step 12.

Step 12: Propagate the fault to the first stage output side network and return to step 10.

[Fault Detection Flag (j-1) If the fault is propagating only to the route marked with the D flag, the fault propagates to the output and the process ends.

(j-2) In the path from the fan-out branch to the output pin where it is determined whether or not a failure has been detected.

If the X flag does not exist, the fault will propagate on all routes marked with the R flag, and if the fault does not propagate to other routes, the fault will propagate to the output and the process will end.

(j-3) The fault reaches the output pin, and in cases other than (j-1) and (j-2), the fault does not propagate to the output.

After performing such processing, specifying one output pin (start output pin specification process 8), and propagating the failure information flag from the output pin to all input pins, specify the next output pin, A process is performed to propagate the failure information flag from the output pin to all input pins, and when the process for all output pins is completed, this is judged in judgment process 7 and 0/
1. A stuck-at fault detection process 13 is performed. That is, a failure information flag is set for the input/output pin of each logic gate of the logic circuit, and the next O/1 stuck-at fault detection process 13 is performed.

In the 0/1 stuck-at fault detection process 13, the presence or absence of a 0/1 stuck-at fault at each point of a given logic circuit is determined as follows. In other words, the normal simulation value is II OI for the fault on the route with the
The fault simulation is performed assuming that a stuck-at-1 fault is detected at the location T, and a stuck-at-O fault is detected at the location where the normal simulation value is PA1'''.

The results of the fault simulation obtained in this way are output to the fault list file 14.

Due to this, the fault list is 0/1 at each point of a given logic circuit for a given input cover turn.
Information on whether a stuck-at fault has been detected can be obtained.

Next, a specific example of failure simulation processing using such a series of processing will be schematically explained.

FIGS. 5a and 5b are diagrams illustrating a specific example of failure simulation processing. As shown in FIG. 5a, each logic gate 51, 52, 5 forming a logic circuit
3, a logic value is set to the input/output pin of each logic gate according to the data of the given input pattern. next,
Using this logical value data, an f flag (mark) is set for each input pin according to the failure cover turn setting rule.

Setting the f flag sets the fault propagation type of each logic gate. In this example, all gates are type 1 gates. Next, according to failure information flag propagation processing 10, the D flag is propagated from the output terminal side according to propagation rule 2, and each flag is propagated to each input/output pin. That is, as shown by the arrow in FIG. 5a, in the logic gate 53, according to rule (g-1) of propagation rule 2,
The logic gate 52 follows the rule of propagation rule 2 (g(7)), and the logic gate 51 also follows the rule of propagation rule 2 (g(7)).
g-1), each failure information flag (D flag, P
flag). As a result, each fault information flag is set to the input/output pin of each logic gate, and the path through which the fault is propagated is determined. In this case, assuming that the fault propagates only to the route with the D flag on it, as shown in Figure 5b, the normal simulation value is at the location of LL O11 for the fault on the route on which the D flag is on. is 1
A fault simulation is performed assuming that a stuck-at fault 5-a-1 is detected and an O stuck-at fault 5-a-0 is detected at a location where the normal simulation value is "1".

FIGS. 6a, 6b, and 6c are diagrams illustrating other specific examples of failure simulation processing. In the same manner as in the above-mentioned example, each rule (g
-1), (g-3), and (g-9), the failure information flags (D flag, E flag, P flag) are propagated in each logic gate and sent to the input/output pins of each logic gate. Set the failure information flag. For this example logic circuit, fanout branches 65, 66, 67
So this fanout branch 65.66,6
The propagation process of the failure information flag for 7 is processed according to each of the propagation rules 3. As a result, a failure information flag is set on the input/output pin of each logic gate as shown in FIG. 6a. As shown in Fig. 6b, the fault (x mark) is propagated only to the path on which the D flag is placed, so a fault in the fan-out branch is also detected, and as shown in Fig. 6c, the fault (x mark) is propagated only to the path on which the D flag is placed. 1 stuck-at fault 5-a occurs at a location where the normal simulation value is 0'' for a fault on the route.
-1, and a stuck-at-O fault 5-a-0 is detected at a location where the normal simulation value is 1111+, and a fault simulation is executed.

The present invention has been specifically explained above based on examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

〔Effect of the invention〕

As described in Section 2, according to the present invention, a given logic circuit can accurately provide information on whether or not an O/1 stuck-at fault has been detected at each point of the given logic circuit in response to an input button. Moreover, by processing with simple rules based on local information in the logic circuit, fault simulation can be processed at high speed.

[Brief Description of the Drawings] Figures 1a and 1b are block diagrams showing the flow of processing in a failure simulation system according to an embodiment of the present invention; Figures 2a, 2b, 2c, and 2d; 3 is a diagram illustrating the detection process of the output logic gate of a reconvergent circuit. FIG. 3 is a diagram showing symbols of four types of fault propagation of logic gates. FIGS. Figures 5a and 5 illustrating the process of detecting unlikely logic gates
Figure b is a diagram for explaining a specific example of failure simulation processing. Figures 6a, 6b, and 6c are diagrams for explaining other specific examples of failure simulation processing. Figure 7 is a diagram for explaining a specific example of failure simulation processing. FIG. 2 is a diagram illustrating an example of a circuit portion having a fan-out branch of FIG. In the figure, 1...Logical connection description file, 2...Input pattern file, 14...Fault list file, 15
. . . Fault information propagation rule file, 16. Fault detection location determination processing, 17. Fault input processing.

Claims (1)

[Claims] (1) In a system that includes a logic connection description file and an input pattern file and performs normal logic simulation and fault simulation of a logic circuit, a fault signal is propagated to the output pin of a logic gate using the result information of the normal logic simulation. a fault input processing means for setting one of a plurality of types of fault propagation types to each logic gate of a logic circuit from a combination of a fault signal and a normal signal applied to an input pin of the logic gate when A fault that defines multiple types of fault information flags that indicate whether or not the fault propagation occurs, and rules for converting the fault information flag on the output pin side to the fault information flag on the input pin side corresponding to each fault propagation type. Using the fault information propagation rule file with information propagation rules, the fault propagation type and fault information propagation rules set for each logic gate, the fault information flag set on the output pin of the logic circuit is propagated from the output side to the input side. processing means for determining the fault detection location on a path through which the fault is propagated to the output pin of the logic circuit; A failure simulation method featuring: