JPH0777562A - Generation method for short circuit diagnostic data - Google Patents

Abstract

PURPOSE:To generate diagnostic data for short circuit with a small program developing scale using a conventional diagnostic data generation program for a stack-at fault model. CONSTITUTION:A short circuit model circuit 8 is inserted in order to make diagnosis of short circuit between an LSI incorporating a boundary scan function and a cluster 4 (e.g. between S1-S2) possible. The model circuit 8 substitute the short circuit fault of input signals S1, S2 to the cluster 4 for a stack-at fault of signal in the model circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of diagnosing a logic circuit such as an LSI or a mounting board, and more particularly to a method of diagnosing short circuit between signal nets.

[0002]

2. Description of the Related Art Conventionally, short-circuit fault detection between signal nets is diagnosed by (1) a case where there is no logic circuit between the source and the sink and (2) there is a logic circuit between the source and the sink. Technology has been developed.

As the prior art of the above (1), there is IEEE
In 1149.1, along with the standardization of the boundary scan (hereinafter referred to as BS) architecture, various researches and developments have been made on the short failure diagnosis pattern of the signal net between BS cells. In the signal wiring test between the BS cells, the signal value on the source side is propagated to the sink side as it is, so that the diagnostic data can be relatively easily generated as a standard test pattern.

Therefore, in many papers (for example, documents (a) and (b) below), there is a question of how to efficiently perform an open failure or a short failure of a wiring with a small number of patterns. Arguing from a perspective.

(A) A. Hassan, J .; Rajsk
i, and V. K. Arawal'Testing
and Diagnostic of of Interco
nects Using BS Architect
ure'IEEE ITC Proceedings,
IEEE Computer Society Pre
ss, Los Alamitos, Calif. 198
8, pp126-137 (b) A. Hassan, J .; Rajski, V .; K.
Agrawal, and B. N. Dostie'Tes
toning of Glue Logic Interc
connectingsus BS Architect
ure'IEEE ITC Proceedings,
IEEE Computer Society Pre
ss, Los Alamitos, Calif. 198
9, pp700-711 However, the above-mentioned paper does not describe the method of generating the short-circuit failure test pattern in the case of the logic circuit of the non-BS component between the BS cells of (2) described above.

Regarding the short-circuit fault (2) described above, a method of obtaining a test pattern of the short-circuit fault by performing an operation corresponding to the short-circuit fault at the short-circuited portion is described in "Fault diagnosis of logic circuit (above ) "
(Kishita, Fujiwara: Engineering Book Co., Ltd., 1983).

[0007]

By the way, as a typical algorithm for automatically generating the stuck-at fault input test pattern, there is the D algorithm (for this, JP Roth: "Diagnostics").
of Automata Failures: Acal
iculus and a method, "IBM
Journalof Research and De
velopment, vol. 10, pp. 278-2
91, Jul 1966).

In this test generation algorithm, it is necessary to consider a logical operation expression for each operation element, and in order to apply the operation of (2) described above to this algorithm, a logical operation expression of a short fault can be handled. Large-scale changes to conventional programs are required. Moreover, in order to perform a failure simulation that automatically calculates an expected value of each output pin for an input data pattern and a failure dictionary for failure analysis for a short failure, it is necessary to independently perform an operation different from the test generation algorithm. As a result, there is a problem that a larger scale change is required.

An object of the present invention is to provide a short fault diagnostic data generation method for generating short fault diagnostic data with a small program development scale by using a conventional diagnostic data generation program for a stuck-at fault model.

[0010]

In order to achieve the above object, in the present invention, in a method for generating diagnostic data for a short circuit fault between signal nets, a signal group between a source and a sink assuming a short circuit fault is It is characterized in that means for converting a short-circuit fault into a stuck-at fault is provided, and diagnostic data for a short-circuit fault between signal groups is generated using this means.

[0011]

[Operation] LSI incorporating a boundary scan function
And a short-circuit fault model circuit is provided in order to enable diagnosis of short-circuit faults between logic circuits such as SSI and MSI. This short-circuit fault model circuit replaces a short-circuit fault between input signals of a logic circuit with a stuck-at fault.
Since the short-circuit fault can be modeled as a stuck-at fault, the short-circuit fault diagnosis data can be generated by the existing diagnostic data generation program.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be specifically described below with reference to the drawings. FIG. 2 shows a BS circuit built-in mounting substrate to which the present invention is applied. In FIG. 2, LSIs 1 and 2 have a BS (Boundary Scan) function defined in IEEE 1149.1 incorporated therein. That is,
BS cells 3-1 (C1) to 3-13 (C13) are incorporated between the LSI input / output pins and the LSI internal circuit, and the input / output pins of the LSI are connected to terminals (TDI,
It is controlled and observable from (TDO).

The circuit 4 has an SSI (s) which does not have a BS function.
mall scale integrated cir
CUTE) and MSI (medium scale in)
It is a logic circuit composed of integrated circuits, etc., and is called a cluster. The input signal 5 (S1 to S3) of the cluster 4 is connected to the input / output pin of the BS embedded LSI 1, and the output signal 6 (S4, S5) is B.
It is connected to the input / output pins of the S-embedded LSI 2. Further, between the input / output pins of the LSIs 1 and 2, the direct connection signal 7 (BS1, BS
2) is also provided.

Direct connection signal 7 between the BS built-in LSIs 1 and 2
The wiring test of (BS1, BS2) can be performed by the standard test pattern described in the above-mentioned papers (a) and (b), and the short circuit failure between BS1 and BS2 can be diagnosed.

Signals S1 to I / O signals of the cluster 4
Among the wiring faults between S5, the wiring open fault can be detected as a stuck-at fault of SSI / MSI in the cluster.
The short circuit defect may not be detected as a stuck-at fault, and may not be detected even by the short circuit fault detection pattern of the signal directly connected between BS cells of (a) described in the prior art.

Therefore, the present invention enables diagnosis of a short-circuit failure (for example, between S1 and S2) between the LSI and the cluster. FIG. 1 shows the configuration of an embodiment of the present invention in which a short circuit model circuit is inserted.

The short-circuit failure model circuit 8 includes a cluster 4
Is a circuit for modeling a test pattern for detecting a short-circuit fault of the input signals S1 and S2 of FIG. 1 by a conventional stuck-at fault, that is, by providing such a model circuit, the short-circuit fault can be reduced. It is replaced with the stuck-at fault of the signal inside.

FIG. 3 shows a specific structure of the short-circuit failure model circuit 8. It should be noted that this configuration has CMOS, TTL
This is the case of the system. In FIG. 3, the signal S1 and the signal SIG1 of the short circuit model circuit 8 are connected, the signal S2 and the signal SIG2 of the model circuit 8 are connected, the input signal S1 ′ of the cluster 4 and the signal OS1 of the model circuit 8 are connected, The input signal S2 ′ of the cluster 4 and the signal OS2 of the model circuit 8 are connected. In the mounting board shown in FIG. 3, this model circuit is inserted between the LSI output pin on the source side of the signals S1 and S2 and the input pin of the cluster 4 on the sink side. After the insertion, different names S1 'and S2' are given to the sync side signal.

The signal LOW of the model circuit 8 is fixed to "0" under normal conditions. Then, at the time of short circuit, it is fixed to "1", and the short circuit failure between SIG1 and SIG2 is equivalent to the "1" stuck-at failure of the output pin 2 (hereinafter referred to as g2-2 pin) of the gate g2. That is, as is clear from the truth table at the time of short circuit, SHORT = 1
Then, when SIG1 = SIG2 = 1, OS1 = OS2 = 1
Therefore, when SIG1 = SIG2 = 0, OS1 = OS2
= 0, and a short circuit failure is modeled.

In the normal state, SHORT = 0, S
In accordance with the input signal level of IG1, it is output to OS1 through gates g6 and g8, and in accordance with the input signal level of SIG2, it is output to OS2 through gates g7 and g9.
The model circuit 8 is a circuit that simply passes the signals S1 and S2.

FIG. 4 is a flow chart of cluster diagnostic data generation, in which short-circuit fault diagnostic data is generated as a part of the cluster diagnostic data. First, in the processing of step 21, diagnostic data for the stuck-at fault of the cluster circuit is generated, and in the processing of steps 22 and 23, among the input / output pins of the cluster 4, between the adjacent pins (C7 and C6, C6 in FIG. 1). And C5) short-circuit failure diagnostic data are generated, and in the processing of step 24, steps 21-23 are performed.
The diagnostic data generated in step 1 are integrated and output as diagnostic data for one type of LSI.

When the real logic and the stuck-at fault of the short-circuit fault model circuit 8 are generated at the same time, since the fault data is also assumed and the diagnostic data is generated at the portion other than the g2-2 pin of the short-circuit fault model circuit 8, the degeneration of the real logic is made. Fault and short fault diagnostic data generation is performed separately.

FIG. 5 is a flow chart for generating diagnostic data for short-circuit failure, and shows the details of the processing in step 23 of FIG. In the process of step 31, a short-circuit fault model circuit 8 for a signal assuming a short-circuit fault is generated (see FIG.
In the process of step 32, a test pattern of the "1" stuck-at fault of the g2-2 pin is generated and a fault simulation is performed. As the test pattern of this "1" stuck-at fault, for example, in the truth table of FIG.
IG1 = 0, SIG2 = 1 pattern, SIG1 = 1,
A pattern of SIG2 = 0 is generated and simulated. OS1, OS for this test pattern
Since both 2 output 0, a failure is detected. In the process of step 33, it is determined whether or not the test generation is successful (that is, it is determined whether or not a failure is detected by the input test pattern).

If successful, the process of step 34
The test pattern is registered, registered in the fault dictionary in the process of step 35, and registered as a detectable fault in the process of step 36. If it is not successful, it is registered as an undetectable failure in the process of step 37, and it is determined in the process of step 38 whether or not the trial has been completed for the test generation of all target signals. Returning to the processing, the diagnostic data of the next signal (that is, the next short circuit failure) is generated. When finished, step 39
By the process of, the short-circuit failure correspondence table is output. here,
Output a correspondence table between the g2-2 pin and a signal pair assuming a short circuit failure. As described above, in this embodiment, the diagnostic data is generated for each short-circuit fault.

FIG. 6 is a diagram showing the relationship between the failure dictionary and the short-circuit failure correspondence table. This table is data used for pointing out the position of the failure detected during diagnosis and is stored as diagnostic data. It

The fault dictionary is a dictionary for short faults (see FIG. 5).
Output) and a stuck-at fault dictionary (generated in step 21 of FIG. 4), and output pins (for example, S4 and S5 in FIG. 1) that fail the test for each test pattern number.
The failure candidate point (for example, g2-2) is stored. The short-circuit fault correspondence table stores a fault position (fault candidate point g2-2 / 1) of the short-circuit fault model circuit and a set of signals (for example, S1-S2) assuming a short fault. The failure candidate point is represented by gate name-pin number / fault value (1 or 0).

FIG. 7 is a flow chart of failure analysis. When performing the failure analysis, the failure dictionary shown in FIG. 6 is used. Since the first half of the test pattern of the fault dictionary in FIG. 6 is the test pattern for short-circuit fault and the second half is the test pattern for stuck-at fault, if the first number of the stuck-at fault test pattern is held in the diagnostic data. , Step 4
In the processing of No. 1, it is possible to determine from the failed test pattern number whether it is a short failure test pattern or a stuck-at failure test pattern. If it is the stuck-at fault test pattern number, then in step 44, the fault analysis of the normal stuck-at fault test is performed.

Some of the short-circuit faults fail with the normal stuck-at fault test pattern, but if they fail with the short-circuit fault test pattern, they are preferentially treated as short-circuit faults in the processing of step 42. In the case of a short-circuit fault, the short-circuit fault correspondence table of FIG. 6 is searched using the fault candidate points as a key, and the signal pairs that may have been short-circuited are extracted in the processing of step 43. Even if the short-circuit fault correspondence table is searched, if there is no fault candidate point, the fault position is output as unknown in the process of step 45.

In the present embodiment, a test pattern is generated for each set of signal pairs for a short-circuit fault, so that one set of short-circuit fault signal pairs corresponds to one failed test pattern.

As described above, in the present embodiment, the conventional stuck-at fault test generation program can be diverted to generate diagnostic data for short-circuit fault between adjacent pins of a cluster.

FIG. 8 is a flowchart of the tester for executing the diagnostic data for short circuit failure. That is, the diagnosis data for short circuit failure generated by the present invention (FIG. 6)
3 is a processing flowchart of a tester that executes the above process and inspects the mounting board (logic circuit) shown in FIG. 2.

In the process of step 51, the logic circuit is powered on, and in the process of step 52, the test pattern (FIG. 6) is added to the TDI of the logic circuit one by one. In the process shown in step 53, the output value observed by TDO and the expected value in the diagnostic data are compared. If they match, it is checked whether or not all the test patterns have been executed in the process of step 54. If they have not been executed, the process returns to step 52 to execute the next test pattern. When all the test patterns have been executed, the power is cut off in the process of step 56, and the fact that the inspection has passed is output in the process of step 57.

If they do not match, the number of the executed test pattern is compared with the number of the first stuck-at fault test pattern held in the diagnostic data to determine whether or not it is the short-circuit fault test pattern. . When the number of the executed test pattern is smaller than the number of the first stuck-at fault test pattern, the executed test pattern is the short-circuit fault test pattern. Therefore, in the process of step 56, the wiring pattern on the mounting substrate Assuming a short,
Immediately turn off the power to prevent damage to the parts due to short circuits. Then, in the process of step 58, the fact that the failure has occurred and the test pattern number are output. In this embodiment, the number of the first stuck-at fault test pattern is held in the diagnostic data, but it may be supplied to the tester as information for controlling the tester independently of the diagnostic data. .

In the above-described embodiment, the short-circuit fault diagnostic data is generated for each set of signal pairs, but it may be changed so as to generate the short-circuit fault diagnostic data for each of a plurality of sets of signal pairs. You can That is, FIG. 9 shows a short-circuit fault diagnostic data batch generation circuit for a plurality of pairs of signals. A signal LOW of each short-circuit failure model circuit 8 is given a number (LOWn, n = 1, 2, 3, ...) To distinguish each signal LOW, and other signal names in each short-circuit failure model circuit 8 and It is necessary to add information to distinguish the gates.

In the circuit shown in FIG. 9, failure assumptions are simultaneously made to the g2-2 pins of each short-circuit failure model circuit 8 and diagnostic data is simultaneously made to reduce the overhead from test pattern generation to failure simulation. can do. However, it is premised that the short-circuit failure occurs in only one signal pair for one circuit. The assumed failure position may be the input pin 1 of the gate g2.

In the above embodiment, the short-circuit fault between two signals is assumed, but it can be changed to a short-circuit fault between three signals. Figure 10
A short circuit model circuit between three signals is shown. With this configuration, it is possible to generate diagnostic data as in the above-described embodiment. Further, FIG. 10 can be expanded to configure a short-circuit failure model circuit between n signals.

Further, in the above embodiment, the short circuit fault of the input signal has been illustrated, but for the short circuit fault between the output signals, the diagnostic data can be generated by using the short circuit fault model circuit of FIG.

Further, in the above embodiment, CMOS / TTL is used.
Although it is premised that the system circuit is short-circuited, the invention is not limited to this, and as shown in FIG. 11, the gate g of FIG.
By changing 3 (AND gate) to OR gate, an ECL system short-circuit failure model circuit can be constructed.

Further, a direct connection signal (BS
1, BS2) and the cluster 4 input / output signal short-circuit fault diagnostic data is generated, that is, for example, B
In order to generate the diagnosis data of the short circuit fault of S1 and S2, the short circuit fault diagnosis data of FIG. 12 including the direct connection signal between the BS cells as the input / output signal may be generated.

As described above, a feedback loop is formed due to a short-circuit failure between input / output pins, but since the circuit of FIG. 3 is inserted between the sink and source of the input / output signal, the feedback loop itself is modeled. Is possible. However, the test data generation program needs to be able to generate test data for the asynchronous sequential circuit.

Further, the present invention can be applied not only to a short circuit failure between cluster input / output proximity pins of the mounting board, but also to a short circuit failure of a signal in an arbitrary logic circuit.
The combination of short-circuit faults between all signals is N! / 2! (N-2)! Since there are various combinations, it is possible to extract only the signal pairs whose wiring paths are close to each other and generate the short-circuit failure diagnostic data.

Further, in the present embodiment, since the short-circuit fault model circuit is added to the logical expression data itself, when the diagnostic data for a plurality of short-circuit faults are simultaneously generated,
The number of gates in the model circuit increases in proportion to the number of short circuits. In order to deal with this, a method of reducing the data amount of the logical expression data by defining a multifunctional cell having a function equivalent to that of the short-circuit model circuit of FIG. 3 as a basic cell of the logical expression data may be adopted. . Also, if the short-circuit fault model circuit is expressed only in the table in the test data generation program, it is possible to model the short-circuit fault without increasing the data amount itself of the logical expression data.

[0043]

As described above, according to the present invention, since the short-circuit fault is modeled as the stuck-at fault, the short-circuit fault diagnostic data can be generated by the existing diagnostic data generation program, and the tester can be used. This makes it possible to diagnose a short circuit failure.

[Brief description of drawings]

FIG. 1 shows a configuration of an embodiment of the present invention in which a short circuit model circuit is inserted.

FIG. 2 shows a BS circuit built-in mounting substrate to which the present invention is applied.

FIG. 3 shows a specific configuration of a short-circuit failure model circuit.

FIG. 4 is a flowchart of cluster diagnostic data generation.

FIG. 5 is a flowchart for generating diagnostic data for short-circuit failure.

FIG. 6 is a diagram showing a relationship between a failure dictionary and a short-circuit failure correspondence table.

FIG. 7 is a flowchart of failure analysis.

FIG. 8 is a flowchart of a tester that executes short failure diagnostic data.

FIG. 9 shows a short-circuit fault diagnostic data batch generation circuit for a plurality of pairs of signals.

FIG. 10 shows a short circuit fault model circuit between three signals.

FIG. 11 shows an ECL system short-circuit failure model circuit.

FIG. 12 shows a cluster including a BS inter-cell net.

[Explanation of symbols]

 1, 2 LSI 3-1 to 3-13 BS cell 4 cluster 5 cluster input signal 6 cluster output signal 7 BS cell direct connection signal 8 short-circuit failure model circuit

Claims (1)

[Claims] 1. A method of generating diagnostic data for a short-circuit fault between signal nets, wherein means for converting the short-circuit fault into a stuck-at fault is provided between the source and sink of a signal group assuming a short-circuit fault, and the means is used. A method of generating short-circuit fault diagnostic data, characterized by generating short-circuit fault diagnostic data between signal groups.