CN105787213B - A kind of restorative procedure that the retention time violates - Google Patents
A kind of restorative procedure that the retention time violates Download PDFInfo
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Abstract
A kind of restorative procedure that the retention time violates, obtains path starting point, terminal and the violation value violated there are the retention time first from the result of static timing analysis；Then the terminal for selecting the retention time to violate path is repaired be inserted into a buffer cell or delay unit in ingress to be inserted every time as the ingress to be inserted for repairing unit, to reduce the influence be inserted into and repair unit to other path timing；Thirdly, in the physical location that the near nodal searching unit that unit is repaired in insertion is put, by the position of original unit in mobile design with release repair unit needed for space, and set objective function and make the total cost of mobile unit minimum, it is smaller to intrinsic disturbance；Fourth, generating the corresponding engineering changing order repaired logic, put unit, position of mobile unit；Finally, carrying out rewiring to the connection relationship for modifying logic, parasitic parameter is then extracted, it is complete to carry out static timing analysis confirmation retention time reparation.
Description
Technical field
The present invention relates to a kind of for repairing the method that the retention time violates in high density physical Design.
Background technique
With extensive and super large-scale integration continuous utilization, process constantly reduces, and prevailing technology is
Reached 40nm, and constantly to the more advanced technological development of smaller szie.Currently, the state-of-the-art technique studied in the world
Technique having a size of Intel Company has striden into more than ten nanometers of magnitude.Smaller and smaller process replaces prior art
Speed is accelerated constantly, and this requires the engineers of physical Design constantly to shorten the production cycle, could be in fierceness
It occupies a tiny space in competition, relatively late in particular for the starting of China's integrated circuit industry, the status of technology weakness, country
It is proposed the relevant policies for vigorously supporting integrated circuit industry.But the continuous diminution of transistor feature size and chip integration
Continuous improvement so that the design of integrated circuit is faced unprecedented challenge, either relatively large-sized integrated electricity in front
Road design in or in the design of deep submicron integrated circuit, sequence problem is always problem of greatest concern, either from
The performance or stability of design chips consider, require that designed chip has a preferable timing closure effect,
Subsequent authentication can be passed through and produce the product of high-performance high reliability.
During entire physical Design, the reparation of retention time is a highly important link during timing is repaired,
Because settling time can solve in the case where that can not repair completely by frequency reducing, the working frequency of chip, chip are reduced
It still can satisfy requirement functionally；But can not be repaired completely if the retention time violates, it will result directly in chip function
Mistake on energy, entire chip just can not work normally, so repairing the important link that the retention time is timing reparation.It is repairing
The key point that foundation/retention time violates is that new retention time violation will not be generated while violating reparation settling time,
New settling time violation will not be generated while retention time violation repairing, this requires repairing foundation/retention time
To consider whether corresponding surplus can satisfy the corresponding requirements of timing reparation when violation.Especially present multi-mode multiterminal
During the Time-Series analysis and its reparation at angle (Multi-mode multi-corner, MMMC), it should comprehensively consider all fields
Timing condition (scenario) of interest under scape, situation will become more complicated, grind to the restorative procedure of its timing
Study carefully, a kind of method for finding out reparation retention time violation rapidly and efficiently seems with independent significance.
Higher for cell density in design, timing repairs difficult situation, at present temporarily without preferable solution, only
It can be the cell density reduced during design by the method for density domination in design.Work is repaired in a large amount of timing
In tool, the timing reparation in high density designs is also not highly desirable, such as used timing fix tool ICE at this stage, is
A relatively good efficient timing fix tool is mainly disobeyed by being inserted into buffer cell in the strength of data road to repair the retention time
Instead, without any changes to existing unit before being repaired in design.In highdensity design, tool is most wantonly searched for setting
If can not find enough space insertion buffer cells within the scope of rope, just having some paths can not be repaired.As shown in Figure 1, figure
Middle display unit outstanding is terminal (endpoint) unit in the path for having the retention time to violate, and the part of position is close
Spend it is higher, around have some spaces but be not enough to be inserted into a smallest buffer cell to repair the retention time and violate, institute
It can not be repaired with the violation tool on the paths, in the design of small-scale component-level, last such path is fewer
When can repair manually, it is remaining although tool has repaired most violation in large-scale design
It is still relatively more to violate item number.Have been manually done relatively difficult, elapsed time is too long, and working efficiency is low, and it is possible to generate
New settling time violates and iterating could repeatedly repair completely.
Summary of the invention
For in high density physical Design, existing timing fix tool can not find enough on the basis of highdensity design
Space be inserted into buffer cell, can not be violated to the complete problem of repairing, the present invention proposes that a kind of retention time disobeys the retention time
Anti- restorative procedure by the position of mobile existing unit, and is inserted into and suitably repairs unit, finally repairs completely all
Retention time violates.
The technical scheme is that
A kind of restorative procedure that the retention time violates, firstly, when obtaining from the result of static timing analysis in the presence of keeping
Between the path starting point, terminal and the violation value that violate；Second, select the retention time violate path terminal as reparation unit to
It is inserted into node, repairs be inserted into a buffer cell or delay unit in ingress to be inserted every time, repairs unit pair to reduce to be inserted into
The influence of other path timing；Third, passing through shifting in the physical location that the near nodal searching unit that unit is repaired in insertion is put
In dynamic design the position of original unit with release repair unit needed for space, and set objective function and make mobile unit
Total cost is minimum, smaller to intrinsic disturbance；It corresponding repair logic fourth, generating, put unit, position of mobile unit
Engineering changing order；Finally, carrying out rewiring to the connection relationship for modifying logic, parasitic parameter is then extracted, is carried out quiet
It is complete that state Time-Series analysis confirms that the retention time repairs.
A kind of restorative procedure that the retention time violates, comprising the following steps:
The first step obtains path starting point, terminal and the violation violated there are the retention time from the result of static timing analysis
Value；
The result of 1.1 pairs of chip makes physical designs carries out static timing analysis, obtains each Time-Series analysis scene (timing
Analysis scene refers to the operating mode of chip and a kind of combination at manufacturing process angle.For example, the operating mode of a chip
Functional and test both of which, there are the worst, typical, best three kinds of process corners at manufacturing process angle, then in static timing analysis
When can be combined into " function+the worst ", " function+typical case ", " function+best ", " test+the worst ", " test+typical case " and
" test+best " six kinds of Time-Series analysis scenes.) in retention time violate path report；
The 1.2 signal jumps from the terminal, terminal unit input terminal interconnection line in acquisition timing violation path in path report
Time, terminal element-interconn ection linear load and violation value；
1.3 merge all identical path of terminal in each scene, and the timing violation value after merging takes under all scenes
Maximum violation value, is denoted as ti, violated with covering the retention time of all scenes；
1.4 finally obtain violation set of paths VP { vpi{ei,tri,loi,ti}}；
In set: vpiIt indicates to violate the i-th paths in set of paths, vpi∈ VP, i=1,2,3 ... n；
eiIndicate the terminal in violation path；
triIt indicates to violate signal bound-time on path termination element-interconn ection line；
loiIndicate the load of violation path termination element-interconn ection line；
tiIndicate the violation value in violation path.
Second step traversal violates set of paths, and the retention time in each path violates in repair capsule one by one；
2.1 using the terminal in retention time violation path as the insertion node for repairing unit, the type of selection insertion unit,
Insertion is single to repair unit, modifies logic connecting relation；
2.1.1 reading i-th, (i=1,2,3 ... n) paths obtain the coordinate for being inserted into node unit, i.e. violation path
Terminal unit coordinate (xei,yei)；
2.1.2 the delay unit and buffer cell for selecting several small multiple violate the cell columns repaired as the retention time
Table.For convenience of description, these units can be denoted as DEL_1, DEL_2, DEL_3, BUF_1, BUF_2, BUF_3 etc. respectively；
2.1.3 it by look-up table, obtains from the timing library file that technique manufacturer provides in bound-time tri and load
The delay size of unit selected in step 2.1.2 under the conditions of loi, can be denoted as respectively tdel_1, tdel_2, tdel_3,
tbuf_1,tbuf_2,tbuf_3；
2.1.4 compare the size relation of delay value in retention time violation value ti and step 2.1.3, selecting unit is delayed most
The reparation unit violated close to the unit of violation value ti as the reparation retention time；
2.1.5 node is connect being inserted into, i.e. unit selected by the terminal inserting step 2.1.4 in violation path, modification is patrolled
Collect connection relationship；
2.2 search blank position in insertion near nodal, put insertion unit, eliminate weight by the unit in mobile design
It is folded；
2.2.1 centered on violating path termination unit coordinate, each m row up and down is found in each distance k micron range in left and right
Put the blank position for repairing unit；
2.2.2 blank position is found, if the big reparation cell width of blank position width, placement unit do not need to move
It is dynamic；If the width of blank position is less than the width for repairing unit, mobile unit is needed to eliminate overlapping；
2.2.3 during eliminating cells overlap, by acquiring unit attribute, immovable register cell or clock
Set the unit with fixed attribute such as unit；
2.2.4 such as cells overlap cannot be eliminated by original unit in mobile design in the selected position, then abandons this
Position returns to step 2.2.1, searches blank position again；If can not find blank position under conditions of 2.2.1, will search
Rope range is expanded to each 2*m row up and down, and left and right is 2*k microns each, and so on；
2.2.5 obtain repair unit specific location coordinate (xai, yai) and and insertion cells overlap design in it is original
The position coordinates (xoi, yoi) of unit；
2.2.6 the width that note repairs unit is wai, is highly hai, and it is highly hoi that the width of overlapped elements, which is woi, by
This size that can calculate cells overlap part is, such as Fig. 2；
waoverlap=| (xai+wai)-xoi|if xai<xoi；
waoverlap=| (xoi+woi)-xai|if xoi<xai； (1)
2.2.7 the initial position for assuming any cell ci in design after unit is repaired in insertion is (xi, yi), once moves it
Coordinate afterwards be (i), cell width wi is highly hi, moves to unit ci by x ' i, y ', movement distance are as follows:
di=| x 'i-xi|+|y′i-yi| (2)
2.2.8 its disturbed value will be denoted as by the port number of mobile unit, the disturbed value of unit ci is denoted as its port number ei；Meter
Calculate the cost fm for eliminating overlapping mobile unit are as follows:
In formula, ei is by the item number of the mobile unit ci line influenced, the as port number of unit ci；
Di is the distance that unit is moved；
2.2.9 step 2.2.1~2.2.8 is repeated, traversal repairs unit and is inserted into owning near nodal specified range
It is inserted into repairing the position of unit, obtains mobile unit after unit is repaired in insertion and eliminate cost set F={ fm, the m=being overlapped
1,2,3……}；
2.2.10 blank position corresponding to f=min { fm } is chosen as being inserted into reparation unit putting in the design
Position, and carry out mobile unit according to minimum movement cost and eliminate cells overlap, it thus obtains be inserted into reparation unit and is designing
In final position be (xa ' i, ya ' is i)；
Third step writes out engineering changing order that placement-and-routing's tool can be read to corresponding file.
3.1 go out to modify the engineering changing order of logic connecting relation according to step 2.1.5；
3.2 write out the order for putting the order for repairing unit and mobile unit elimination overlapping according to step 2.2；
Line weight is arranged in 3.3 pairs of interconnection lines for modifying logic connecting relation, writes out the life of setting interconnection line weighted value
It enables；
4th step runs the engineering changing order of rewiring in placement-and-routing's tool, to modifying logic connecting relation
Design carries out rewiring；
5th step card repairs result；Static timing analysis is re-started to the design after reparation, until not having in design
Any retention time violates, and the confirmation retention time, which violates, repairs completely.
The beneficial effects of the present invention are: repairing unit by insertion, mobile unit is eliminated insertion and is repaired caused by unit
Cells overlap reduces and repairs the retention time and violate and design influence caused by timing to original, to the full extent in repair capsule
Retention time violates.
Detailed description of the invention
Fig. 1 is the higher schematic diagram for causing the retention time that can not repair of local density
Fig. 2 is that model of element schematic diagram is repaired in path insertion to be repaired；
Fig. 3 is flow chart of the invention；
Below with reference to the drawings and specific embodiments, invention is further described in detail.
Specific embodiment
As shown in figure 3, a kind of flow chart of the restorative procedure violated retention time for the present invention, the present invention includes following step
It is rapid:
The first step obtains path starting point, terminal and the violation violated there are the retention time from the result of static timing analysis
Value；
The result of 1.1 pairs of chip makes physical designs carries out static timing analysis, and the retention time obtained in each scene violates
Path report；
The 1.2 signal jumps from the terminal, terminal unit input terminal interconnection line in acquisition timing violation path in path report
Time, terminal element-interconn ection linear load and violation value；
1.3 merge all identical path of terminal in each scene, and the timing violation value after merging takes under all scenes
Maximum violation value, is denoted as ti, violated with covering the retention time of all scenes；
1.4 finally obtain violation set of paths VP { vpi{ei,tri,loi,ti}}；
In set: vpiIt indicates to violate the i-th paths in set of paths, vpi∈ VP, i=1,2,3 ... n；
eiIndicate the terminal in violation path；
triIt indicates to violate signal bound-time on path termination element-interconn ection line；
loiIndicate the load of violation path termination element-interconn ection line；
tiIndicate the violation value in violation path；
Second step traversal violates set of paths, and the retention time in each path violates in repair capsule one by one；
2.1 using the terminal in retention time violation path as the insertion node for repairing unit, the type of selection insertion unit,
Insertion is single to repair unit, modifies logic connecting relation；
2.1.1 reading i-th, (i=1,2,3 ... n) paths obtain the coordinate for being inserted into node unit, i.e. violation path
Terminal unit coordinate (xei,yei)；
2.1.2 the delay unit (* DEL*) and buffer cell (* BUF*) for selecting several small multiple are disobeyed as the retention time
Anti-revisionist multiple unit list, we select six kinds of units of DEL_1, DEL_2, DEL_3, BUF_1, BUF_2, BUF_3 here.
2.1.3 it by look-up table, obtains from the timing library file that technique manufacturer provides in bound-time tri and load
The delay size of six kinds of units, is denoted as tdel_1, tdel_2, tdel_3, tbuf_1, tbuf_2, tbuf_ respectively under the conditions of loi
3；
2.1.4 compare the size relation of six delay values in retention time violation value ti and 2.1.3, selecting unit is delayed most
The reparation unit violated close to the unit of violation value ti as the reparation retention time；
2.1.5 node is connect being inserted into, i.e. unit selected by the terminal insertion 2.1.4 in violation path, modification logic connects
Connect relationship；
2.2 search blank position in insertion near nodal, put insertion unit, eliminate weight by the unit in mobile design
It is folded；
2.2.1 centered on violating path termination unit coordinate, each m row up and down is found in each distance k micron range in left and right
Put the blank position for repairing unit；
2.2.2 blank position is found, if the big reparation cell width of blank position width, placement unit do not need to move
It is dynamic；If the width of blank position is less than the width for repairing unit, mobile unit is needed to eliminate overlapping；
2.2.3 during eliminating cells overlap, by acquiring unit attribute, immovable register cell or clock
Set the unit with fixed attribute such as unit；
2.2.4 such as cells overlap cannot be eliminated by original unit in mobile design in the selected position, then abandons this
Position returns to step 2.2.1, searches blank position again；If can not find blank position under conditions of 2.2.1, will search
Rope range is expanded to each 2*m row up and down, and left and right is 2*k microns each, and so on；
2.2.5 obtain repair unit specific location coordinate (xai, yai) and and insertion cells overlap design in it is original
The position coordinates (xoi, yoi) of unit；
2.2.6 the width that note repairs unit is wai, is highly hai, and it is highly hoi that the width of overlapped elements, which is woi, by
This size that can calculate cells overlap part is, such as Fig. 2；
waoverlap=| (xai+wai)-xoi|if xai<xoi；
waoverlap=| (xoi+woi)-xai|if xoi<xai； (1)
2.2.7 the initial position for assuming any cell ci in design after unit is repaired in insertion is (xi, yi), once moves it
Coordinate afterwards be (i), cell width wi is highly hi, moves to unit ci by x ' i, y ', movement distance are as follows:
di=| x'i-xi|+|y'i-yi| (2)
2.2.8 its disturbed value will be denoted as by the port number of mobile unit, the disturbed value of unit ci is denoted as its port number ei；Meter
Calculate the cost fm for eliminating overlapping mobile unit are as follows:
In formula, ei is by the item number of the mobile unit ci line influenced, the as port number of unit ci；
Di is the distance that unit ci is moved；
2.2.9 step 2.2.1~2.2.8 is repeated, traversal repairs unit and is inserted into owning near nodal specified range
It is inserted into repairing the position of unit, obtains mobile unit after unit is repaired in insertion and eliminate cost set F={ fm, the m=being overlapped
1,2,3……}；
2.2.10 blank position corresponding to f=min { fm } is chosen as being inserted into reparation unit putting in the design
Position, and carry out mobile unit according to minimum movement cost and eliminate cells overlap, it thus obtains be inserted into reparation unit and is designing
In final position be (xa ' i, ya ' is i)；
Third step writes out engineering changing order that placement-and-routing's tool can be read to corresponding file.
3.1 go out to modify the engineering changing order of logic connecting relation according to step 2.1.5；
3.2 write out the order for putting the order for repairing unit and mobile unit elimination overlapping according to step 2.2；
Line weight is arranged in 3.3 pairs of interconnection lines for modifying logic connecting relation, writes out the life of setting interconnection line weighted value
It enables；
4th step runs the engineering changing order of rewiring in placement-and-routing's tool, to modifying logic connecting relation
Design carries out rewiring；
5th step card repairs result；Static timing analysis is re-started to the design after reparation, until not having in design
Any retention time violates, and the confirmation retention time, which violates, repairs completely.
Claims (1)
1. the restorative procedure that a kind of retention time violates, it is characterised in that: the following steps are included:
The first step obtains path starting point, terminal and the violation value violated there are the retention time from the result of static timing analysis；
The result of 1.1 pairs of chip makes physical designs carries out static timing analysis, obtains the retention time in each Time-Series analysis scene
The path report of violation；
1.2 from obtained in path report timing violate the terminal in path, signal bound-time on terminal unit input terminal interconnection line,
Terminal element-interconn ection linear load and violation value；
1.3 merge all identical path of terminal in each scene, and the timing violation value after merging takes the maximum under all scenes
Violation value, is denoted as ti, violated with covering the retention time of all scenes；
1.4 finally obtain violation set of paths VP { vpi{ei,tri,loi,ti}}；
In set: vpiIt indicates to violate the i-th paths in set of paths, vpi∈ VP, i=1,2,3 ... n；
eiIndicate the terminal in violation path；
triIt indicates to violate signal bound-time on path termination element-interconn ection line；
loiIndicate the load of violation path termination element-interconn ection line；
tiIndicate the violation value in violation path；
Second step traversal violates set of paths, and the retention time in each path violates in repair capsule one by one；
2.1 using the terminal in retention time violation path as the insertion node for repairing unit, the type of selection insertion unit, insertion
It is single to repair unit, modify logic connecting relation；
2.1.1 the i-th paths are read, the coordinate for being inserted into node unit is obtained, that is, violates the terminal unit coordinate (x in pathei,
yei)；
2.1.2 the delay unit and buffer cell for selecting several small multiple violate the unit list repaired as the retention time；
2.1.3 it by look-up table, is obtained from the timing library file that technique manufacturer provides in bound-time tri and load loi item
The delay size of each unit selected in step 2.1.2 under part；
2.1.4 compare the size relation of delay value in retention time violation value ti and step 2.1.3, selecting unit delay is closest
The unit of violation value ti is as the reparation unit for repairing retention time violation；
2.1.5 node is connect being inserted into, i.e. unit selected by the terminal inserting step 2.1.4 in violation path, modification logic connects
Connect relationship；
2.2 search blank position in insertion near nodal, put insertion unit, eliminate overlapping by the unit in mobile design；
2.2.1 centered on violating path termination unit coordinate, each m row up and down is found in each distance k micron range in left and right and is put
Repair the blank position of unit；
2.2.2 blank position is found, if blank position width, which is greater than, repairs cell width, placement unit does not need to move；
If the width of blank position is less than the width for repairing unit, mobile unit is needed to eliminate overlapping；
2.2.3 during eliminating cells overlap, by acquiring unit attribute, the immovable unit with fixed attribute,
Unit with fixed attribute includes register cell, Clock Tree unit；
2.2.4 such as cells overlap cannot be eliminated by original unit in mobile design in the blank position being currently found, then abandoned
The blank position returns to step 2.2.1, searches blank position again；If can not find blank position under conditions of 2.2.1,
Search range is then expanded to each 2*m row up and down, left and right is 2*k microns each, and so on；
2.2.5 obtain repair unit specific location coordinate (xai, yai) and and insertion cells overlap design in original unit
Position coordinates (xoi, yoi)；
2.2.6 the width that note repairs unit is wai, is highly hai, and the width of overlapped elements is woi, is highly hoi, thus may be used
It is to calculate the size of cells overlap part,
waoverlap=| (xai+wai)-xoi|if xai<xoi；
waoverlap=| (xoi+woi)-xai|if xoi<xai； (1)
2.2.7 the initial position for assuming any cell ci in design after unit is repaired in insertion is (xi, yi), after primary mobile
Coordinate be (i), cell width wi is highly hi, moves to unit ci by x ' i, y ', movement distance are as follows:
di=| x'i-xi|+|y'i-yi| (2)
2.2.8 its disturbed value will be denoted as by the port number of mobile unit, the disturbed value of unit ci is denoted as its port number ei；Calculating disappears
Except the cost fm of overlapping mobile unit are as follows:
In formula, ei is by the item number of the mobile unit ci line influenced, the as port number of unit ci；
Di is the distance that unit ci is moved；
2.2.9 repeat step 2.2.1~2.2.8, traversal repair that unit is inserted near nodal specified range it is all can
Insertion repair unit position, obtain insertion repair unit after mobile unit eliminate overlapping cost set F=fm, m=1,2,
3……}；
2.2.10 blank position corresponding to f=min { fm } is chosen as being inserted into reparation unit placement position in the design,
And carry out mobile unit according to minimum movement cost and eliminate cells overlap, it thus obtains being inserted into and repairs unit in the design most
Final position is set to that (xa ' i, ya ' is i)；
Third step writes out engineering changing order that placement-and-routing's tool can be read to corresponding file
3.1 going out to modify the engineering changing order of logic connecting relation according to step 2.1.5；
3.2 write out the order for putting the order for repairing unit and mobile unit elimination overlapping according to step 2.2；
Line weight is arranged in 3.3 pairs of interconnection lines for modifying logic connecting relation, writes out the order of setting interconnection line weighted value；
4th step runs the engineering changing order of rewiring in placement-and-routing's tool, sets to logic connecting relation was modified
Meter carries out rewiring；
5th step card repairs result；Static timing analysis is re-started to the design after reparation, until not keeping in design
Time violation, the confirmation retention time, which violates, repairs completely.
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