CN112257375B - Layout adjustment method and device for integrated circuit design and electronic equipment - Google Patents
Layout adjustment method and device for integrated circuit design and electronic equipment Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
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- G06F30/396—Clock trees
Abstract
A layout adjustment method, apparatus, non-transitory readable storage medium, and electronic device for integrated circuit design. The layout adjustment method for integrated circuit design comprises the following steps: acquiring a first layout structure of a clock structure in an integrated circuit, wherein the clock structure comprises a gating clock unit, a driving unit corresponding to the gating clock unit and a plurality of loads; and carrying out layout adjustment on the first layout structure based on a first distance between the driving unit and the plurality of loads in the first layout structure and positions of the plurality of loads to obtain a second layout structure. The layout adjustment method can discover and solve the time sequence problem of clock structure cloning in advance by automatically checking the rationality of the layout of the integrated circuit and adjusting the layout, thereby optimizing the time sequence problem of clock structure cloning and reducing the power consumption.
Description
Technical Field
Embodiments of the present disclosure relate to a layout adjustment method, apparatus, non-transitory readable storage medium, and electronic device for integrated circuit design.
Background
In large scale integrated circuit designs, a single clock source signal drives numerous sequential devices (e.g., registers, latches, memories, etc.). If the sequential device is driven directly with the clock source signal, the driving capability becomes a problem, and too long wiring from the clock source to the register clock terminal causes a problem of too long delay. Therefore, it is common to drive the sequential devices in a clock distribution network, i.e. a buffer or an inverter is inserted between the clock source and the sequential devices, so as to form a clock distribution network. Current clock distribution networks typically employ a clock tree architecture.
Disclosure of Invention
Embodiments of the present disclosure provide a layout adjustment method for integrated circuit design, comprising: acquiring a first layout structure of a clock structure in an integrated circuit, wherein the clock structure comprises a gating clock unit, a driving unit corresponding to the gating clock unit and a plurality of loads; and carrying out layout adjustment on the first layout structure based on a first distance between the driving unit and the plurality of loads and positions of the plurality of loads in the first layout structure so as to obtain a second layout structure.
For example, in a layout adjustment method provided in at least one embodiment of the present disclosure, performing layout adjustment on the first layout structure to obtain a second layout structure based on a first distance between the driving unit and the plurality of loads and positions of the plurality of loads in the first layout structure, includes: acquiring a maximum distance between the driving unit and the plurality of loads in the first layout structure as the first distance; detecting the position of each load in the first layout structure; judging whether the positions of the loads meet preset conditions or not based on the first distance; and if not, adjusting the position of the load which does not meet the preset condition to obtain the second layout structure.
For example, in a layout adjustment method provided by at least one embodiment of the present disclosure, obtaining, as the first distance, a maximum distance between the driving unit and the plurality of loads in the first layout structure includes: acquiring a second distance between the gating clock unit and the driving unit in the first layout structure; acquiring a third distance between the gating clock unit and a target load in the first layout structure; the maximum distance is obtained based on the second distance and the third distance as the first distance, and the target load is a load corresponding to the first distance among the plurality of loads.
For example, in the layout adjustment method provided in at least one embodiment of the present disclosure, the first distance is represented by the following expression:
D1＝D2+D3，
wherein D1 represents the first distance, D2 represents the second distance, and D3 represents the third distance.
For example, in the layout adjustment method provided in at least one embodiment of the present disclosure, the second distance is represented by the following expression:
D2＝(P+D skw –T stp –D100 ck-q )/σ，
wherein D2 represents the second distance, P represents the clock period of the clock signal, T stp Representing the setup time of the gated clock unit, D skw D100 represents the clock offset between the gated clock cells and the drive cells ck-q Representing the cell delay of the drive unit, sigma representing the delay per unit line length.
For example, in a layout adjustment method provided in at least one embodiment of the present disclosure, obtaining a third distance between the gated clock cells and a target load in the first layout structure includes: and obtaining the third distance between the gating clock unit and the target load based on clock conversion time, fan-out number of the gating clock unit and clock delay of the target load.
For example, in the layout adjustment method provided in at least one embodiment of the present disclosure, the preset condition includes that a winding distance of each load is smaller than the first distance.
For example, in the layout adjustment method provided in at least one embodiment of the present disclosure, the winding distance of each load is represented by the following expression:
d＝x+y，
where d represents a winding distance of the load, x represents a distance of the load to the driving unit in a first direction, and y represents a distance of the load to the driving unit in a second direction.
For example, in a layout adjustment method provided by at least one embodiment of the present disclosure, the first direction and the second direction are orthogonal to each other.
For example, the layout adjustment method provided in at least one embodiment of the present disclosure further includes: and executing clock cloning operation based on the second layout structure to obtain a third layout structure.
For example, the layout adjustment method provided in at least one embodiment of the present disclosure further includes: obtaining an input netlist of the clock structure in the integrated circuit; and acquiring the first layout structure based on the input netlist.
Embodiments of the present disclosure also provide an apparatus for integrated circuit design, comprising: an acquisition unit configured to acquire a first layout structure of a clock structure in an integrated circuit, the clock structure including a gating clock unit, a driving unit corresponding to the gating clock unit, and a plurality of loads; and an adjustment unit configured to perform layout adjustment on the first layout structure based on a first distance between the driving unit and the plurality of loads and positions of the plurality of loads in the first layout structure to obtain a second layout structure.
For example, the apparatus provided in at least one embodiment of the present disclosure further includes a cloning unit configured to perform a clock cloning operation based on the second layout structure, resulting in a third layout structure.
Embodiments of the present disclosure also provide an apparatus for integrated circuit design, comprising: a processor; a memory including one or more computer program modules; the one or more computer program modules are stored in the memory and configured to be executed by the processor, the one or more computer program modules comprising instructions for performing the layout adjustment method for integrated circuit design as described above.
Embodiments of the present disclosure also provide a non-transitory readable storage medium having stored thereon computer instructions that, when executed by a processor, perform a layout adjustment method for integrated circuit design as described above.
Embodiments of the present disclosure also provide an electronic device comprising an apparatus for integrated circuit design as described above.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following brief description of the drawings of the embodiments will make it apparent that the drawings described below relate only to some embodiments of the present disclosure and are not limiting of the present disclosure.
FIG. 1A is a schematic diagram of a laid out clock structure;
FIG. 1B is a schematic diagram of a clock structure after clock cloning based on the laid out clock structure of FIG. 1A;
FIG. 2 is a flow diagram of a layout adjustment method for an integrated circuit design in accordance with at least one embodiment of the present disclosure;
FIG. 3A is a schematic diagram of a first layout structure of a clock structure in accordance with at least one embodiment of the present disclosure;
FIG. 3B is a schematic diagram of a second layout structure of a clock structure in accordance with at least one embodiment of the present disclosure;
FIG. 4 is a flowchart of an example operation corresponding to step S102 of FIG. 2 in accordance with at least one embodiment of the present disclosure;
FIG. 5 is a schematic diagram of a gating circuit according to at least one embodiment of the present disclosure;
FIG. 6 is a flow chart of another layout adjustment method for integrated circuit design provided by at least one embodiment of the present disclosure;
FIG. 7 is a flowchart of an example operation of steps S302 and S303 of FIG. 6 provided in accordance with at least one embodiment of the present disclosure;
FIG. 8 is a schematic diagram of an input netlist of a clock structure in accordance with at least one embodiment of the present disclosure;
FIG. 9 is a schematic diagram of a third layout structure of a clock structure in accordance with at least one embodiment of the present disclosure;
FIG. 10A is a schematic block diagram of an apparatus for integrated circuit design in accordance with at least one embodiment of the present disclosure;
FIG. 10B is a schematic block diagram of another apparatus for integrated circuit design in accordance with at least one embodiment of the present disclosure;
FIG. 11 is a schematic block diagram of yet another apparatus for integrated circuit design in accordance with at least one embodiment of the present disclosure;
FIG. 12 is a schematic block diagram of a non-transitory readable storage medium according to at least one embodiment of the present disclosure; and
fig. 13 is a schematic block diagram of an electronic device in accordance with at least one embodiment of the present disclosure.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by one of ordinary skill in the art without the need for inventive faculty, are within the scope of the present disclosure, based on the described embodiments of the present disclosure.
Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Likewise, the terms "a," "an," or "the" and similar terms do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.
Clock tree creation for high performance chips typically uses cloning techniques. The principle of clock cloning technology is to determine the number and location of cloned clock units based on the physical location of load registers of a layout that is optimized based on a timing relationship path. For example, FIG. 1A is a schematic diagram of a laid out clock structure. As shown in fig. 1A, clk represents a clock signal line, 101 represents a gating clock unit, for example, a gating clock unit of a top clock, 100 represents a driving unit of a data terminal of the gating clock unit, that is, a driving unit corresponding to the gating clock unit 101, 103 represents logic units except the gating clock unit on a clock tree, 102 and 111 represent loads, for example, load registers, and 104 represents a gating clock unit of a low-end gating clock, for example, a gating clock unit of a local clock. FIG. 1B is a schematic diagram of a clock structure after clock cloning based on the laid out clock structure of FIG. 1A. Referring to fig. 1A and 1B, the gating clock cells 105 and 108 are cloned gating clock cells corresponding to the gating clock cell 101, the logic cells 106 and 109 are cloned logic cells corresponding to the logic cell 103, the gating clock cells 107 and 110 are cloned low-side gating clock cells corresponding to the gating clock cell 104, and the positions of the load registers 102, 111 remain unchanged.
The technology has the following difficulties and defects in practical application: the clock cloning pre-driver unit 100 has a timing check with the gated clock unit 101, the load registers 102, 111 are loads of the gated clock unit 101, the layout optimization only takes these factors into account, and the timing of the cloning units (e.g., the gated clock units 108, 105, etc.) is not considered in the pre-cloning layout optimization stage; because the physical distance creates timing issues, there is a timing check between the cloned gated clock Unit 108 and the drive Unit 100 after clock cloning; cloning units 108, 109, 110 may increase power consumption. These problems occur in the middle and late stages of design affecting project progress; a new and more difficult timing interlock problem is introduced if the gating clock unit 108 is not an integrated unit, for example, the Setup Time (Setup Time) and Hold Time (Hold Time) conflict with each other. The setup time refers to the time required for data to be unstable to settle before the clock acquisition edge arrives, and if the setup time is not satisfactory, the data cannot be stably driven into the sequential device at this clock edge. The retention time is the time to be retained after the data is stabilized, and if the retention time does not meet the requirement, the data cannot be stably driven into the sequential device.
In view of the above problems, a solution adopted by those skilled in the art is to repair the found timing problem under a cloned clock structure, for example, the timing of a cloned gated clock unit is checked only after a clock tree, and if the timing is difficult to converge, the solution still needs to be returned through optimizing layout operation, which leads to a later found problem. If the timing cannot be repaired, product performance is affected and power consumption of the integrated circuit is increased.
At least one embodiment of the present disclosure provides a layout adjustment method for an integrated circuit design, comprising: acquiring a first layout structure of a clock structure in an integrated circuit, wherein the clock structure comprises a gating clock unit, a driving unit corresponding to the gating clock unit and a plurality of loads; and carrying out layout adjustment on the first layout structure based on a first distance between the driving unit and the plurality of loads in the first layout structure and positions of the plurality of loads to obtain a second layout structure. At least one embodiment of the present disclosure also provides an apparatus, a non-transitory readable storage medium, and an electronic device corresponding to the above-described layout adjustment method.
By the layout adjustment method provided by the embodiment of the disclosure, the layout is automatically detected and automatically adjusted, so that clock cloning operation is executed after the layout is reasonable, thereby discovering and solving the time sequence problem in advance, shortening the project research and development time, reducing the number of clock cloning units and reducing the power consumption.
The layout adjustment method provided according to at least one embodiment of the present disclosure is described below in a non-limiting manner by means of several examples or embodiments, and as described below, different features in these specific examples or embodiments may be combined with each other without contradiction, thereby obtaining new examples or embodiments, which also fall within the scope of protection of the present disclosure.
Fig. 2 is a flow chart of a layout adjustment method for integrated circuit design according to at least one embodiment of the present disclosure.
For example, in at least one embodiment of the present disclosure, as shown in FIG. 2, a layout adjustment method 10 for an integrated circuit design may include the steps of:
step S101: acquiring a first layout structure of a clock structure in an integrated circuit, wherein the clock structure comprises a gating clock unit, a driving unit corresponding to the gating clock unit and a plurality of loads;
step S102: and carrying out layout adjustment on the first layout structure based on a first distance between the driving unit and the plurality of loads in the first layout structure and positions of the plurality of loads to obtain a second layout structure.
The layout adjustment method 10 for integrated circuit design according to the embodiments of the present disclosure adds a layout adjustment for optimizing clock cloning after conventional layout optimization, i.e. adjusts from the first layout structure to the second layout structure, so as to discover and solve the timing problem in advance, reduce the number of clock cloning units, and reduce the clock power consumption.
Fig. 3A is a schematic diagram of a first layout structure of a clock structure provided in at least one embodiment of the present disclosure, fig. 3B is a schematic diagram of a second layout structure of a clock structure provided in at least one embodiment of the present disclosure, and fig. 4 is an exemplary operation flowchart corresponding to step S102 in fig. 2 according to at least one embodiment of the present disclosure.
For step S101, the acquired first layout structure refers to a clock structure after layout placement (e.g., after conventional layout optimization). As shown in fig. 3A, the first layout structure includes a gate clock unit 101 of a clock structure, a driving unit 100 corresponding to the gate clock unit 101, a low-side gate clock unit 104, logic units 130, 103 other than the gate clock unit, and a plurality of load registers 102, 111, and the like.
For example, referring to fig. 4, in at least one embodiment of the present disclosure, for step S102, performing layout adjustment on a first layout structure to obtain a second layout structure based on a first distance between a driving unit and a plurality of loads and positions of the plurality of loads in the first layout structure may include the following steps S201 to S204.
Step S201: acquiring a maximum distance between a driving unit and a plurality of loads in a first layout structure as a first distance;
Step S202: detecting the position of each load in the first layout structure;
step S203: judging whether the positions of the loads meet preset conditions or not based on the first distance;
step S204: if not, the position of the load which does not meet the preset condition is adjusted to obtain a second layout structure.
For example, in at least one embodiment of the present disclosure, for step S201, acquiring, as a first distance, a maximum distance between a driving unit and a plurality of loads in a first layout structure includes: acquiring a second distance between a gating clock unit and a driving unit in the first layout structure; acquiring a third distance between a gating clock unit and a target load in the first layout structure; the maximum distance is obtained based on the second distance and the third distance as the first distance. For example, the target load is a load corresponding to the first distance among the plurality of loads.
For example, in at least one embodiment of the present disclosure, taking the first layout structure shown in fig. 3A as an example, a method of acquiring the first distance D1 is described in detail below.
For example, as shown in fig. 3A, it is assumed that the target load determined based on the obtained first distance D1 (e.g., D1 is calculated by the following method) is the load register 111 located at the position (x 2, y 2) in fig. 3A, in which case the second distance D2 refers to the distance between the gating clock unit 101 and the driving unit 100, and the third distance D3 refers to the distance between the gating clock unit 101 and the target load (e.g., the load register 111 located at the position (x 2, y 2). Fig. 3A shows a horizontal coordinate axis X and a vertical coordinate axis Y with the position (X0, Y0) of the driving unit 100 as the origin of coordinates in which the position of the gating clock unit 101 is assumed to be (X1, Y1), the position of the target load is assumed to be (X2, Y2), and the position of some other load register 111 is assumed to be (X3, Y3), as shown in fig. 3A.
Note that, in the embodiment of the present disclosure, the target load is a load corresponding to the first distance D1 among the loads of the first layout structure. For example, the first distance D1 is obtained first by a method described below, and then the target load among the plurality of loads can be determined based on the first distance D1. Thus, the target load is not necessarily the load register 111 at the position (x 2, y 2) shown in fig. 3A, but may be other load registers, which is determined according to the actual situation, and the embodiment of the present disclosure is not particularly limited thereto.
For example, in one example, first, the second distance D2 and the third distance D3 in the first layout structure are calculated, respectively, and then the maximum distance is obtained based on the second distance D2 and the third distance D3 as the first distance D1.
Note that, in the embodiment of the present disclosure, the first distance D1, the second distance D2, and the third distance D3 are not straight-line distances between specific logic units, but are calculated by the following various expressions.
For example, in at least one embodiment of the present disclosure, the second distance may be represented by the following expression (1):
D2＝(P+D skw –T stp –D100 ck-q )/σ (1)
where D2 represents the second distance, P represents the clock period of the clock signal clk, T stp Represents the setup time of the gating clock cell 101, D skw Represents the clock offset between the gated clock cell 101 and the drive cell 100, D100 ck-q Representing the cell delay of the drive unit 100, i.e. the delay of the ck to q-terminal of the drive unit 100, sigma represents the delay per line length.
The calculation method of the second distance (i.e., the second distance D2 between the gating clock cell 101 and the driving cell 100) is explained in detail below with reference to fig. 5.
Fig. 5 is a schematic diagram of a gating circuit according to at least one embodiment of the present disclosure.
Referring to fig. 5, in the gating circuit, the timing requirements of the gating clock unit 101 are: the data arrival time of the gating clock unit 101 is less than or equal to the data demand time of the gating clock unit 101.
The data arrival time of the gated clock cell 101 can be expressed as: d120+d100 ck-q +D130；
Data demand time table of gating clock unit 101The method is shown as follows: P+D121-D101 stp ；
According to the above timing requirements, it is possible to obtain:
D120+D100 ck-q +D130<＝P+D121-D101 stp
D130<＝P+D121–D101 stp -D120–D100 ck-q
D2*σ<＝P+D121–D101 stp -D120–D100 ck-q
D2<＝(P+D121-D120–D101 stp –D100 ck-q )/σ
D2<＝(P+D skw –D101 stp –D100 ck-q )/σ
where D120 represents the clock delay of the driving unit 100, D121 represents the clock delay of the gating clock unit 101, that is, D in the above expression (1) skw ＝(D121-D120)，D100 ck-q Representing the cell delay of the drive unit 100, i.e. the delay of the ck to q-terminal, D130 represents the path delay of the data-terminal of the gated clock cell 101, P is the clock period of the gated clock cell 101, D101 stp Representing the data setup time of the gating clock cell 101, i.e., T in expression (1) above stp ＝D101 stp Sigma represents the delay per unit line length.
It should be noted that, the value of the delay σ of the unit line length is related to the process and the logic depth on the path actually adopted by the technician, and the specific value of σ is not limited in the embodiments of the present disclosure and may be set according to the actual situation.
For example, in at least one embodiment of the present disclosure, as shown in fig. 3A, obtaining a third distance D3 between the gated clock cell 101 and the target load in the first layout structure includes: based on the clock transition time, the fan-out of the gated clock cells 101, the clock delay of the target load, a third distance D3 between the gated clock cells 101 and the target load is obtained.
It should be noted that the third distance D3 is determined empirically according to actual design requirements or design goals, which is not limited by the embodiment of the present disclosure.
For example, in at least one embodiment of the present disclosure, based on the above-described second distance D2 and third distance D3, a maximum distance may be obtained as the first distance D1.
For example, in at least one embodiment of the present disclosure, it is represented by the following expression:
D1＝D2+D3，
Wherein D1 represents a first distance, D2 represents a second distance, and D3 represents a third distance.
For step S202, the positions of the respective loads in the first layout structure are detected.
For example, in at least one embodiment of the present disclosure, as shown in fig. 3A, the location of some other load register 111 is (x 3, y 3). Likewise, the location of other load registers 102 may be detected or scanned, and the particular detection method of embodiments of the present disclosure is not limited and conventional detection methods may be employed.
For step S203, it is determined whether the positions of the respective loads satisfy the preset condition based on the first distance.
For example, in at least one embodiment of the present disclosure, the preset condition may be that a winding distance of each load is less than the first distance.
For example, in at least one embodiment of the present disclosure, the winding distance of each load is represented by the following expression:
d＝x+y，
where d represents the winding distance of the load, x represents the distance of the load to the drive unit in the first direction, and y represents the distance of the load to the drive unit in the second direction.
For example, in one example, the first direction and the second direction are orthogonal to each other.
For example, referring to fig. 3A, based on the X and Y coordinate axes shown in fig. 3A, the position of a certain load register 111 is (X3, Y3), the winding distance d of the load register 111 is |x3|+|y3| along the horizontal coordinate axis X in the first direction and along the vertical coordinate axis Y in the second direction.
For example, with the first layout structure shown in fig. 3A, it is determined whether the winding distance D of each load register (e.g., the load registers 111, 102, etc.) is smaller than the first distance D1.
It should be noted that the preset conditions may be set according to actual situations, and the embodiment of the present disclosure is not particularly limited thereto.
For step S204, if not, the position of the load that does not satisfy the preset condition is adjusted to obtain the second layout structure.
For example, referring to fig. 3A, if the position of a load in the first layout structure shown in fig. 3A does not satisfy a preset condition, for example, the winding distance D of the load is greater than or equal to the first distance D1 in the above embodiment, the load that does not satisfy the preset condition is subjected to targeted position adjustment (for example, left shift, right shift, etc. according to the timing attribute, physical attribute, etc. of the corresponding load register) until it is determined that the positions of all the loads in the first layout structure satisfy the preset condition, thereby obtaining a second layout structure, for example, obtaining the second layout structure shown in fig. 3B.
It should be noted that, the specific operation of the position adjustment of the load according to the embodiment of the present disclosure is not limited, and a conventional position adjustment operation may be adopted.
For ease of understanding, the layout adjustment method 10 provided by embodiments of the present disclosure is further described in conjunction with fig. 5 and 3A. For example, in one example, it is assumed that in the first layout structure, the position of the driving unit 100 is (x 0, y 0) = (0, 0), the position of the gating clock unit 101 is (x 1, y 1) = (50, 40), and a certain load register 111 is located at the position (x 3, y 3), where (x 3, y 3) = (280,200).
As described above, in order to calculate the first distance D1, the second distance D2 and the third distance D3 are first calculated.
1) Calculating a second distance D2:
for example, assuming that the clock delay d120=60 ps (picoseconds) of the driving unit 100, the clock delay d121=2 ps of the gate clock unit 101, the delay D100 of the ck to q terminal of the driving unit 100 ck-q Data setup time D101 of gated clock cell 101 =30ps stp =15 ps, clock period p=300 ps of the gated clock cell 101, and when the 7nm (nanometer) process is adopted, the logic depth of the cell data path of the gated clock cell 101 is 10 stagesIn case σ=0.5.
Thus, for the second distance D2 (i.e., the distance between the gating clock cell 101 and the driving cell 100), with the expression (1) described above, it is possible to obtain:
D2＝(P+D121–D101 stp -D120–D100 ck-q )/σ。
for example, d2= (300+2-15-60-30)/0.5=394 μm
2) Calculating a third distance D3:
for example, according to an actual design objective or design requirement, the clock transition time is 30ps, the fanout number (fanout) of the gate clock unit 101 is 40, and the clock delay of the target load is 60ps, so that the distance between the target load and the gate clock unit 101 is 50 μm (micrometers).
3) Calculating a first distance D1:
D1＝D2+D3。
for example, d1=394+50=444 μm.
For example, in one example, according to the first distance D1 obtained by the above-described calculation method, the target load in the first layout structure shown in fig. 3A may be determined as the load register 111 located at the position (x 2, y 2).
Next, the position of each load in the first layout structure is detected or scanned, and it is determined whether the position of each load is satisfied, for example, the winding distance D < D1.
For example, in this example, the position of a certain load register 111 is (x 3, y 3), where (x 3, y 3) = (280,200), and the winding distance d=280+200=480 μm of the load register 111 at (x 3, y 3), it is seen that the load register 111 does not satisfy the preset condition, and the position of the load register 111 is adjusted specifically. For example, by grabbing the timing check attribute of the load register 111, shifting left by 36 μm or the like in the horizontal direction, the embodiment of the present disclosure does not limit the position adjustment operation. And until the positions of all loads in the first layout structure are determined to meet the preset condition, thereby obtaining the second layout structure.
The layout adjustment method 10 for integrated circuit design according to the embodiments of the present disclosure adds a layout adjustment for optimizing clock cloning after conventional layout optimization, i.e. adjusts from the first layout structure to the second layout structure, so as to discover and solve the timing problem in advance, reduce the number of clock cloning units, and reduce the clock power consumption.
Fig. 6 is a schematic diagram of another layout adjustment method for an integrated circuit design provided in accordance with at least one embodiment of the present disclosure, fig. 7 is a flowchart illustrating an example operation of steps S302 and S303 in fig. 6 provided in accordance with at least one embodiment of the present disclosure, fig. 8 is a schematic diagram of an input netlist of a clock structure in accordance with at least one embodiment of the present disclosure, and fig. 9 is a schematic diagram of a third layout structure of a clock structure in accordance with at least one embodiment of the present disclosure.
For example, at least one embodiment of the present disclosure provides another layout adjustment method 30 for integrated circuit design. The layout adjustment method 30 includes steps S301-S303. The layout adjustment method 30 shown in fig. 6 additionally includes step S301 and step S303, compared to the layout adjustment method 10 shown in fig. 2.
For example, in step S301, an input netlist of a clock structure in an integrated circuit is obtained, and a first layout structure is obtained based on the input netlist. That is, the input netlist of the clock structure is placed in layout. For example, in one example, the input netlist is used to represent the clock structure in the original integrated circuit, as shown in FIG. 8, and includes the logical relationships between the logic cells of the integrated circuit design, and does not include layout information. The first layout structure is obtained by performing layout optimization on the input netlist, as shown in fig. 3A.
It should be noted that the first layout structure is a result of performing conventional layout optimization on the input netlist of the clock structure. Embodiments of the present disclosure will not be described in detail with respect to conventional layout optimization, and reference may be made to the relevant literature.
In step S302, the layout adjustment for optimizing the clock cloning, that is, the adjustment from the first layout structure (see fig. 3A) to the second layout structure (see fig. 3B), is performed, and the specific operation of step S302 may refer to the specific description of the above layout adjustment method 10, which is not repeated herein.
In step S303, a clock cloning operation is performed based on the second layout structure, resulting in a third layout structure.
For example, in at least one embodiment of the present disclosure, a third layout structure as shown in fig. 9 may be obtained based on the second layout structure as shown in fig. 3B. Referring to fig. 9, clone unit 105 corresponds to gating clock unit 101 and clone unit 107 corresponds to low-side gating clock unit 104.
For example, referring to fig. 7, in at least one embodiment of the present disclosure, in step S401, the maximum distance between the driving unit and the load registers in the first layout structure is calculated by the method described above, in step S402, the positions of all the load registers in the first layout structure are detected, in step S403, it is determined whether the position of each load register needs to be adjusted, for example, by determining whether the position of each load register satisfies a specific preset condition, and if each load register satisfies, step S405 is performed to perform a clock cloning operation based on the current layout structure; if the load registers are not satisfied, step S404 is executed, and position adjustment is performed for the load registers that do not satisfy the condition, and then the judgment step S403 is returned to perform judgment until the positions of all the load registers satisfy the condition, and step S405 is executed without readjusting, and clock cloning is performed.
Comparing the cloned clock structure (fig. 9) after the layout adjustment method 10 or 30 of the present disclosure with the cloned clock structure (fig. 1B) after cloning based on the laid-out clock structure shown in fig. 1A, it can be seen that the layout adjustment method 10 or 30 provided by the embodiment of the present disclosure can avoid cloning the clone units 108, 109, 110 in fig. 1B, thereby reducing power consumption, avoiding timing problems caused by physical distances of the gate clock unit 108, and improving clock performance.
The layout adjustment methods 10 and 30 provided by the embodiments of the present disclosure can be applied to clock cloning of all structures by calculating the maximum distance between the driving units and the load registers of the gating circuit before performing the clock cloning operation, checking all the physical positions of the registers and optimizing the load register layout, finding and solving timing problems in advance, improving product performance, shortening project development time, reducing clock cloning units, reducing power consumption, and optimizing EDA (electronic design automation) tools.
It should be noted that, in the embodiments of the present disclosure, the execution order of the steps of the layout adjustment method is not limited, and although the execution process of the steps is described in a specific order above, this does not constitute a limitation to the embodiments of the present disclosure. The steps in the layout adjustment method may be performed in series or in parallel, which may be according to actual requirements. The video processing method may also include more or fewer steps, as embodiments of the present disclosure are not limited in this regard.
Fig. 10A is a schematic block diagram of an apparatus for integrated circuit design in accordance with at least one embodiment of the present disclosure, and fig. 10B is a schematic block diagram of another apparatus for integrated circuit design in accordance with at least one embodiment of the present disclosure.
Embodiments of the present disclosure also provide an apparatus for integrated circuit design, as shown in fig. 10A, the apparatus 80 for integrated circuit design includes an acquisition unit 801 and an adjustment unit 802.
The acquisition unit 801 is configured to acquire a first layout structure of a clock structure in an integrated circuit. For example, the clock structure includes a gated clock unit, a driving unit corresponding to the gated clock unit, and a plurality of loads. For example, the obtaining unit 801 may implement step S101, and a specific implementation method thereof may refer to a description related to step S101, which is not described herein.
The adjustment unit 802 is configured to perform layout adjustment on the first layout structure based on a first distance between the driving unit and the plurality of loads in the first layout structure and positions of the plurality of loads to obtain a second layout structure. For example, the adjusting unit 802 may implement step S102, and a specific implementation method thereof may refer to the related description of step S102, which is not described herein.
For example, in at least one embodiment of the present disclosure, as shown in fig. 10B, the apparatus 80 further includes a cloning unit 803 on the basis of the example shown in fig. 10A. The cloning unit 803 is configured to perform a clock cloning operation based on the second layout structure resulting in a third layout structure.
For example, the specific operations that the obtaining unit 801, the adjusting unit 802, and the cloning unit 803 are configured to perform may refer to the relevant descriptions of the layout adjustment methods 10 and 30 provided in at least one embodiment of the present disclosure, which are not described herein.
It should be noted that, these obtaining unit 801, adjusting unit 802, and cloning unit 803 may be implemented by software, hardware, firmware, or any combination thereof, for example, may be implemented as obtaining circuit 801, adjusting circuit 802, and cloning circuit 803, respectively, and embodiments of the present disclosure are not limited to their specific implementation.
It should be understood that the apparatus 80 for integrated circuit design according to the embodiments of the present disclosure may implement the foregoing layout adjustment methods 10 and 30, and may also achieve similar technical effects as the foregoing layout adjustment methods 10 and 30, which are not described herein.
It should be noted that, in the embodiments of the present disclosure, the apparatus for designing an integrated circuit may include more or less circuits or units, and the connection relationship between the respective circuits or units is not limited, and may be determined according to actual requirements. The specific configuration of each circuit is not limited, and may be constituted by an analog device, a digital chip, or other suitable means according to the circuit principle.
Embodiments of the present disclosure also provide an apparatus for integrated circuit design. Fig. 11 is a schematic block diagram of another apparatus for integrated circuit design in accordance with at least one embodiment of the present disclosure. As shown in fig. 11, the apparatus 90 includes a processor 910 and a memory 920. Memory 920 includes one or more computer program modules 921. One or more computer program modules 921 are stored in the memory 920 and configured to be executed by the processor 910, the one or more computer program modules 921 including instructions for performing the layout adjustment method 10 or 30 provided by at least one embodiment of the present disclosure, which when executed by the processor 910, can perform one or more steps of the layout adjustment method 10 or 30 provided by at least one embodiment of the present disclosure. The memory 920 and the processor 910 may be interconnected by a bus system and/or other form of connection mechanism (not shown).
For example, the processor 910 may be a Central Processing Unit (CPU), a Digital Signal Processor (DSP), or other form of processing unit having data processing and/or program execution capabilities, such as a Field Programmable Gate Array (FPGA), or the like; for example, the Central Processing Unit (CPU) may be an X86 or ARM architecture, or the like. Processor 910 may be a general purpose processor or a special purpose processor that may control other components in apparatus 90 to perform the desired functions.
For example, memory 920 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and/or non-volatile memory. Volatile memory can include, for example, random Access Memory (RAM) and/or cache memory (cache) and the like. The non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, and the like. One or more computer program modules 921 may be stored on the computer readable storage medium, and the processor 910 may execute the one or more computer program modules 921 to implement the various functions of the apparatus 90. Various applications and various data, as well as various data used and/or generated by the applications, etc., may also be stored in the computer readable storage medium. The specific functions and technical effects of the apparatus 90 may be referred to the description of the layout adjustment method hereinabove, and will not be repeated here.
Embodiments of the present disclosure also provide a non-transitory readable storage medium. Fig. 12 is a schematic block diagram of a non-transitory readable storage medium according to at least one embodiment of the present disclosure. As shown in fig. 12, the non-transitory readable storage medium 100 has stored thereon computer instructions 111 that when executed by a processor perform one or more of the steps of the layout adjustment method 10 or 30 for integrated circuit design as described above.
For example, the non-transitory readable storage medium 100 may be any combination of one or more computer readable storage media, such as one containing computer readable program code for obtaining a first layout structure of a clock structure in an integrated circuit and another containing computer readable program code for performing layout adjustment of the first layout structure to obtain a second layout structure based on a first distance between a drive unit and a plurality of loads in the first layout structure and a position of the plurality of loads. Of course, the various program codes described above may also be stored on the same computer-readable medium, as embodiments of the present disclosure are not limited in this regard. For example, when the program code is read by a computer, the computer may execute the program code stored in the computer storage medium, performing a layout adjustment method such as provided by any of the embodiments of the present disclosure.
For example, the storage medium may include a memory card of a smart phone, a memory component of a tablet computer, a hard disk of a personal computer, random Access Memory (RAM), read Only Memory (ROM), erasable Programmable Read Only Memory (EPROM), portable compact disc read only memory (CD-ROM), flash memory, or any combination of the foregoing, as well as other suitable storage media. For example, the readable storage medium may also be the memory 920 in fig. 11, and the related description may refer to the foregoing, which is not repeated herein.
The embodiment of the disclosure also provides electronic equipment. Fig. 13 is a schematic block diagram of an electronic device in accordance with at least one embodiment of the present disclosure. As shown in fig. 13, the electronic device 50 may include an apparatus 80 or 90 for integrated circuit design as described above. For example, the electronic device may implement the layout adjustment method provided by any of the embodiments of the present disclosure.
In the present disclosure, the term "plurality" refers to two or more, unless explicitly defined otherwise.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This disclosure is intended to cover any adaptations, uses, or adaptations of the disclosure following the general principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It is to be understood that the present disclosure is not limited to the precise arrangements and instrumentalities shown in the drawings, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.
Claims (14)
1. A layout adjustment method for an integrated circuit design, comprising:
acquiring a first layout structure of a clock structure in an integrated circuit, wherein the clock structure comprises a gating clock unit, a driving unit corresponding to the gating clock unit and a plurality of loads;
performing layout adjustment on the first layout structure based on a first distance between the driving unit and the plurality of loads and positions of the plurality of loads in the first layout structure to obtain a second layout structure;
wherein the first distance is a maximum distance between the driving unit and the plurality of loads in the first layout structure;
the layout adjustment method further includes: and executing clock cloning operation based on the second layout structure to obtain a third layout structure.
2. The layout adjustment method according to claim 1, wherein performing layout adjustment on the first layout structure to obtain a second layout structure based on a first distance between the driving unit and the plurality of loads in the first layout structure and positions of the plurality of loads, comprises:
detecting the position of each load in the first layout structure;
Judging whether the positions of the loads meet preset conditions or not based on the first distance;
and if not, adjusting the position of the load which does not meet the preset condition to obtain the second layout structure.
3. The layout adjustment method according to claim 2, wherein obtaining a maximum distance between the driving unit and the plurality of loads in the first layout structure as the first distance includes:
acquiring a second distance between the gating clock unit and the driving unit in the first layout structure;
acquiring a third distance between the gating clock unit and a target load in the first layout structure;
obtaining the maximum distance based on the second distance and the third distance as the first distance,
wherein the target load is a load of the plurality of loads corresponding to the first distance.
4. The layout adjustment method according to claim 3, wherein the first distance is represented by the following expression:
D1＝D2+D3，
wherein D1 represents the first distance, D2 represents the second distance, and D3 represents the third distance.
5. The layout adjustment method according to claim 3, wherein the second distance is represented by the following expression:
D2＝(P+D skw –T stp –D100 ck-q )/σ，
Wherein D2 represents the second distance, P represents the clock period of the clock signal, T stp Representing the setup time of the gated clock unit, D skw D100 represents the clock offset between the gated clock cells and the drive cells ck-q Representing the cell delay of the drive unit, sigma representing the delay per unit line length.
6. The layout adjustment method of claim 3, wherein obtaining a third distance between the gated clock cells and a target load in the first layout structure comprises:
and obtaining the third distance between the gating clock unit and the target load based on clock conversion time, fan-out number of the gating clock unit and clock delay of the target load.
7. The layout adjustment method according to claim 2, wherein the preset condition includes a winding distance of the respective loads being smaller than the first distance.
8. The layout adjustment method according to claim 7, wherein the winding distance of each load is represented by the following expression:
d＝x+y，
where d represents a winding distance of the load, x represents a distance of the load to the driving unit in a first direction, and y represents a distance of the load to the driving unit in a second direction.
9. The layout adjustment method of claim 8, wherein the first direction and the second direction are orthogonal to each other.
10. The layout adjustment method according to any one of claims 1 to 9, further comprising:
obtaining an input netlist of the clock structure in the integrated circuit;
and acquiring the first layout structure based on the input netlist.
11. An apparatus for integrated circuit design, comprising:
an acquisition unit configured to acquire a first layout structure of a clock structure in an integrated circuit, wherein the clock structure includes a gate clock unit, a driving unit corresponding to the gate clock unit, and a plurality of loads;
an adjustment unit configured to perform layout adjustment on the first layout structure based on a first distance between the driving unit and the plurality of loads in the first layout structure and positions of the plurality of loads to obtain a second layout structure;
wherein the first distance is a maximum distance between the driving unit and the plurality of loads in the first layout structure;
the device further comprises a cloning unit configured to perform a clock cloning operation based on the second layout structure, resulting in a third layout structure.
12. An apparatus for integrated circuit design, comprising:
a processor;
a memory including one or more computer program modules;
wherein the one or more computer program modules are stored in the memory and configured to be executed by the processor, the one or more computer program modules comprising instructions for performing the layout adjustment method for integrated circuit design of any of claims 1-10.
13. A non-transitory readable storage medium having stored thereon computer instructions, wherein the computer instructions, when executed by a processor, perform the layout adjustment method for integrated circuit design of any of claims 1-10.
14. An electronic device comprising the apparatus for integrated circuit design of claim 11 or 12.
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| CN112926283B (en) * | 2021-04-09 | 2023-09-15 | 成都海光集成电路设计有限公司 | Layout design method and device for integrated circuit, equipment and storage medium |
| CN113283207B (en) * | 2021-05-24 | 2024-03-01 | 海光信息技术股份有限公司 | Layout analysis method and device for integrated circuit, electronic equipment and storage medium |
| CN113486612B (en) * | 2021-06-29 | 2023-06-06 | 海光信息技术股份有限公司 | Integrated circuit design method, apparatus, electronic device, and readable storage medium |
| CN114896941B (en) * | 2022-07-15 | 2022-10-25 | 飞腾信息技术有限公司 | Layout optimization method, optimization device and related equipment of clock tree |
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