CN112257375A

CN112257375A - Layout adjustment method and device for integrated circuit design and electronic equipment

Info

Publication number: CN112257375A
Application number: CN202011158467.0A
Authority: CN
Inventors: 王慧莉; 袁晓鑫; 王继东; 杜华斌
Original assignee: Haiguang Information Technology Co Ltd
Current assignee: Haiguang Information Technology Suzhou Co ltd
Priority date: 2020-10-26
Filing date: 2020-10-26
Publication date: 2021-01-22
Anticipated expiration: 2040-10-26
Also published as: CN112257375B

Abstract

A layout adjustment method, apparatus, non-transitory readable storage medium, and electronic device for an integrated circuit design. The layout adjustment method for integrated circuit design comprises the following steps: acquiring a first layout structure of a clock structure in an integrated circuit, wherein the clock structure comprises a gate control clock unit, a driving unit corresponding to the gate control clock unit and a plurality of loads; and performing layout adjustment on the first layout structure to obtain a second layout structure based on a first distance between the driving unit and the plurality of loads in the first layout structure and the positions of the plurality of loads. The layout adjusting method can find and solve the time sequence problem of the clock structure cloning in advance by automatically checking the rationality of the integrated circuit layout and adjusting the layout, thereby optimizing the time sequence problem of the clock structure cloning and reducing the power consumption.

Description

Layout adjustment method and device for integrated circuit design and electronic equipment

Technical Field

Embodiments of the present disclosure relate to a layout adjustment method, apparatus, non-transitory readable storage medium, and electronic device for integrated circuit design.

Background

In large scale integrated circuit designs, a single clock source signal drives numerous sequential devices (e.g., registers, latches, memories, etc.). If the sequential device is directly driven by a clock source signal, the driving capability becomes a problem, and the problem of excessive time delay is caused by the excessively long wiring from the clock source to the clock terminal of the register. Therefore, at present, a clock distribution network is usually used to drive the sequential devices, i.e. a buffer or an inverter is inserted between the clock source and the sequential devices to form a clock distribution network. Current clock distribution networks typically employ a clock tree architecture.

Disclosure of Invention

An embodiment of the present disclosure provides a layout adjustment method for an integrated circuit design, including: acquiring a first layout structure of a clock structure in an integrated circuit, wherein the clock structure comprises a gate control clock unit, a driving unit corresponding to the gate control clock unit and a plurality of loads; and performing layout adjustment on the first layout structure to obtain a second layout structure based on a first distance between the driving unit and the plurality of loads in the first layout structure and the positions of the plurality of loads.

For example, in a layout adjustment method provided in at least one embodiment of the present disclosure, performing layout adjustment on the first layout structure to obtain a second layout structure based on a first distance between the driving unit and the plurality of loads in the first layout structure and positions of the plurality of loads includes: acquiring a maximum distance between the driving unit and the plurality of loads in the first layout structure as the first distance; detecting the position of each load in the first layout structure; judging whether the positions of the loads meet preset conditions or not based on the first distance; if not, adjusting the position of the load which does not meet the preset condition to obtain the second layout structure.

For example, in a layout adjustment method provided in at least one embodiment of the present disclosure, acquiring a maximum distance between the driving unit and the plurality of loads in the first layout structure as the first distance includes: acquiring a second distance between the clock gating unit and the driving unit in the first layout structure; acquiring a third distance between the gated clock unit and a target load in the first layout structure; obtaining the maximum distance as the first distance based on the second distance and the third distance, the target load being a load corresponding to the first distance among the plurality of loads.

For example, in a layout adjustment method provided in at least one embodiment of the present disclosure, the first distance is represented by the following expression:

D1＝D2+D3，

wherein D1 represents the first distance, D2 represents the second distance, and D3 represents the third distance.

For example, in a layout adjustment method provided in at least one embodiment of the present disclosure, the second distance is represented by the following expression:

D2＝(P+D_skw–T_stp–D100_ck-q)/σ，

wherein D2 represents the second distance, P represents a clock period of a clock signal, T_stpRepresenting the setup time of said gated clock unit, D_skwRepresenting the clock offset between the gated clock unit and the driving unit, D100_ck-qRepresents the unit delay of the drive unit and sigma represents the time delay of unit line length.

For example, in a layout adjustment method provided in at least one embodiment of the present disclosure, acquiring a third distance between the clock gating cell and a target load in the first layout structure includes: and obtaining the third distance between the clock gating unit and the target load based on the clock conversion time, the fan-out number of the clock gating unit and the clock delay of the target load.

For example, in a layout adjustment method provided in at least one embodiment of the present disclosure, the preset condition includes that a winding distance of each load is smaller than the first distance.

For example, in a layout adjustment method provided in at least one embodiment of the present disclosure, the winding distance of each load is represented by the following expression:

d＝x+y，

wherein d represents a winding distance of a load, x represents a distance of the load to the driving unit in a first direction, and y represents a distance of the load to the driving unit in a second direction.

For example, in a layout adjustment method provided in at least one embodiment of the present disclosure, the first direction and the second direction are orthogonal to each other.

For example, the layout adjustment method provided by at least one embodiment of the present disclosure further includes: and executing clock clone operation based on the second layout structure to obtain a third layout structure.

For example, the layout adjustment method provided by at least one embodiment of the present disclosure further includes: acquiring an input netlist of the clock structure in the integrated circuit; and acquiring the first layout structure based on the input netlist.

Embodiments of the present disclosure also provide an apparatus for integrated circuit design, comprising: an acquisition unit configured to acquire a first layout structure of a clock structure in an integrated circuit, the clock structure including a clock gating cell, a driving unit corresponding to the clock gating cell, and a plurality of loads; an adjusting unit configured to perform layout adjustment on the first layout structure to obtain a second layout structure based on a first distance between the driving unit and the plurality of loads in the first layout structure and positions of the plurality of loads.

For example, an apparatus provided in at least one embodiment of the present disclosure further includes a cloning unit configured to perform a clock cloning operation based on the second layout structure, resulting in a third layout structure.

Embodiments of the present disclosure also provide an apparatus for integrated circuit design, comprising: a processor; a memory including one or more computer program modules; the one or more computer program modules are stored in the memory and configured to be executed by the processor, the one or more computer program modules including instructions for performing the layout adjustment method for an integrated circuit design as described above.

Embodiments of the present disclosure also provide a non-transitory readable storage medium having stored thereon computer instructions that, when executed by a processor, perform a layout adjustment method for an integrated circuit design as described above.

Embodiments of the present disclosure also provide an electronic device including the apparatus for integrated circuit design as described above.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below, and it should be apparent that the drawings described below only relate to some embodiments of the present disclosure and are not limiting on the present disclosure.

FIG. 1A is a schematic diagram of a laid out clock architecture;

FIG. 1B is a schematic diagram of a clock structure after clock cloning based on the laid out clock structure of FIG. 1A;

FIG. 2 is a flow diagram of a layout adjustment method for an integrated circuit design in accordance with at least one embodiment of the present disclosure;

FIG. 3A is a schematic diagram of a first layout structure of a clock structure in accordance with at least one embodiment of the present disclosure;

FIG. 3B is a schematic diagram of a second layout structure of a clock structure in accordance with at least one embodiment of the present disclosure;

fig. 4 is a flowchart of an example operation corresponding to step S102 in fig. 2, in accordance with at least one embodiment of the present disclosure;

FIG. 5 is a simplified schematic diagram of a gating circuit in accordance with at least one embodiment of the present disclosure;

FIG. 6 is a flow chart of another layout adjustment method for an integrated circuit design according to at least one embodiment of the present disclosure;

fig. 7 is a flowchart of an example operation of steps S302 and S303 of fig. 6 provided in accordance with at least one embodiment of the present disclosure;

FIG. 8 is a schematic diagram of an input netlist of a clock structure in accordance with at least one embodiment of the present disclosure;

FIG. 9 is a schematic diagram of a third layout structure of a clock structure in accordance with at least one embodiment of the present disclosure;

fig. 10A is a schematic block diagram of an apparatus for integrated circuit design in accordance with at least one embodiment of the present disclosure;

FIG. 10B is a schematic block diagram of another apparatus for integrated circuit design in accordance with at least one embodiment of the present disclosure;

FIG. 11 is a schematic block diagram of yet another apparatus for integrated circuit design in accordance with at least one embodiment of the present disclosure;

FIG. 12 is a schematic block diagram of a non-transitory readable storage medium in accordance with at least one embodiment of the present disclosure; and

fig. 13 is a schematic block diagram of an electronic device in accordance with at least one embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be described below clearly and completely with reference to the accompanying drawings. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

Clock tree building for high performance chips typically employs cloning techniques. The principle of the clock cloning technology is to determine the number and the positions of the cloned clock units according to the physical positions of the load registers of the layout, wherein the layout is optimized based on the timing relationship paths. For example, FIG. 1A is a schematic diagram of a laid out clock structure. As shown in fig. 1A, clk denotes a clock signal line, 101 denotes a clock gating unit, e.g., a clock gating unit of a top-level clock, 100 denotes a driving unit of a data side of the clock gating unit, i.e., a driving unit corresponding to the

clock gating unit

101, 103 denotes a logic unit on a clock tree other than the clock gating unit, 102, 111 denotes a load, e.g., a load register, and 104 denotes a clock gating unit of a low-side clock gating unit, e.g., a local clock. FIG. 1B is a schematic diagram of a clock structure after clock cloning based on the laid out clock structure of FIG. 1A. Referring to fig. 1A and 1B,

clock gating cells

105 and 108 are cloned clock gating cells corresponding to clock gating cell 101,

logic cells

106 and 109 are cloned logic cells corresponding to logic cell 103,

clock gating cells

107 and 110 are cloned low-side clock gating cells corresponding to clock gating cell 104, and the locations of load registers 102 and 111 remain unchanged.

The above technology has the following difficulties and defects in practical application: before clock cloning, the driving unit 100 and the gated clock unit 101 have a timing check, the load registers 102 and 111 are the loads of the gated clock unit 101, and the layout optimization only considers the factors, while the timing of the cloned units (e.g., the

gated clock units

108 and 105, etc.) is not considered in the layout optimization stage before cloning; because of timing issues due to physical distance, there is a timing check between the cloned gated clock unit 108 and the driver unit 100 after clock cloning; cloning the

units

108, 109, 110 increases power consumption. These problems occur in the middle and late stages of the design affecting project progress; if the clock gating unit 108 is not an integrated unit, it introduces new more difficult timing cross-clocking problems, such as the Setup Time (Setup Time) and Hold Time (Hold Time) conflicting. The setup time refers to the time required for data to settle from unstable to stable before the arrival of a clock acquisition edge, at which the data cannot be stably driven into a sequential device if the setup time is not satisfactory. The hold time is the time to be held after the data is stable, and if the hold time does not meet the requirements, the data cannot be stably driven into the sequential device.

In view of the above problems, a solution generally adopted by those skilled in the art is to repair the discovered timing problem under the cloned clock structure, for example, the timing of the cloned clock gating unit is only checked after the clock tree, and if the timing is difficult to converge, the solution still needs to be returned through the optimized layout operation, but this may result in a later discovered timing problem. If the timing sequence cannot be repaired, the performance of the product is affected, and the power consumption of the integrated circuit is increased.

At least one embodiment of the present disclosure provides a layout adjustment method for an integrated circuit design, including: acquiring a first layout structure of a clock structure in an integrated circuit, wherein the clock structure comprises a gate control clock unit, a driving unit corresponding to the gate control clock unit and a plurality of loads; and performing layout adjustment on the first layout structure to obtain a second layout structure based on a first distance between the driving unit and the plurality of loads in the first layout structure and the positions of the plurality of loads. At least one embodiment of the present disclosure also provides an apparatus, a non-transitory readable storage medium, and an electronic device corresponding to the above layout adjustment method.

According to the layout adjusting method provided by the embodiment of the disclosure, the clock clone operation is executed after the layout is reasonable through automatic detection and automatic layout adjustment, so that the timing sequence problem is found and solved in advance, the project research and development time is shortened, the number of clock clone units is reduced, and the power consumption is reduced.

In the following, a layout adjustment method provided according to at least one embodiment of the present disclosure is described in a non-limiting manner by using several examples or embodiments, and as described below, different features in these specific examples or embodiments may be combined with each other without mutual conflict, so as to obtain new examples or embodiments, and these new examples or embodiments also belong to the protection scope of the present disclosure.

Fig. 2 is a flowchart of a layout adjustment method for an integrated circuit design according to at least one embodiment of the present disclosure.

For example, in at least one embodiment of the present disclosure, as shown in fig. 2, a layout adjustment method 10 for an integrated circuit design may include the steps of:

step S101: acquiring a first layout structure of a clock structure in an integrated circuit, wherein the clock structure comprises a gate control clock unit, a driving unit corresponding to the gate control clock unit and a plurality of loads;

step S102: and performing layout adjustment on the first layout structure to obtain a second layout structure based on a first distance between the driving unit and the plurality of loads in the first layout structure and the positions of the plurality of loads.

The layout adjustment method 10 for an integrated circuit design according to the embodiment of the present disclosure adds a layout adjustment for optimizing clock cloning after the conventional layout optimization, that is, adjusts from a first layout structure to a second layout structure, thereby finding and solving the timing problem in advance, reducing the number of clock cloning units, and reducing the clock power consumption.

Fig. 3A is a schematic diagram of a first layout structure of a clock structure provided in at least one embodiment of the present disclosure, fig. 3B is a schematic diagram of a second layout structure of a clock structure provided in at least one embodiment of the present disclosure, and fig. 4 is an exemplary operation flowchart corresponding to step S102 in fig. 2 according to at least one embodiment of the present disclosure.

For step S101, the obtained first layout structure refers to a clock structure after layout (e.g., after conventional layout optimization). As shown in fig. 3A, the first layout structure includes a clock gating unit 101 of a clock structure, a driving unit 100 corresponding to the clock gating unit 101, a low-side clock gating unit 104,

logic units

130 and 103 other than the clock gating unit, and a plurality of load registers 102 and 111.

For example, referring to fig. 4, in at least one embodiment of the present disclosure, for step S102, performing layout adjustment on the first layout structure to obtain the second layout structure based on the first distance between the driving unit and the plurality of loads and the positions of the plurality of loads in the first layout structure may include the following steps S201 to S204.

Step S201: acquiring a maximum distance between a driving unit and a plurality of loads in a first layout structure as a first distance;

step S202: detecting the position of each load in the first layout structure;

step S203: judging whether the position of each load meets a preset condition or not based on the first distance;

step S204: if not, adjusting the position of the load which does not meet the preset condition to obtain a second layout structure.

For example, in at least one embodiment of the present disclosure, for step S201, acquiring a maximum distance between the driving unit and the plurality of loads in the first layout structure as the first distance includes: acquiring a second distance between a gating clock unit and a driving unit in the first layout structure; acquiring a third distance between a gated clock unit and a target load in the first layout structure; the maximum distance is obtained as the first distance based on the second distance and the third distance. For example, the target load is a load corresponding to the first distance among the plurality of loads.

For example, in at least one embodiment of the present disclosure, a method for obtaining the first distance D1 is described in detail below by taking the first layout structure shown in fig. 3A as an example.

For example, as shown in fig. 3A, it is assumed that the target load determined based on the obtained first distance D1 (e.g., D1 calculated by the following method) is the load register 111 located at the position (x2, y2) in fig. 3A, in which case, the second distance D2 refers to the distance between the clock gating cell 101 and the driving unit 100, and the third distance D3 refers to the distance between the clock gating cell 101 and the target load (e.g., the load register 111 located at the position (x2, y 2)). Fig. 3A shows a horizontal coordinate axis X and a vertical coordinate axis Y with the position (X0, Y0) of the driving unit 100 as the origin of coordinates, and in this coordinate system, it is assumed that the position of the gate clock unit 101 is (X1, Y1), the position of the target load is (X2, Y2), and the position of some other load register 111 is (X3, Y3), as shown in fig. 3A.

It is to be noted that, in the embodiment of the present disclosure, the target load is a load corresponding to the first distance D1 among the plurality of loads in the first layout structure. For example, the first distance D1 is first obtained by the method described below, and then a target load among the plurality of loads may be determined from the first distance D1. Therefore, the target load is not necessarily the load register 111 with the position (x2, y2) shown in fig. 3A, but may be other load registers, which is determined according to practical situations, and the embodiment of the present disclosure is not limited in this respect.

For example, in one example, first, the second distance D2 and the third distance D3 in the first layout structure are calculated, respectively, and then the maximum distance is obtained as the first distance D1 based on the second distance D2 and the third distance D3.

It is to be noted that, in the embodiment of the present disclosure, the first distance D1, the second distance D2, and the third distance D3 are not straight-line distances between specific logic units, but are calculated by the following various expressions.

For example, in at least one embodiment of the present disclosure, the second distance may be represented by the following expression (1):

D2＝(P+D_skw–T_stp–D100_ck-q)/σ (1)

where D2 denotes the second distance, P denotes the clock period of the clock signal clk, T_stpRepresenting the setup time, D, of the gated clock unit 101_skwRepresenting the clock skew between the gated clock unit 101 and the drive unit 100, D100_ck-qDenotes the unit delay of the driving unit 100, i.e., the delay of the ck to q terminals of the driving unit 100, and σ denotes the time delay of the unit line length.

The calculation method of the second distance (i.e., the second distance D2 between the clock gating cell 101 and the driving cell 100) is explained in detail below with reference to fig. 5.

Fig. 5 is a schematic diagram of a gating circuit according to at least one embodiment of the present disclosure.

Referring to fig. 5, in the gating circuit, the timing requirements of the clock gating unit 101 are: the data arrival time of the clock gating cell 101 is less than or equal to the data required time of the clock gating cell 101.

The data arrival time of the clock gating cell 101 may be expressed as: d120+ D100_ck-q+D130；

The clock gating cell 101 data demand time may be expressed as: p + D121-D101_stp；

According to the above timing requirements, it is possible to obtain:

D120+D100_ck-q+D130<＝P+D121-D101_stp

D130<＝P+D121–D101_stp-D120–D100_ck-q

D2*σ<＝P+D121–D101_stp-D120–D100_ck-q

D2<＝(P+D121-D120–D101_stp–D100_ck-q)/σ

D2<＝(P+D_skw–D101_stp–D100_ck-q)/σ

where D120 denotes the clock delay of the driving unit 100 and D121 denotes the clock delay of the gated clock unit 101, i.e. D in expression (1) above_skw＝(D121-D120)，D100_ck-qDenotes the unit delay of the driving unit 100, i.e. the delay from ck to q, D130 denotes the path delay of the data side of the gated clock unit 101, P is the clock period of the gated clock unit 101, D101_stpRepresenting the data setup time of the gated clock unit 101, i.e., T in expression (1) above_stp＝D101_stpAnd σ represents the delay per line length.

It should be noted that the value of the delay σ of the unit line length is related to the actually adopted process and the logic depth on the path of the technician, and the specific value of σ is not limited in the embodiment of the present disclosure and may be set according to the actual situation.

For example, in at least one embodiment of the present disclosure, as shown in fig. 3A, obtaining the third distance D3 between the gated clock cell 101 and the target load in the first layout structure includes: the third distance D3 between the clock gating cell 101 and the target load is derived based on the clock transition time, the number of fan-outs of the clock gating cell 101, and the clock delay of the target load.

It should be noted that the third distance D3 is determined empirically according to actual design requirements or design objectives, and the embodiment of the present disclosure is not limited thereto.

For example, in at least one embodiment of the present disclosure, based on the above-described second distance D2 and third distance D3, the maximum distance may be obtained as the first distance D1.

For example, in at least one embodiment of the present disclosure, it is represented by the following expression:

D1＝D2+D3，

where D1 denotes the first distance, D2 denotes the second distance, and D3 denotes the third distance.

For step S202, the positions of the respective loads in the first layout structure are detected.

For example, in at least one embodiment of the present disclosure, as shown in fig. 3A, the position of some other load register 111 is (x3, y 3). Also, the position of other load registers 102 may be detected or scanned, and the specific detection method of the embodiments of the present disclosure is not limited, and a conventional detection method may be adopted.

With respect to step S203, it is determined whether the position of each load satisfies a preset condition based on the first distance.

For example, in at least one embodiment of the present disclosure, the preset condition may be that the winding distance of each load is less than the first distance.

For example, in at least one embodiment of the present disclosure, the winding distance of each load is represented by the following expression:

d＝x+y，

where d denotes a winding distance of the load, x denotes a distance of the load to the driving unit in the first direction, and y denotes a distance of the load to the driving unit in the second direction.

For example, in one example, the first direction and the second direction are orthogonal to each other.

For example, referring to fig. 3A, based on the X and Y coordinate axes shown in fig. 3A, a load register 111 is located at (X3, Y3), the first direction is along the horizontal coordinate axis X, the second direction is along the vertical coordinate axis Y, and the winding distance d of the load register 111 is | X3| + | Y3 |.

For example, for the first layout structure shown in fig. 3A, it is determined whether the routing distance D of each load register (e.g., load registers 111, 102, etc.) is less than the first distance D1.

It should be noted that the preset condition may be set according to actual situations, and the embodiment of the present disclosure is not particularly limited to this.

For step S204, if not, the position of the load not meeting the preset condition is adjusted to obtain the second layout structure.

For example, referring to fig. 3A, if the position of a certain load in the first layout structure shown in fig. 3A does not satisfy the preset condition, for example, the winding distance D of the load is greater than or equal to the first distance D1 in the above embodiment, the position of the load that does not satisfy the preset condition is adjusted in a targeted manner (for example, left shift, right shift, etc. are performed according to the timing property, physical property, etc. of the corresponding load register) until it is determined that the positions of all loads in the first layout structure satisfy the preset condition, so as to obtain the second layout structure, for example, the second layout structure shown in fig. 3B is obtained.

It should be noted that the embodiment of the present disclosure does not limit the specific operation of adjusting the position of the load, and a conventional position adjusting operation may be adopted.

For ease of understanding, the layout adjustment method 10 provided by the embodiments of the present disclosure is further explained in conjunction with fig. 5 and 3A. For example, in one example, it is assumed that in the first layout structure, the position of the driving unit 100 is (x0, y0) ═ 0, the position of the clock gating unit 101 is (x1, y1) ═ 50,40, and a certain load register 111 is located at the position (x3, y3), where (x3, y3) ═ 280,200.

As described above, to calculate the first distance D1, the second distance D2 and the third distance D3 are first calculated.

1) Calculating the second distance D2:

for example, assume that the clock delay D120 of the driving unit 100 is 60ps (picosecond), the clock delay D121 of the clock gating unit 101 is 2ps, and the delay D100 of the ck to q terminals of the driving unit 100_ck-qThe data setup time D101 of the clock gating unit 101 is 30ps_stp15ps, the clock period P of the clock gating cell 101 is 300ps, and σ is 0.5 in the case where the logic depth of the cell data path of the clock gating cell 101 is 10 levels using a 7nm (nanometer) process.

Therefore, with the above expression (1) for the second distance D2 (i.e., the distance between the clock gating cell 101 and the driving cell 100), it is possible to obtain:

D2＝(P+D121–D101_stp-D120–D100_ck-q)/σ。

for example, D2 ═ (300+2-15-60-30)/0.5 ═ 394 μm

2) Calculating the third distance D3:

for example, according to an actual design objective or design requirement, the clock transition time is 30ps, the fan-out (fanout) of the gated clock unit 101 is 40, and the clock delay of the target load is 60ps, so that the distance between the target load and the gated clock unit 101 is 50 μm (micrometer).

3) Calculating the first distance D1:

D1＝D2+D3。

for example, D1 ═ 394+50 ═ 444 μm.

For example, in one example, according to the first distance D1 obtained by the above calculation method, it may be determined that the target load is the load register 111 located at the position (x2, y2) in the first layout structure shown in fig. 3A.

Next, the position of each load in the first layout structure is detected or scanned, and whether the position of each load satisfies, for example, the winding distance D < D1 is determined.

For example, in this example, the position of a certain load register 111 is (x3, y3), (x3, y3) is (280,200), the winding distance d of the load register 111 at (x3, y3) is 280+200 is 480 μm, and it is seen that the load register 111 does not satisfy the preset condition, the position of the load register 111 is adjusted in a targeted manner. For example, by grabbing the timing check attribute of the load register 111, shifting left along the horizontal by 36 μm, etc., embodiments of the present disclosure do not limit the position adjustment operation. And obtaining a second layout structure until the positions of all the loads in the first layout structure are determined to meet the preset condition.

Fig. 6 is another layout adjustment method for an integrated circuit design according to at least one embodiment of the present disclosure, fig. 7 is a flowchart illustrating exemplary operations of steps S302 and S303 in fig. 6 according to at least one embodiment of the present disclosure, fig. 8 is a schematic diagram illustrating an input netlist of a clock structure according to at least one embodiment of the present disclosure, and fig. 9 is a schematic diagram illustrating a third layout structure of a clock structure according to at least one embodiment of the present disclosure.

For example, at least one embodiment of the present disclosure provides another layout adjustment method 30 for an integrated circuit design. The layout adjustment method 30 includes steps S301 to S303. The layout adjustment method 30 shown in fig. 6 additionally includes step S301 and step S303, compared to the layout adjustment method 10 shown in fig. 2.

For example, in step S301, an input netlist of a clock structure in an integrated circuit is obtained, and a first layout structure is obtained based on the input netlist. That is, the input netlist of the clock structure is laid out. For example, in one example, the input netlist is used to represent the clock structure in the original integrated circuit, as shown in FIG. 8, the input netlist includes the logical relationships between the logic cells of the integrated circuit design, but does not include layout information. The first layout structure is obtained by performing layout optimization on the input netlist, as shown in fig. 3A.

It should be noted that the first layout structure is a result of performing conventional layout optimization on the input netlist of the clock structure. The conventional layout optimization is not described in detail in the embodiments of the present disclosure, and reference may be made to relevant documents.

In step S302, a layout adjustment for optimizing clock cloning is performed, that is, a layout adjustment from a first layout structure (see fig. 3A) to a second layout structure (see fig. 3B), and the specific operation of step S302 may refer to the specific description of the layout adjustment method 10, which is not described herein again.

In step S303, a clock clone operation is performed based on the second layout structure to obtain a third layout structure.

For example, in at least one embodiment of the present disclosure, based on the second layout structure as shown in fig. 3B, a third layout structure as shown in fig. 9 may be obtained. Referring to fig. 9, clone 105 corresponds to clock gating unit 101 and clone 107 corresponds to low-side clock gating unit 104.

For example, referring to fig. 7, in at least one embodiment of the present disclosure, in step S401, the maximum distance between the driving unit and the load registers in the first layout structure is calculated by the above-described method, in step S402, the positions of all the load registers in the first layout structure are detected, in step S403, it is determined whether the position of each load register needs to be adjusted, for example, by determining whether the position of each load register meets a specific preset condition, and if each load register meets, step S405 is executed, and a clock cloning operation is executed based on the current layout structure; if the load registers do not meet the requirement, step S404 is executed, the position of the load registers not meeting the requirement is adjusted, and then the process returns to the judgment step S403 to judge until the positions of all the load registers meet the requirement, and no readjustment is needed, step S405 is executed to clone the clock.

Comparing the clone clock structure (fig. 9) after the

layout adjustment method

10 or 30 of the present disclosure with the clone clock structure (fig. 1B) after cloning based on the laid-out clock structure shown in fig. 1A, it can be seen that the cloning of the

clone units

108, 109, and 110 in fig. 1B can be avoided by the

layout adjustment method

10 or 30 provided in the embodiment of the present disclosure, so as to reduce power consumption, and also avoid the timing problem of the gated clock unit 108 due to physical distance, and improve clock performance.

The

layout adjustment methods

10 and 30 provided by the embodiments of the present disclosure may be applied to clock cloning of all structures, and by calculating the maximum distance between the driving unit of the gate control circuit and the load register, checking the physical positions of all registers and optimizing the layout of the load register, finding and solving timing problems in advance, improving product performance, shortening project development time, reducing clock cloning units, reducing power consumption, and optimizing EDA (electronic design automation) tools, before performing clock cloning operations.

It should be noted that, in the embodiments of the present disclosure, the execution order of the steps of the layout adjustment method is not limited, and although the execution process of the steps is described in a specific order, this does not limit the embodiments of the present disclosure. The various steps in the layout adjustment method may be performed in series or in parallel, which may depend on the actual requirements. The video processing method may also include more or fewer steps, and embodiments of the present disclosure are not limited in this respect.

Fig. 10A is a schematic block diagram of an apparatus for integrated circuit design in accordance with at least one embodiment of the present disclosure, and fig. 10B is a schematic block diagram of another apparatus for integrated circuit design in accordance with at least one embodiment of the present disclosure.

Embodiments of the present disclosure also provide an apparatus for integrated circuit design, as shown in fig. 10A, the apparatus 80 for integrated circuit design includes an obtaining unit 801 and an adjusting unit 802.

The acquisition unit 801 is configured to acquire a first layout structure of a clock structure in an integrated circuit. For example, a clock structure includes a gated clock unit, a driving unit corresponding to the gated clock unit, and a plurality of loads. For example, the obtaining unit 801 may implement step S101, and a specific implementation method thereof may refer to the related description of step S101, which is not described herein again.

The adjusting unit 802 is configured to perform layout adjustment on the first layout structure to obtain a second layout structure based on a first distance between the driving unit and the plurality of loads in the first layout structure and positions of the plurality of loads. For example, the adjusting unit 802 may implement step S102, and the specific implementation method thereof may refer to the related description of step S102, which is not described herein again.

For example, in at least one embodiment of the present disclosure, as shown in fig. 10B, the apparatus 80 further includes a cloning unit 803 on the basis of the example shown in fig. 10A. The cloning unit 803 is configured to perform a clock cloning operation based on the second layout structure resulting in a third layout structure.

For example, the specific operations that the obtaining unit 801, the adjusting unit 802, and the cloning unit 803 are configured to perform may all be referred to the above description related to the

layout adjusting methods

10 and 30 provided in at least one embodiment of the present disclosure, and are not described herein again.

It should be noted that the obtaining unit 801, the adjusting unit 802, and the cloning unit 803 may be implemented by software, hardware, firmware, or any combination thereof, for example, they may be implemented as the obtaining circuit 801, the adjusting circuit 802, and the cloning circuit 803, respectively, and the embodiments of the present disclosure do not limit their specific implementation.

It should be understood that the apparatus 80 for integrated circuit design provided in the embodiment of the present disclosure may implement the foregoing

layout adjustment methods

10 and 30, and also achieve similar technical effects to the foregoing

layout adjustment methods

10 and 30, which are not described herein again.

It should be noted that, in the embodiments of the present disclosure, the apparatus for integrated circuit design may include more or less circuits or units, and the connection relationship between the respective circuits or units is not limited and may be determined according to actual requirements. The specific configuration of each circuit is not limited, and may be configured by an analog device, a digital chip, or other suitable configurations according to the circuit principle.

Embodiments of the present disclosure also provide an apparatus for integrated circuit design. Fig. 11 is a schematic block diagram of another apparatus for integrated circuit design in accordance with at least one embodiment of the present disclosure. As shown in fig. 11, the apparatus 90 includes a processor 910 and a memory 920. Memory 920 includes one or more computer program modules 921. One or more computer program modules 921 are stored in the memory 920 and configured to be executed by the processor 910, the one or more computer program modules 921 including instructions for performing the

layout adjustment method

10 or 30 provided by at least one embodiment of the present disclosure, which when executed by the processor 910, may perform one or more steps of the

layout adjustment method

10 or 30 provided by at least one embodiment of the present disclosure. The memory 920 and the processor 910 may be interconnected by a bus system and/or other form of connection mechanism (not shown).

For example, the processor 910 may be a Central Processing Unit (CPU), a Digital Signal Processor (DSP), or other form of processing unit having data processing capabilities and/or program execution capabilities, such as a Field Programmable Gate Array (FPGA), or the like; for example, the Central Processing Unit (CPU) may be an X86 or ARM architecture or the like. The processor 910 may be a general-purpose processor or a special-purpose processor that may control other components in the apparatus 90 to perform desired functions.

For example, memory 920 may include any combination of one or more computer program products that may include various forms of computer-readable storage media, such as volatile memory and/or non-volatile memory. Volatile memory can include, for example, Random Access Memory (RAM), cache memory (or the like). The non-volatile memory may include, for example, Read Only Memory (ROM), a hard disk, an Erasable Programmable Read Only Memory (EPROM), a portable compact disc read only memory (CD-ROM), USB memory, flash memory, and the like. One or more computer program modules 921 may be stored on the computer-readable storage medium, and processor 910 may execute one or more computer program modules 921 to implement various functions of apparatus 90. Various applications and various data, as well as various data used and/or generated by the applications, and the like, may also be stored in the computer-readable storage medium. The detailed functions and technical effects of the apparatus 90 can be referred to the above description of the layout adjustment method, and are not described herein again.

Embodiments of the present disclosure also provide a non-transitory readable storage medium. Fig. 12 is a schematic block diagram of a non-transitory readable storage medium in accordance with at least one embodiment of the present disclosure. As shown in FIG. 12, the non-transitory readable storage medium 100 has stored thereon computer instructions 111, which computer instructions 111, when executed by a processor, perform one or more steps of the

layout adjustment method

10 or 30 for an integrated circuit design as described above.

For example, the non-transitory readable storage medium 100 may be any combination of one or more computer readable storage media, such as one containing computer readable program code for obtaining a first layout structure of a clock structure in an integrated circuit, and another containing computer readable program code for performing layout adjustment on the first layout structure to obtain a second layout structure based on a first distance between a driver unit and a plurality of loads in the first layout structure and positions of the plurality of loads. Of course, the above program codes may also be stored in the same computer readable medium, and the embodiments of the disclosure are not limited thereto. For example, when the program code is read by a computer, the computer may execute the program code stored in the computer storage medium, performing a layout adjustment method such as that provided by any of the embodiments of the present disclosure.

For example, the storage medium may include a memory card of a smart phone, a storage component of a tablet computer, a hard disk of a personal computer, a Random Access Memory (RAM), a Read Only Memory (ROM), an Erasable Programmable Read Only Memory (EPROM), a portable compact disc read only memory (CD-ROM), a flash memory, or any combination of the above, as well as other suitable storage media. For example, the readable storage medium may also be the memory 920 in fig. 11, and reference may be made to the foregoing for related description, which is not described herein again.

The embodiment of the disclosure also provides an electronic device. Fig. 13 is a schematic block diagram of an electronic device in accordance with at least one embodiment of the present disclosure. As shown in fig. 13, the electronic device 50 may include an

apparatus

80 or 90 for integrated circuit design as described above. For example, the electronic device may implement the layout adjustment method provided in any of the embodiments of the present disclosure.

In the present disclosure, the term "plurality" means two or more unless explicitly defined otherwise.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

It will be understood that the present disclosure is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A layout adjustment method for an integrated circuit design, comprising:

acquiring a first layout structure of a clock structure in an integrated circuit, wherein the clock structure comprises a gate control clock unit, a driving unit corresponding to the gate control clock unit and a plurality of loads;

and performing layout adjustment on the first layout structure to obtain a second layout structure based on a first distance between the driving unit and the plurality of loads in the first layout structure and the positions of the plurality of loads.

2. The layout adjustment method according to claim 1, wherein performing layout adjustment on the first layout structure to obtain a second layout structure based on a first distance between the driving unit and the plurality of loads in the first layout structure and positions of the plurality of loads comprises:

acquiring a maximum distance between the driving unit and the plurality of loads in the first layout structure as the first distance;

detecting the position of each load in the first layout structure;

judging whether the positions of the loads meet preset conditions or not based on the first distance;

if not, adjusting the position of the load which does not meet the preset condition to obtain the second layout structure.

3. The layout adjustment method according to claim 2, wherein acquiring, as the first distance, a maximum distance between the drive unit and the plurality of loads in the first layout structure includes:

acquiring a second distance between the clock gating unit and the driving unit in the first layout structure;

acquiring a third distance between the gated clock unit and a target load in the first layout structure;

obtaining the maximum distance as the first distance based on the second distance and the third distance,

wherein the target load is a load corresponding to the first distance among the plurality of loads.

4. The layout adjustment method according to claim 3, wherein the first distance is represented by the following expression:

D1＝D2+D3，

5. The layout adjustment method according to claim 3, wherein the second distance is represented by the following expression:

D2＝(P+D_skw–T_stp–D100_ck-q)/σ，

wherein D2 represents the second distance and P represents a clock signalClock period of number, T_stpRepresenting the setup time of said gated clock unit, D_skwRepresenting the clock offset between the gated clock unit and the driving unit, D100_ck-qRepresents the unit delay of the drive unit and sigma represents the time delay of unit line length.

6. The layout adjustment method of claim 3 wherein obtaining a third distance between the clock-gated cell and a target load in the first layout structure comprises:

and obtaining the third distance between the clock gating unit and the target load based on the clock conversion time, the fan-out number of the clock gating unit and the clock delay of the target load.

7. The layout adjustment method according to claim 2, wherein the preset condition includes that a winding distance of the respective loads is smaller than the first distance.

8. The layout adjustment method according to claim 7, wherein the winding distance of each load is represented by the following expression:

d＝x+y，

9. The layout adjustment method according to claim 8, wherein the first direction and the second direction are orthogonal to each other.

10. The layout adjustment method according to any one of claims 1 to 9, further comprising:

and executing clock clone operation based on the second layout structure to obtain a third layout structure.

11. The layout adjustment method according to any one of claims 1 to 9, further comprising:

acquiring an input netlist of the clock structure in the integrated circuit;

and acquiring the first layout structure based on the input netlist.

12. An apparatus for integrated circuit design, comprising:

an acquisition unit configured to acquire a first layout structure of a clock structure in an integrated circuit, wherein the clock structure includes a clock gating unit, a driving unit corresponding to the clock gating unit, and a plurality of loads;

an adjusting unit configured to perform layout adjustment on the first layout structure to obtain a second layout structure based on a first distance between the driving unit and the plurality of loads in the first layout structure and positions of the plurality of loads.

13. The apparatus of claim 12, further comprising a cloning unit configured to perform a clock cloning operation based on the second layout structure resulting in a third layout structure.

14. An apparatus for integrated circuit design, comprising:

a processor;

a memory including one or more computer program modules;

wherein the one or more computer program modules are stored in the memory and configured to be executed by the processor, the one or more computer program modules comprising instructions for performing the layout adjustment method for an integrated circuit design of any of claims 1-11.

15. A non-transitory readable storage medium having stored thereon computer instructions, wherein the computer instructions, when executed by a processor, perform the layout adjustment method for an integrated circuit design of any of claims 1-11.

16. An electronic device comprising the apparatus for integrated circuit design of any of claims 12-14.