CN114167264A - Device for detecting digital circuit holding time violation in nuclear radiation environment - Google Patents
Device for detecting digital circuit holding time violation in nuclear radiation environment Download PDFInfo
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- 238000001514 detection method Methods 0.000 claims abstract description 76
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31725—Timing aspects, e.g. clock distribution, skew, propagation delay
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E30/00—Energy generation of nuclear origin
- Y02E30/30—Nuclear fission reactors
Abstract
The invention discloses a device for detecting the violation of digital circuit holding time in nuclear radiation environment, which comprises more than two detection circuit modules connected in sequence, wherein each detection circuit module comprises a trigger unit, a buffer unit and a multiplexer unit, the buffer unit comprises a plurality of buffer branches with different stages, the multiplexer unit is respectively connected with each buffer branch, a control end of the multiplexer unit inputs a selection signal to control and select different buffer branches, a clock signal input end of the trigger unit is connected with an input end of the buffer unit to access a clock signal, an output end of a previous trigger unit is connected with an input end of a next trigger unit, and an output end of a last trigger unit outputs a final detection result. The invention can detect whether the digital circuit working in the nuclear radiation environment has the holding time violation or not, and has the advantages of simple and compact structure, low cost, high detection efficiency and precision and the like.
Description
Technical Field
The invention relates to the technical field of circuit detection in a nuclear radiation environment, in particular to a device for detecting a digital circuit holding time violation in the nuclear radiation environment.
Background
Scenes such as powerful radiation planetary detection like Jupiter and the like, nuclear leakage accident treatment, electronic monitoring of large-scale hadron colliders and nuclear fusion devices and the like all need digital circuits capable of normally working in a nuclear radiation environment. The nuclear radiation environment can affect the normal operation of electronic components, so that the research on the electronic components resistant to high-dose radiation has great significance for nuclear crisis such as nuclear leakage.
The problem of time sequence violation of a digital circuit in a nuclear radiation environment is a big difficulty in the current research and development of radiation-resistant electronic components. Most of the present large-scale digital integrated circuits such as Central Processing Units (CPUs), Digital Signal Processors (DSPs), etc. are synchronous circuits, as shown in fig. 1, and include flip-flops (UFF0 and UFF1), Combinational logic (combinatorial logic), and a clock tree, where the setup time requirement can be described by equation (1), and the hold time requirement can be described by equation (2):
Tlauch+Tck2q+Tdp<Tcapture+Tcycle-Tsetup (1)
Tlauch+Tck2q+Tdp>Tcapture+Thold (2)
wherein, TlaunchIs the delay of the transmission clock, Tck2qIs the delay from the clock terminal (CK) to the output terminal (Q) of the transmission flip-flop, TdpIs a delay of combinational logic, TcaptureIs a fishingObtaining a time delay of the clock, TcycleIs the clock period, TsetupIs the setup time of the capture flip-flop (T)holdIs the hold time of the capture trigger.
If the formula (2) is satisfied, the retention time constraint is satisfied, the circuit can work normally, and if the formula (2) is not satisfied, the retention time is violated, and the working state of the circuit is abnormal. The synchronous circuit works under the driving of a clock, and the requirements of establishing time sequence constraint and maintaining the time sequence constraint are met, otherwise, the circuit has functional failure. Establishing time sequence constraint requires that data transmitted by a launch flip-flop (launch flip-flop) is stably established within a period of time before a capture clock (lags a clock period compared with a transmission clock) reaches a capture flip-flop after the delay of a combinational logic (combinational logic) so as to be correctly sampled by the capture clock; otherwise the capture clock will not sample the correct data and a functional error will occur. As can be seen from the formula (1) setup time requirement expression, the radiation causes delay change of the circuit, thereby causing setup time violation. For example, if the cumulative radiation increases TdpIf the left side of the equation (1) is larger than the right side, the setup time will be violated and eventually a functional error will occur, and such a functional error can be caused by increasing TcycleThe mode of (i.e., down-conversion).
The hold time timing constraint requires that data transmitted by a launch flip-flop (launch flip-flop) can be kept stable for a period of time after the same beat clock reaches a capture flip-flop after a period of time delay of combinatorial logic (combinatorial logic), as described in equation (2). I.e. the radiation will cause the delay of the circuit to change, causing a hold time violation. For example, cumulative radiation increases TcaptureMaking the right side of equation (2) larger than the left side, in this case the hold time is violated, eventually resulting in a functional error of the circuit. However, because the holdover time timing constraint is independent of the clock cycle, holdover time violations cannot be resolved by down-clocking, and thus the hazard of the holdover time violations is greater than the setup time violationsAmong many reliability problems caused by radiation, the retention time violation is caused by a "hard error" and is not recoverable by a power-off restart, so the detection of the retention time violation is a problem to be solved at present.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: aiming at the technical problems in the prior art, the invention provides the device for detecting the hold time violation of the digital circuit in the nuclear radiation environment, which has the advantages of simple and compact structure, low cost and high detection efficiency and precision, and can detect whether the hold time violation occurs in the digital circuit working in the nuclear radiation environment.
In order to solve the technical problems, the technical scheme provided by the invention is as follows:
a device for detecting the violation of digital circuit holding time in nuclear radiation environment is characterized by comprising more than two detection circuit modules which are connected in sequence, the detection circuit module comprises a trigger unit, a buffer unit and a multiplexer unit, the buffer unit comprises a plurality of buffer branches with different stages, the multiplexer unit is respectively connected with each buffer branch, the control terminal of the multiplexer unit inputs a selection signal S to control the selection of the buffer branch, the clock signal input end of the trigger unit is connected with the input end of the buffer unit for accessing a clock signal CLK, the output end of the trigger unit in the last detection circuit module is connected with the input end of the trigger unit in the next detection circuit module, and the output end of the trigger unit in the last detection circuit module outputs a final detection result.
Furthermore, by adjusting the selection signal S input by each multiplexer unit, different buffer branches are controlled and selected, so as to control and change the delay of the path between the clock signal CLK accessed by the buffer unit and the output clock signal CLKOUT.
And further, judging whether the holding time violation occurs according to the waveform state of the final detection result.
Further, the output end of the trigger unit is also provided with an inverter.
Furthermore, the SET ends of the flip-flop units in each of the detection circuit modules are connected to access a unified SET signal SET.
Further, the output end of the flip-flop unit in the last detection circuit module is also connected to the input end of the flip-flop unit in the first detection circuit module.
Further, the number of the detection circuit modules is even.
Further, the trigger unit is a D trigger.
Compared with the prior art, the invention has the advantages that: according to the invention, the delay of the capture clock is changed, the retention time timing constraint allowance is controlled, and the sensitivity of the detection circuit module to the retention time violation in the nuclear radiation environment is further controlled, so that the trigger unit can normally latch data under the condition that the retention time timing constraint is satisfied; and when the holding time is violated, the trigger unit can not normally latch data any more, so that whether the holding time is violated or not is judged according to the output final detection result, and the detection of the holding time violation in the nuclear radiation environment is realized.
Drawings
Fig. 1 is a schematic diagram of a typical digital circuit configuration.
Fig. 2 is a schematic structural diagram of an apparatus for detecting a hold time violation of a digital circuit in a nuclear radiation environment in the present embodiment.
Fig. 3 is a schematic structural diagram of a circuit module in this embodiment.
FIG. 4 is a diagram illustrating the results of detecting that a hold time violation has not occurred in a circuit in a specific application embodiment.
FIG. 5 is a diagram illustrating the results of detecting a hold time violation in a circuit in an exemplary embodiment.
Illustration of the drawings: 1. a detection circuit module; 11. a trigger unit; 12. a buffer unit; 13. a multiplexer unit; 14. an inverter.
Detailed Description
The invention is further described below with reference to the drawings and specific preferred embodiments of the description, without thereby limiting the scope of protection of the invention.
As shown in fig. 1, the apparatus for detecting a hold time violation of a digital circuit in a nuclear radiation environment of this embodiment includes more than two sequentially connected detection circuit modules 1, the detection circuit modules 1 include flip-flop units 11, the buffer unit 12 includes a plurality of buffer branches with different stages, the multiplexer unit 13 is connected to each buffer branch, a control terminal of the multiplexer unit 13 inputs a selection signal S to control the selection of the buffer branch, a clock signal input terminal of the flip-flop unit 11 is connected to an input terminal of the buffer unit 12 for receiving a clock signal CLK, an output terminal of the flip-flop unit 11 in the previous detection circuit module 1 is connected to an input terminal of the flip-flop unit 11 in the next detection circuit module 1, and an output terminal of the flip-flop unit 11 in the last detection circuit module 1 outputs a final detection result.
In the embodiment, by changing the delay of the capture clock, that is, Tcapture in the formula (2), the retention time timing constraint margin is controlled, and then the sensitivity of the detection circuit module 1 to the retention time violation in the nuclear radiation environment is controlled, so that the flip-flop unit 11 can normally latch data under the condition that the retention time timing constraint is satisfied; when the hold time is violated, the flip-flop unit 11 can no longer latch data normally, and thus, whether the hold time is violated is determined according to the output final detection result, and the detection of the hold time violation in the nuclear radiation environment can be realized accurately and efficiently.
The present embodiment specifically determines whether the hold time violation occurs according to the waveform state of the final detection result, that is, if the signal duty cycle of the final detection result matches the preset value, it is determined that the hold time violation does not occur, and if the signal duty cycle of the final detection result does not match the preset value, it is determined that the hold time violation occurs.
In this embodiment, the selection signal S input by each multiplexer unit 13 is adjusted to control and select different buffer branches, so as to control and change the delay of the path between the clock signal CLK and the output clock signal CLKOUT that are accessed by the buffer unit 2. Each buffer branch corresponds to a buffer with different stages, and the buffers with different stages can be controlled and selected through the selection signal S, so that the delay of changing the path from CLK to CLKOUT can be controlled.
In this embodiment, the output end of the flip-flop unit 11 is further provided with a phase inverter 14, and the flip-flop unit 11 in the previous detection circuit module 1 is connected to the input end of the flip-flop unit 11 in the next detection circuit module 1 through the phase inverter 14, so that the output signal of the flip-flop unit 11 in the previous detection circuit module 1 is output to the flip-flop unit 11 in the next detection circuit module 1 after being inverted.
In this embodiment, the SET ends of the flip-flop units 11 in each detection circuit module 1 are connected to access a unified SET signal SET, and the flip-flop units 11 in each detection circuit module 1 can be controlled to be SET by inputting the SET signal SET.
In this embodiment, the output terminal of the flip-flop 11 in the last detection circuit module 1 is further connected to the input terminal of the flip-flop 11 in the first detection circuit module 1. The flip-flop cell 11 in the last detection circuit module 1 is feedback-connected to the input terminal of the flip-flop cell 11 in the first flip-flop cell 11 through the inverter 14. The first and the last determination are specifically determined according to a connection sequence, the first flip-flop unit 11 connected to the input end of the input signal is the first, and the detection circuit module 1 connected to the output end is the last.
In this embodiment, the number of the detection circuit modules 1 is an even number, that is, 2N, where N is greater than or equal to 1, and the specific data may be configured according to actual requirements.
In this embodiment, the flip-flop unit 11 is specifically a D flip-flop, and of course, other types of flip-flops may be adopted according to actual requirements.
In a specific application embodiment, to implement the detection device:
firstly, 1 trigger, 1 inverter, 1 multiplexer and a plurality of buffers are utilized to form a basic module of a holding time violation detection circuit according to the connection mode of a figure 3, wherein the input is SET, D, CLK and S, and the output is QN and CLKOUT; the input of the multiplexer is a signal output after CLK passes through buffers with different stages, and the output is CLKOUT; the delay of the CLK to CLKOUT path may be varied by controlling the select signal S of the multiplexer.
Then, an even number of basic blocks of the retention time violation detection circuit are connected in series, that is, the output signal QN of the basic block of the first retention time violation detection circuit is connected to the input signal D of the basic block of the second retention time violation detection circuit, the output signal CLKOUT of the basic block of the first retention time violation detection circuit is connected to the input signal CLK of the basic block of the second retention time violation detection circuit, and the SET input signals SET of all the basic blocks of the retention time violation detection circuit are shorted, and the multiplexer selection signals S of all the retention time violation detection circuits are shorted, so as to form the structure shown in fig. 2.
The output of the last hold time violation detection circuit basic block (# 2N in FIG. 2) is then connected to the input of the first hold time violation detection circuit basic block (# 1 in FIG. 2). The device for detecting the hold time violation of the digital circuit under the nuclear radiation environment is formed, the input of the whole device for detecting the hold time violation is SET, CLK and S, the output is OUT, wherein SET is a SET signal, CLK is an input clock signal, S is a multiplexer selection signal, OUT is an output signal, and whether the hold time violation occurs or not can be judged by observing the waveform of the OUT signal.
The circuit operating state transition table of the detection apparatus constructed as described above in the case where the hold time timing constraint is satisfied is shown in table 1 below, where D1 denotes a flip-flop input signal D in the first hold time violation detection circuit, and Q2 denotes a flip-flop output signal Q in the second hold time violation detection circuit.
Table 1: and (4) a circuit working state transition table.
| D1 | Q1 | D2 | Q2 | … | D2N | Q2N | OUT | ||
| After setting | 0 | 1 | 0 | 1 | … | 0 | 1 | 0 | |
| First beat | 1 | 0 | 1 | 0 | … | 1 | 0 | 1 | |
| Second beat | 0 | 1 | 0 | 1 | … | 0 | 1 | 0 | |
| |
1 | 0 | 1 | 0 | … | 1 | 0 | 1 | |
| … |
As shown in fig. 2 and the above table, after the hold time violation detecting circuit is SET by the SET signal, the output states of the flip-flops from front to back are sequentially inverted; if the hold time constraint in the detection circuit is satisfied, the signal of each flip-flop can be normally latched under the clock driving, and after the clock CLK with the duty ratio of 50% is input, the output signal OUT of the hold time violation detection circuit exhibits an oscillating state of 0101, the frequency of the OUT signal is 1/2 of the clock CLK, and the duty ratio of the OUT signal is 50%, as shown in fig. 4. If the holding time in the detection circuit is not regular, a metastable state phenomenon occurs, the signal of the flip-flop cannot be normally latched, the output waveform is distorted, and after the clock CLK with a duty ratio of 50% is input, the duty ratio of the OUT signal is no longer 50%, as shown in fig. 5, so that whether the holding time is irregular can be determined. The invention controls the retention time sequence constraint allowance by changing the time delay of the capture clock, controls the sensitivity of the detection circuit to the retention time violation in the nuclear radiation environment, ensures that the trigger can normally latch data under the condition that the retention time sequence constraint is satisfied, and when the retention time violation occurs, the trigger can not normally latch the data any more, and can accurately and efficiently realize the detection of the retention time violation in the nuclear radiation environment.
The foregoing is considered as illustrative of the preferred embodiments of the invention and is not to be construed as limiting the invention in any way. Although the present invention has been described with reference to the preferred embodiments, it is not intended to be limited thereto. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical spirit of the present invention should fall within the protection scope of the technical scheme of the present invention, unless the technical spirit of the present invention departs from the content of the technical scheme of the present invention.
Claims (8)
1. A device for detecting the hold time violation of a digital circuit in a nuclear radiation environment is characterized by comprising more than two detection circuit modules (1) which are sequentially connected, wherein each detection circuit module (1) comprises a trigger unit (11), a buffer unit (12) and a multiplexer unit (13), each buffer unit (12) comprises a plurality of buffer branches with different stages, each multiplexer unit (13) is respectively connected with each buffer branch, a control end of each multiplexer unit (13) inputs a selection signal S to control and select the buffer branch, a clock signal input end of each trigger unit (11) is connected with an input end of each buffer unit (12) to be connected with a clock signal CLK, an output end of each trigger unit (11) in a previous detection circuit module (1) is connected with an input end of each trigger unit (11) in a next detection circuit module (1), and outputting a final detection result by the output end of the trigger unit (11) in the last detection circuit module (1).
2. The apparatus for detecting violations of digital circuit hold times in nuclear radiation environment as claimed in claim 1, wherein the selection of different said buffer branches is controlled by adjusting the selection signal S inputted by each said multiplexer unit (13) to control the delay of changing the path between the clock signal CLK inputted by said buffer unit (2) and the output clock signal.
3. The apparatus of claim 1, wherein the hold time violation is determined according to a waveform status of the final detection result.
4. The arrangement for detecting a digital circuit hold time violation in a nuclear radiation environment according to claim 1, characterized in that the output of the flip-flop cell (11) is further provided with an inverter (14).
5. The apparatus for detecting digital circuit hold time violations in nuclear radiation environment as claimed in any of claims 1-4, wherein the SET terminals of the flip-flop cells (11) in each of said detection circuit modules (1) are connected to access a unified SET signal SET.
6. The apparatus for detecting digital circuit hold time violations in a nuclear radiation environment according to any of claims 1-4, wherein the output of the flip-flop cell (11) in the last detection circuit block (1) is further connected to the input of the flip-flop cell (11) in the first detection circuit block (1).
7. The device for detecting the hold time violation of a digital circuit in a nuclear radiation environment according to any of claims 1-4, wherein the number of the detection circuit modules (1) is an even number.
8. The arrangement for detecting violations of digital circuit hold times in a nuclear radiation environment as claimed in claim 1, wherein said flip-flop cells (11) are D flip-flops.
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| US5859776A (en) * | 1995-08-18 | 1999-01-12 | Sony Corporation | Method and apparatus for the design of a circuit |
| JPH10285003A (en) * | 1997-04-04 | 1998-10-23 | Nippon Samusun Kk | Delay circuit and character generating circuit using the circuit |
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