CN113884865A

CN113884865A - Test circuit and test method of D flip-flop

Info

Publication number: CN113884865A
Application number: CN202010624254.6A
Authority: CN
Inventors: 王旺; 林殷茵
Original assignee: Fudan University
Current assignee: Fudan University
Priority date: 2020-07-01
Filing date: 2020-07-01
Publication date: 2022-01-04
Anticipated expiration: 2040-07-01
Also published as: CN113884865B

Abstract

The invention belongs to the technical field of digital integrated circuits, and relates to a test circuit and a test method of a D trigger. The test circuit is used for testing the time sequence information of a D trigger in a digital integrated circuit and comprises a delay generation module, an oscillator circuit and a path selector; wherein the delay generation module comprises a first delay path and a second delay path, and the first delay path and the second delay path can be dynamically configured to output a first output signal and a second output signal with variable delay difference; the path selector is used for respectively connecting the first delay path and the second delay path under corresponding configuration into the oscillator circuit so as to respectively form a first oscillation loop and a second oscillation loop. The test circuit and the test method can eliminate the influence of the interconnection line delay and the process fluctuation of the test circuit on the test result, and have high test accuracy.

Description

Test circuit and test method of D flip-flop

Technical Field

The invention belongs to the technical field of digital integrated circuits, and relates to a test circuit and a test method of a D trigger.

Background

As the number of transistors on a chip increases dramatically as the moore's theorem directs semiconductor manufacturing to advance to smaller feature sizes, D-flipflops are one of the most important standard cells on digital integrated circuits, and chips also tend to have a large number of D-flipflops. Meanwhile, the frequency of the digital integrated circuit is also increasing continuously, and under high clock frequency, the time sequence information of the D trigger needs accurate modeling representation, so that a reliable circuit netlist can be synthesized in the circuit design stage.

However, the fluctuation of the threshold voltage of the device is increased along with the scaling of the process node, which has an important influence on the timing information of the standard cell (i.e., the D flip-flop), and accordingly, the process fluctuation is more and more difficult to characterize; and, as the process node is reduced, the proportion of the interconnection line delay to the path delay is increased.

The timing information of the D flip-flop generally comes from the testing of the D flip-flop by the testing circuit, however, the testing circuit itself is prone to process fluctuations and is affected by the interference of such process fluctuations, and the interconnection line delay of the testing circuit increasingly affects the testing result, so that the testing result of the testing circuit becomes unreliable or inaccurate.

At present, the clock frequency of a high-performance digital integrated circuit reaches above GHz, and under the condition that one clock period is less than 1ns, the timing margin for a logic unit between two D flip-flops is very small. In conventional EDA tools, both the setup time and the hold time of the D flip-flop leave a corresponding safety margin for a reliable circuit, however, this reduces the timing margin of the logic circuit. Therefore, if the setup time and the hold time of the timing information of the D flip-flops can be accurately measured and then fed back to the circuit design stage, more logic cells can be inserted between the two D flip-flops or the operating frequency of the circuit can be further increased.

It follows that it becomes very meaningful but increasingly difficult to accurately measure timing information of D flip-flops.

Disclosure of Invention

The purpose of the invention comprises improving the testing precision of the time sequence information of the D trigger.

To achieve the above and other objects, the present invention provides the following technical solutions.

According to an aspect of the present invention, there is provided a test circuit of a D flip-flop, for testing timing information of the D flip-flop in a digital integrated circuit; the test circuit includes:

a delay generation module comprising a first delay path for providing a first delayed output signal to a clock/data terminal of the D flip-flop under test, and a second delay path for providing a second delayed output signal to a data/clock terminal of the D flip-flop under test, wherein the first and second delay paths are dynamically configurable to have a variable delay difference between the first and second output signals;

an oscillator circuit; and

a path selector, for respectively connecting the first delay path and the second delay path in the corresponding configuration to the oscillator circuit when the third output signal of the D flip-flop under test is inconsistent with the data end in data at the rising edge time point corresponding to the clock end, so as to respectively form a first oscillation loop for outputting a first oscillation output signal with a first period and a second oscillation loop for outputting a second oscillation output signal with a second period, wherein the first period and the second period can be used to calculate or characterize the corresponding timing information.

According to an additional or alternative embodiment, the delay generation module is configured to fix the respective configurations of the first and second delay paths when the third output signal of the D flip-flop under test does not coincide in data with the data terminal at a rising edge time point corresponding to the clock terminal.

According to an additional or alternative embodiment, the first delay path comprises a first delay chain formed by a plurality of first delay cells connected in series and the second delay path comprises a second delay chain formed by a plurality of second delay cells connected in series, wherein the delay produced by a single first delay cell is different from the delay produced by a single second delay cell.

According to an additional or alternative embodiment, the first delay path further comprises a first selector arranged in correspondence with the first delay chain, wherein the first selector may be biased with different first configuration control signals to select different numbers of first delay cells in the first delay chain to be configured active so as to enable the first delay path to be dynamically configured;

the second delay path further comprises a second selector arranged corresponding to the second delay chain, wherein the second selector can be biased with different second configuration control signals to select different numbers of second delay units in the second delay chain to be configured to be effective, so as to realize that the second delay path is dynamically configured.

According to an additional or alternative embodiment, the first and second delay cells are first and second inverters, respectively.

According to an additional or alternative embodiment, the PMOS and NMOS transistors of the first inverter have the same gate width but different gate lengths than the PMOS and NMOS transistors of the second inverter, respectively.

According to an additional or alternative embodiment, the delay generating module further comprises a third selector configured to select to provide the first delayed output signal and the second delayed output signal to the clock terminal and the data terminal, respectively, in case a setup time of the timing information needs to be tested, and to provide the first delayed output signal and the second delayed output signal to the data terminal and the clock terminal, respectively, in case a hold time of the timing information needs to be tested.

According to an additional or alternative embodiment, the test circuit further comprises:

and the output module is used for receiving the first oscillation output signal and outputting fourth output information for amplifying the first period, receiving the second oscillation output signal and outputting fifth output information for amplifying the second period, wherein the fourth output information and the fifth output information are used for calculating and obtaining corresponding time sequence information.

According to an additional or alternative embodiment, the output module comprises a frequency divider.

According to an additional or alternative embodiment, the first or second oscillating output signal is output via an and gate with the first or second oscillating loop operating stably.

According to an additional or alternative embodiment, the timing information comprises a setup time and/or a hold time.

According to a further aspect of the invention, there is provided a chip comprising a digital integrated circuit having D flip-flops, further comprising a test circuit as described in any of the above for testing timing information of said D flip-flops.

According to a further aspect of the present invention, there is provided a method of testing any one of the above test circuits, comprising the steps of:

providing a first output signal output by a first delay path of the delay generation module to a clock terminal/data terminal of the D flip-flop to be tested, and providing a second output signal output by a second delay path of the delay generation module to a data terminal/clock terminal of the D flip-flop to be tested;

dynamically configuring the first delay path and the second delay path to make the delay difference between the first output signal and the second output signal which are dynamically output by the first delay path and the second delay path change until the third output signal of the D flip-flop to be tested is inconsistent in data with the data end at the time point of the rising edge corresponding to the clock end, and stopping dynamically configuring the first delay path and the second delay path;

respectively connecting the first delay path and the second delay path under corresponding configuration to the oscillator circuit, thereby respectively forming a first oscillation loop and a second oscillation loop; and

receiving a first oscillating output signal having a first period output by the first oscillating loop and a second oscillating output signal having a second period output by the second oscillating loop, wherein the first period and the second period can be used to calculate or characterize the corresponding timing information.

According to an additional or alternative implementation, the respective configurations of the first and second delay paths are fixed when the third output signal of the D flip-flop under test does not coincide in data with the data terminal at a point in time corresponding to a rising edge of the clock terminal.

According to an additional or alternative embodiment, in dynamically configuring the first delay path, a different number of first delay cells are selected and configured to be active in a first delay chain of the first delay path by a first configuration control signal;

in the process of dynamically configuring the second delay path, a different number of second delay cells are selected in the second delay chain by a second configuration control signal and configured to be active.

According to an additional or alternative embodiment, the timing information includes a setup time and/or a hold time;

when the time sequence information is tested for establishing time, the first delay output signal and the second delay output signal are respectively provided to the clock end and the data end;

and when the retention time of the time sequence information is tested, the first delay output signal and the second delay output signal are respectively provided to the data end and the clock end.

According to additional or alternative embodiments, the testing method further comprises the steps of:

and receiving the first oscillation output signal and outputting fourth output information for amplifying the first period, receiving the second oscillation output signal and outputting fifth output information for amplifying the second period, wherein the fourth output information and the fifth output information are used for calculating to obtain corresponding time sequence information.

The above features, operation and advantages of the present invention will become more apparent from the following description and the accompanying drawings.

Drawings

The above and other objects and advantages of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings, in which like or similar elements are designated by like reference numerals.

Fig. 1 is a schematic circuit diagram of a chip according to an embodiment of the present invention, in which a test circuit of a D flip-flop according to an embodiment of the present invention is shown.

Fig. 2 is a diagram illustrating setup and hold times of timing information of a tested D flip-flop, wherein fig. 2(a) illustrates the setup time and fig. 2(b) illustrates the hold time.

Fig. 3 is a schematic structural diagram of a delay generating module of a test circuit according to an embodiment of the invention.

Fig. 4 illustrates that the first delay path and the second delay path of the delay generating module are respectively connected to the oscillator circuit to form an oscillation loop in the oscillation output stage, wherein fig. 4(a) outputs the first oscillation loop having the first oscillation output signal ro _ out1 with a first period, and fig. 4(b) outputs the second oscillation loop having the second oscillation output signal ro _ out2 with a second period.

Fig. 5 is a schematic diagram of an inverter of a delay cell according to an embodiment of the present invention, in which fig. 5(a) illustrates a structure of an inverter in a first delay path, and fig. 5(b) illustrates a structure of an inverter in a second delay path.

Fig. 6 is a schematic diagram illustrating the testing principle of the testing circuit of the D flip-flop when testing the setup time of the D flip-flop according to an embodiment of the present invention.

Fig. 7 is a schematic diagram illustrating the testing principle of the testing circuit of the D flip-flop when testing the retention time of the D flip-flop according to an embodiment of the present invention.

Detailed Description

The following description is of some of the many possible embodiments of the invention and is intended to provide a basic understanding of the invention and is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Where used, the terms "first," "second," and the like do not necessarily denote any order or priority relationship, but rather may be used to more clearly distinguish one object from another.

Examples

Fig. 1 shows a schematic circuit diagram of a chip 90 according to an embodiment of the present invention, and a digital integrated circuit 20 using a D flip-flop 21 and a test circuit 10 of the D flip-flop according to an embodiment of the present invention are disposed in the chip 10. Chip 90 may be embodied as a digital IC chip with test circuit 10 or as a test chip that is specially manufactured for testing digital integrated circuit 20. The particular type, structure and/or function of digital integrated circuit 20 is not limiting. A plurality of D flip-flops 21 in the digital integrated Circuit 20 may be used as a tested object, and they may be arranged in an array form by a time-Sequence Circuit Under Test (SCUT), thereby forming a SCUT array as shown in fig. 1. The number of D flip-flops 21 in the SCUT array is not limited, and one or more D flip-flops 21 in the SCUT array may be selected by a decoder 22 or the like in the digital integrated circuit 20 to perform a test of timing information; where SEL _ FF [7:0] is a selection signal input to the decoder 22 for selecting the D flip-flop 21 under test, RST is a set signal of the decoder 22, and EN is an enable signal of the decoder 22.

In chip 90, test circuit 10 may be provided independently from digital integrated circuit 20, and both test circuit 10 and digital integrated circuit 20 may be fabricated together under process conditions at a node. It will be appreciated that the test circuit 10 itself is also susceptible to process variation interference and has some interconnect delay, particularly as feature sizes get smaller. The test circuit 10 may be used to test timing information of a selected one of the D flip-flops 21 in the digital integrated circuit 20, such as parameters of setup time and hold time of the test D flip-flop 21. As shown in fig. 2, the setup time refers to the time that data needs to be kept unchanged before the sampling edge of the clock CLK comes, which includes data being low (D _ low) and high (D _ high); the hold time refers to the time that data needs to be held constant after the sampling edge of the clock CLK, and the data also has two types of high (D _ high) and low (D _ low).

Referring to fig. 1, the test circuit 10 mainly includes a delay time generation module 110, a path selector 130, an oscillator circuit 140, and in an embodiment, may further include an output module implemented by, for example, a frequency divider 150, a third selector 119, and the like.

With reference to fig. 1 and 3, the delay generating module 110 may include a first delay path 111 and a second delay path 112; in an embodiment, the first delay path 111 may be configured to provide the first delayed output signal p1 to the clock terminal CLK of the D flip-flop under test 21, and the second delay path 112 may be configured to provide the second delayed output signal p2 to the data terminal D of the D flip-flop under test 21; in yet another alternative embodiment, the first delay path 111 may be used to provide the first delayed output signal p1 to the data terminal D of the D flip-flop under test 21, and the second delay path 112 may be used to provide the second delayed output signal p2 to the clock terminal CLK of the D flip-flop under test 21. The first and

second delay paths

111, 112 may be dynamically configured such that they output a variable delay difference Δ d between the first and second output signals p1, p2 (e.g., the delay difference Δ d becomes smaller from Δ d0, Δ d1, Δ d2, …, to Δ d _ out as shown in fig. 6). the manner in which the first and

second delay paths

111, 112 are dynamically configured and applied to the dynamic configuration phase of the test method as shown in fig. 6 will be illustrated below.

In an embodiment, as shown in fig. 3, the first delay path 111 includes a first delay chain 1111 formed by serially connecting a plurality of first delay units 1101, and the second delay path includes a second delay chain 1121 formed by serially connecting a plurality of second delay units 1102, where the first delay unit 1101 and the second delay unit 1102 may be represented as delay gates, and may be implemented by inverters, for example. The delay caused by a single first delay unit 1101 may be different from the delay caused by a single second delay unit 1102, e.g. the delay caused by a single second delay unit 1102 is shorter than the delay caused by a single first delay unit 1101. Specifically, referring to fig. 5, different delays can be realized by setting the gate structures of the first inverter 1101 corresponding to the first delay unit and the second inverter 1102 corresponding to the second delay unit, for example, the PMOS transistor and the NMOS transistor of the first inverter 1101 have the same gate width but different gate lengths than the PMOS transistor and the NMOS transistor of the second inverter 1102, and their gate length difference from each other will determine the magnitude of the delay difference between the first inverter 1101 and the second inverter 1102, and further determine the maximum precision (for example, reaching picosecond level) of the change of the delay difference Δ d in the dynamic configuration process.

The number of first delay units 1101 preset in the first delay chain 1111 may be determined at the time of manufacture (e.g., 256), but whether they are configured to be valid or not may be controlled by the first configuration control signals sel1_ del [7:0 ]; likewise, the number of second delay cells 1102 preset in the second delay chain 1112 may be determined at the time of manufacture (e.g., 255), but whether they are configured to be active may be controlled by the second configuration control signals sel2_ del [7:0 ]. To this end, first delay path 111 further includes a first selector 1112 arranged corresponding to first delay chain 1111, wherein first selector 1112 may be set with different first configuration control signals sel1_ del [7:0] to select different numbers of first delay units 1101 to be configured active in first delay chain 1111, thereby enabling first delay path 111 to be dynamically configured, first delay output signal p1 of first delay path 111 may be dynamically adjusted to change; second delay path 112 further includes a second selector 1122 provided in correspondence with second delay chain 1121, wherein second selector 1122 can be set with different second configuration control signals sel2_ del [7:0] to select different numbers of second delay cells 1102 in second delay chain 1121 to be configured active, thereby enabling second delay path 112 to be dynamically configured, and second delay output signal p2 of second delay path 112 can be dynamically adjusted to change. The first and

second selectors

1112 and 1122 may be specifically 256-to-1 selectors.

In particular, in case the delay caused by a single first delay unit 1101 may be different from the delay caused by a single second delay unit 1102, the first configuration control signals sel1_ del [7:0] and the second configuration control signals sel2_ del [7:0] may be the same (e.g., both input sel _ del [7:0] as shown in fig. 6), therefore, the number of first delay units 1101 configured to be valid in first delay chain 1111 is equal to the number of second delay units 1102 configured to be valid in second delay chain 1121 (i.e. the effective chain lengths of first delay chain 1111 and second delay chain 1121 are equal), the effective chain lengths of first delay chain 1111 and second delay chain 1121 are changed synchronously, different delay differences Δ d may be generated between first delay output signal p1 and second delay output signal p2 according to the synchronous change of the effective chain lengths, therefore, it is relatively easy to control the dynamic configuration process and the variation process of the delay difference Δ d is finer.

Illustratively, referring to fig. 3 and 6, in the dynamic configuration phase, by controlling the changes of the first configuration control signal sel1_ del [7:0] and the second configuration control signal sel2_ del [7:0], the effective chain lengths of the first delay chain 1111 and the second delay chain 1121 may be controlled to gradually change from 256 to 1, and the delay difference Δ D between the first delay output signal p1 of the first delay path 111 and the first delay output signal p2 of the first delay path 112 will gradually and linearly decrease until the change of the sel1_ del [7:0] and the second configuration control signal sel2_ del [7:0] and the change of the fixed delay chain length of the first delay chain 111 and the second delay chain 1111 (i.e. the first delay chain 111 and the second delay chain 112) are stopped when the time point of the third output signal Q of the D flip-flop 21 under test does not coincide with the time point of the corresponding clock terminal CLK (i.e. the rising edge of the second output signal p2 or the first output signal p 1) and the data terminal D on the data side, respectively, the change of the effective chain lengths of the first delay chain 1111 and the second delay chain 112 (i.e. the corresponding delay chain 112 and the fixed delay chain 112) are stopped Timing), the delay difference between the first delayed output signal p1 and the first delayed output signal p2 is also fixed, for example, at the delay difference Δ d _ out.

It will be appreciated that in other alternative embodiments, the delay generated by a single first delay unit 1101 may be equal to the delay generated by a single second delay unit 1102, and that during the dynamic configuration, the first configuration control signal sel1_ del [7:0] and the second configuration control signal sel2_ del [7:0] may not be the same, so that the number of first delay units 1101 configured to be active in the first delay chain 1111 may not be equal to the number of second delay units 1102 configured to be active in the second delay chain 1121 (i.e. the effective chain lengths of the first delay chain 1111 and the second delay chain 1121 are not equal), the effective chain lengths of the first delay chain 1111 and the second delay chain 1121 may not change synchronously, and the difference Δ D between the first delay output signal p1 and the second delay output signal p2 may also change with the difference between the effective chain lengths thereof until the rising edge time point of the third output signal Q of the D flip-flop 21 under test and the data terminal CLK at the corresponding clock terminal CLK and the data terminal D In the event of a data inconsistency, the changes of sel1_ del [7:0] and second configuration control signals sel2_ del [7:0] are stopped, and the respective configurations of first delay path 111 and second delay path 112 (i.e., the effective chain lengths of first delay chain 1111 and second delay chain 1121 are fixed) are fixed.

With continued reference to fig. 1 and 4, the oscillator circuit 140 may be formed from several inverters, which may be looped with any one of the first delay path 111 and the second delay path 112 to form a first oscillation loop 1401 or a second oscillation loop 1402.

The path selector 130 may specifically be a 1-out-of-2 MUX, which may be triggered to operate when the third output signal Q of the D flip-flop 21 under test does not coincide with the data terminal D in data at the time point of the rising edge of the corresponding clock terminal CLK, that is, in the oscillation output phase shown in fig. 6; the path selector 130 connects the first delay path 111 and the second delay path 112 in a corresponding configuration (e.g., in case of a fixed effective chain length) to the oscillator circuit 140, respectively, so as to form a first oscillation loop 1401 and a second oscillation loop 1402, respectively, the first oscillation loop 1401 may output a first oscillation output signal ro _ out1 (see fig. 6) having a first period T1, and the second oscillation loop 1402 may output a second oscillation output signal ro _ out2 (see fig. 6) having a second period T2, wherein the first period T1 and the second period T2 may be used to calculate or characterize corresponding timing information (e.g., setup time or hold time).

Specifically, the path select signal sel _ ro may be applied to the path selector 130 during the oscillation output phase to select one of the first delay path 111 and the second delay path 112 to be respectively coupled to the oscillator circuit 140.

It should be noted that, different from the conventional test circuit, the test circuit 10 of the above embodiment may put the entire first delay path 111 or the second delay path 112 outside the tested timing unit into the oscillation loop, and the period of the oscillation output signal of the

oscillation loop

1401 or 1402 includes the entire delay of the delay path of the test circuit 10, so that the test result easily eliminates the influence of the process fluctuation on the two delay paths and the interconnect delay on the test result, that is, the influence of the interconnect delay and the process fluctuation of the test circuit 10 on the timing information of the tested D flip-flop 21 is eliminated, and the test result is relatively accurate, for example, can reach picosecond magnitude.

In an embodiment, referring to fig. 1 and 4, the first oscillation output signal ro _ out1 or the second oscillation output signal ro _ out2 is output through the and gate 141 in case that the first oscillation loop 1401 or the second oscillation loop 1402 stably operates; wherein the output process can be controlled by controlling the oscillation loop output enable signal rst _ freq applied to the and gate 141.

Continuing with fig. 1, in an embodiment, considering that the first period T1 and the second period T2 are too short to be used for calculating or characterizing the setup time or the hold time, the test circuit 10 may further include an output module, which may be implemented by, but not limited to, the frequency divider 150, and the frequency divider 150 may receive the first oscillating output signal ro _ out1 and output fourth output information out _ T1 (e.g., frequency division output information) for amplifying the first period T1, and may also receive the second oscillating output signal ro _ out2 and output fifth output information out _ T2 (e.g., frequency division output information) for amplifying the second period T2, wherein the fourth output information out _ T1 and the fifth output information out _ T2 are used for calculating corresponding timing information.

As shown in fig. 1, in an embodiment, to conveniently implement the test circuit 10 to be compatible with both the test setup time and the test hold time, the corresponding delay time generation module 110 further includes a third selector 119, and the third selector 119 is configured to: in the case that the setup time of the timing information needs to be tested, the first delayed output signal p1 and the second delayed output signal p2 are selected to be provided to the clock terminal CLK and the data terminal D, respectively, and the first delayed output signal p1 and the second delayed output signal p2 are selected to be provided to the data terminal D and the clock terminal CLK, respectively, in the mode of testing the holding time of the timing information; that is, the third selector 119 may switchably output two delay paths, thereby conveniently switching between the test setup time and the hold time. The third selector 119 may be controlled by a select signal sel _ path to implement the above-described switching action.

It should be noted that the test circuit 10 can operate in one of a dynamic configuration mode and an oscillation output mode. The switching of the two modes can be realized by a mode control signal mode; when the mode is equal to 1, the test circuit 10 operates in the dynamic configuration mode and enters the dynamic configuration stage of the test process, and when the mode is equal to 0, the test circuit 10 operates in the oscillation output mode and enters the oscillation output stage of the test process.

The following further illustrates a method for testing timing information of the D flip-flop 10 according to an embodiment of the present invention with reference to the operation waveforms shown in fig. 1 and fig. 6, where the method includes a dynamic configuration phase and an oscillation output phase.

First, a signal, which is generally a reference square wave signal, is generated and applied to the delay generating module 110, and the delay chains on the first delay path 111 and the second delay path 112 are configured to be longest, at which time, the first output signal p1 and the second output signal p2 have the largest delay difference, i.e., the initial delay difference Δ d 0.

Taking the setup time for testing and setting up a selected D flip-flop 21 as an example, the first output signal p1 output by the first delay path 111 of the delay generation module 110 is provided to the clock terminal CLK of the D flip-flop 21 under test, and the second output signal p2 output by the second delay path 112 of the delay generation module 110 is provided to the data terminal D of the D flip-flop 21 under test. That is, the data terminal D is connected to one end of the first delay path 111 with smaller delay unit, for example, p2 in fig. 3, and the clock terminal CLK is connected to one end with larger delay, for example, p 1.

Further, the first delay path 111 and the second delay path 112 are dynamically configured such that the delay difference Δ D between the first output signal p1 and the second output signal p2 that they dynamically output varies until the third output signal Q of the D flip-flop under test 21 at the rising edge of the corresponding clock terminal CLK does not coincide in data, and the first delay path 111 and the second delay path 112 are stopped from being dynamically configured. During the dynamic configuration, the effective chain lengths of the first delay chain 1111 and the second delay chain 1121 may be controlled by controlling the first configuration control signal sel1_ del [7:0] and the second configuration control signal sel2_ del [7:0] applied to the delay generation module 110, for example, the first configuration control signal sel1_ del [7:0] and the second configuration control signal sel2_ del [7:0] are continuously decreased, and the delay chain selected by the first selector 1112 and the second selector 1122 is continuously decreased, at which the delay difference Δ D between the rising edges of the signals of the data terminal D and the clock terminal CLK (for example, between the rising edges of p1 and p 2) of the D flip-flop is continuously decreased (for example, as shown in fig. 6, the delay difference Δ D is continuously decreased from Δ D0, Δ D1, Δ D2, …, to Δ D _ out); meanwhile, continuously observing the third output signal Q corresponding to the Q terminal of the D flip-flop 21, at a certain rising edge time point of the first output signal p1 (i.e. a certain rising edge time point of the clock terminal CLK), when the third output signal Q is just inconsistent with the second output signal p2 of the data terminal D in data (for example, when the sampling value of the Q terminal at the rising edge time point of p1 is just not equal to the input value of the data terminal D at the time point), it indicates that the setup time is failed, and at this time, the difference between the rising edge of the data terminal D and the rising edge of the clock terminal CLK is the corresponding setup time.

Further, the oscillation output stage is entered, and the entering of the oscillation output stage can be specifically controlled by the transformation of the input value of the mode control signal mode. In the oscillation output stage, first, the first delay path 111 and the second delay path 112 in the corresponding configuration are respectively connected to the oscillator circuit 140, so as to respectively form a first oscillation loop 1401 and a second oscillation loop 1402; this step may be implemented by applying a corresponding path select signal sel _ ro to the path selector 130.

In the oscillation output stage, further, the first oscillation output signal ro _ out1 or the second oscillation output signal ro _ out2 (as shown in fig. 6) is output through the and gate 141 under the condition that the first oscillation loop 1401 or the second oscillation loop 1402 stably operates, so that the first period T1 of the first oscillation output signal ro _ out1 and the second period T2 of the second oscillation output signal ro _ out2 can be obtained.

In one embodiment, the oscillation output stage of the test method further comprises the steps of: receiving the first oscillating output signal ro _ out1 and outputting fourth output information out _ T1 for amplifying the first period T1, receiving the second oscillating output signal ro _ out2 and outputting fifth output information out _ T2 for amplifying the second period T2, wherein the fourth output information out _ T1 and the fifth output information out _ T2 are used for calculating corresponding timing information. Illustratively, in this step, the received first and second oscillating output signals ro _ out1 and ro _ out2 are subjected to frequency division processing, resulting in periods T1 'and T2' from the first and second periods T1 and T2, respectively. Thus, the settling time may ultimately be calculated by (T1 '-T2')/(2 x k), where k is the division multiple.

To this end, the setup time of the D flip-flop 21 can be tested.

When testing the holding time of the D flip-flop 21, the testing process is substantially the same as the above testing setup time, and only the first delay output signal p1 and the second delay output signal p2 need to be changed to be respectively provided to the data terminal D and the clock terminal CLK, that is, the two delay paths are output in an exchange manner, and the exchange operation can be controlled and implemented by the selection signal sel _ path; accordingly, in the dynamic configuration phase, the third output signal Q corresponding to the Q terminal of the D flip-flop 21 is continuously observed, and at a certain rising edge time point of the second output signal p2 (i.e. a certain rising edge time point of the clock terminal CLK), when the third output signal Q is just inconsistent with the first output signal p1 of the data terminal D in data (for example, when the value of the sample of the Q terminal at the rising edge time point of p2 is just not equal to the input value of the data terminal D at the time point), it indicates that the holding time is invalid, and then the difference between the rising edge of the data terminal D and the rising edge of the clock terminal CLK is the corresponding holding time. See fig. 7 for a timing diagram of the hold time of the test D flip-flop.

The testing method of the above embodiment can effectively eliminate the process fluctuation of the delay path of the testing circuit 10 itself and the influence of the delay of the interconnection line on the testing result, and the time information such as the setup time, the hold time, and the like of the D flip-flop 21 can be accurately tested, and particularly, the testing precision is higher under the condition that the delay generated by the single first delay unit 1101 can be different from the delay generated by the single second delay unit 1102.

The above examples mainly illustrate the test circuit and the test method of the present invention. Although only a few embodiments of the present invention have been described, those skilled in the art will appreciate that the present invention may be embodied in many other forms without departing from the spirit or scope thereof. Accordingly, the present examples and embodiments are to be considered as illustrative and not restrictive, and various modifications and substitutions may be made therein without departing from the spirit and scope of the present invention as defined by the appended claims.

Claims

1. A test circuit for a D flip-flop for testing timing information of the D flip-flop in a digital integrated circuit, the test circuit comprising:

an oscillator circuit; and

a path selector, for respectively connecting the first delay path and the second delay path in the corresponding configuration to the oscillator circuit when the third output signal of the D flip-flop under test is inconsistent in data at the rising edge time point corresponding to the clock terminal, so as to respectively form a first oscillation loop for outputting a first oscillation output signal with a first period and a second oscillation loop for outputting a second oscillation output signal with a second period, wherein the first period and the second period can be used for calculating or characterizing the corresponding timing information.

2. The test circuit of a D flip-flop of claim 1, wherein the delay generation module is configured to fix the respective configurations of the first delay path and the second delay path when a third output signal of the D flip-flop under test does not coincide in data with the data terminal at a rising edge time point corresponding to the clock terminal.

3. The test circuit of a D flip-flop of claim 1 or 2, wherein said first delay path comprises a first delay chain formed by a plurality of first delay cells connected in series and said second delay path comprises a second delay chain formed by a plurality of second delay cells connected in series, wherein a delay produced by a single said first delay cell is different from a delay produced by a single said second delay cell.

4. The test circuit of a D flip-flop of claim 3, wherein said first delay path further comprises a first selector disposed corresponding to said first delay chain, wherein said first selector is biasable with different first configuration control signals to select a different number of first delay cells in said first delay chain to configure as active so as to enable said first delay path to be dynamically configured;

5. The test circuit of a D flip-flop of claim 3, wherein said first delay cell and said second delay cell are a first inverter and a second inverter, respectively.

6. The test circuit of the D flip-flop of claim 5, wherein the PMOS and NMOS transistors of the first inverter have the same gate width but different gate lengths than the PMOS and NMOS transistors of the second inverter, respectively.

7. The test circuit of a D flip-flop of claim 1, wherein said delay time generation module further comprises a third selector configured to select to provide said first delayed output signal and said second delayed output signal to said clock terminal and a data terminal, respectively, in case of a setup time required to test said timing information, and to provide said first delayed output signal and said second delayed output signal to said data terminal and a clock terminal, respectively, in case of a hold time required to test said timing information.

8. The test circuit for a D flip-flop of claim 1, wherein said test circuit further comprises:

9. The test circuit for a D flip-flop of claim 8, wherein said output module comprises a frequency divider.

10. The test circuit of a D flip-flop of claim 1, wherein the first or second oscillating output signal is output through an and gate in a case where the first or second oscillating loop stably operates.

11. The test circuit of a D flip-flop of claim 1, wherein said timing information comprises a setup time and/or a hold time.

12. A chip comprising a digital integrated circuit with D flip-flops, characterized in that it further comprises a test circuit for testing the timing information of the D flip-flops as claimed in any one of claims 1 to 11.

13. A method of testing a test circuit as claimed in claim 1, comprising the steps of:

14. The test method of claim 13, wherein the respective configurations of the first and second delay paths are fixed when the third output signal of the D flip-flop under test does not coincide in data with the data terminal at a rising edge time point corresponding to the clock terminal.

15. The test method of claim 13, wherein in dynamically configuring the first delay path, a different number of first delay cells are selected and configured to be active in a first delay chain of the first delay path by a first configuration control signal;

16. The test method according to claim 13, wherein the timing information comprises a setup time and/or a hold time; when the time sequence information is tested for establishing time, the first delay output signal and the second delay output signal are respectively provided to the clock end and the data end;

17. The test method of claim 13, further comprising the steps of: