CN103576079B - Chip test system and chip detecting method - Google Patents

Chip test system and chip detecting method Download PDF

Info

Publication number
CN103576079B
CN103576079B CN201310574106.8A CN201310574106A CN103576079B CN 103576079 B CN103576079 B CN 103576079B CN 201310574106 A CN201310574106 A CN 201310574106A CN 103576079 B CN103576079 B CN 103576079B
Authority
CN
China
Prior art keywords
signal
test
chip
output
clock signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201310574106.8A
Other languages
Chinese (zh)
Other versions
CN103576079A (en
Inventor
张大成
施瑾
刘远华
顾春华
郝丹丹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sino IC Technology Co Ltd
Original Assignee
Sino IC Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sino IC Technology Co Ltd filed Critical Sino IC Technology Co Ltd
Priority to CN201310574106.8A priority Critical patent/CN103576079B/en
Publication of CN103576079A publication Critical patent/CN103576079A/en
Application granted granted Critical
Publication of CN103576079B publication Critical patent/CN103576079B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Landscapes

  • Tests Of Electronic Circuits (AREA)

Abstract

The invention provides a kind of chip test system and chip detecting method, wherein, described chip test system includes: test machine, crystal oscillator and Signal Analysis System, and described test machine and crystal oscillator are all connected with described Signal Analysis System;Described test machine is in order to provide test signal;Described crystal oscillator is in order to provide clock signal;Described Signal Analysis System is in order to obtain the signal output time of test machine output test signal;Wherein, described test machine is according to signal output time output test signal.At this, obtained the signal output time of test machine output test signal by Signal Analysis System, test machine exports test signal accordingly, and thus test machine just can select the moment of output test signal, and then realize and clock signal synchronization, thus obtain reliable/chip testing result accurately.

Description

Chip test system and chip detecting method
Technical field
The present invention relates to ic manufacturing technology field, survey particularly to a kind of chip test system and chip Method for testing.
Background technology
Due to being rapidly introduced into of day by day complicated integrated circuit, material and technique, during the silicon chip in today manufactures Hardly possible each chip requirement up to specification.For correcting the problem in manufacturing process, and guarantee to have scarce Fall into chip will not be sent in client's hands, introduce in ic manufacturing process chip testing (CP, Circuit Probing).Chip testing is in order to check the concordance of specification and to carry out on silicon chip level integrated circuit Electrical parameter measure and functional test.Test can verify whether each chip has acceptable electrical property Can be with complete function, the electricity specification used in its test process is different with the difference of test purpose. If chip testing imperfection, it is possible to cause more product to lose efficacy during client uses, finally give Chip maker brings serious consequence.Introduce in the manufacture process of integrated circuit can find early for this Technological problems and be requisite by the bad select chip testing of chip.
Chip test system generally includes test machine (Automatic Test Equipment, ATE), test machine Be quickly, accurately, repeatedly can measure on device under test submicron level electric current and millivolt level voltage from Dynamic device.Concrete, test machine will test signal (at present specification middle finger in addition to clock signal Signal in order to test) it is input in device under test (DUT, Device Under Test), receive the most again This device under test is for the accordingly result of input signal.When carrying out chip testing, often also need to use crystalline substance Shake to produce the clock signal needed for test.Such as, in the test of some chip, clock signal is wanted Ask comparison special, such as the clock of 19.44MHz, be to have no idea to be given by test machine, it is therefore desirable to use External crystal oscillator carrys out device under test provides clock signal.Owing to clock signal and test signal are by different devices Produce/provide (wherein clock signal is provided by crystal oscillator, test signal provided by test machine), therefore both it Between the most asynchronous, and then make obtained chip testing result inaccurate/unreliable.
Therefore it provides a kind of chip test system, its clock signal being capable of output and test signal are same Step, thus obtain accurately/reliable chip testing result, become the difficult problem that those skilled in the art are urgently to be resolved hurrily.
Summary of the invention
It is an object of the invention to provide a kind of chip test system and chip detecting method, existing to solve In chip test system, the most asynchronous between clock signal and test signal, and then make obtained core Inaccurate/insecure problem of built-in testing result.
For solving above-mentioned technical problem, the present invention provides a kind of chip test system, described chip test system Including test machine, crystal oscillator and Signal Analysis System, described test machine and crystal oscillator all with described signal analysis system System connects;Described test machine is in order to provide test signal;Described crystal oscillator is in order to provide clock signal;Described letter Number analysis system is in order to obtain the signal output time of test machine output test signal;Wherein, described test machine According to signal output time output test signal.
Optionally, in described chip test system, described signal output time rising according to clock signal Shake the time and test signal the output used time determine.
Optionally, in described chip test system, described signal output time rising according to clock signal Shake the time, low and high level redirect the moment and test signal the output used time determine.
Optionally, in described chip test system, when described crystal oscillator often exports a clock signal, Described Signal Analysis System just obtains the signal of the test machine output test signal corresponding with this clock signal Output time.
Optionally, in described chip test system, the test signal that described test machine provides includes voltage Signal and/or current signal.
Optionally, in described chip test system, the clock signal that described crystal oscillator provides includes that square wave is believed Number.
Optionally, in described chip test system, also include: the probe card being connected with described test machine, And the probe station being connected with described probe card.
The present invention also provides for a kind of chip detecting method, and described chip detecting method includes:
Crystal oscillator output clock signal, test machine output test signal;
Signal Analysis System receives described clock signal and test signal, and obtains test machine output test signal Signal output time;
Test machine exports test signal again according to signal output time.
Optionally, in described chip detecting method, described signal output time rising according to clock signal Shake the time and test signal the output used time determine.
Optionally, in described chip detecting method, described signal output time rising according to clock signal Shake the time, low and high level redirect the moment and test signal the output used time determine.
Optionally, in described chip detecting method, when described crystal oscillator often exports a clock signal, Described Signal Analysis System just obtains the signal of the test machine output test signal corresponding with this clock signal Output time.
Optionally, in described chip detecting method, the test signal that described test machine provides includes voltage Signal and/or current signal.
Optionally, in described chip detecting method, the clock signal that described crystal oscillator provides includes that square wave is believed Number.
In the chip test system and chip detecting method of present invention offer, obtained by Signal Analysis System The signal output time of test machine output test signal, test machine exports test signal, thus test machine accordingly Just can select the moment of output test signal, and then realize and clock signal synchronization, thus obtain reliable/accurate True chip testing result.
Accompanying drawing explanation
Fig. 1 is the mount structure schematic diagram of the chip test system of the embodiment of the present invention;
Fig. 2 is the schematic diagram of the clock signal of the embodiment of the present invention;
Fig. 3 is the schematic flow sheet of the chip detecting method of the embodiment of the present invention.
Detailed description of the invention
The chip test system present invention proposed below in conjunction with the drawings and specific embodiments and chip detecting method It is described in further detail.According to following explanation and claims, advantages and features of the invention will be more clear Chu.It should be noted that, accompanying drawing all uses the form simplified very much and all uses non-ratio accurately, only in order to Conveniently, the purpose of the embodiment of the present invention is aided in illustrating lucidly.
Refer to Fig. 1, it is the mount structure schematic diagram of chip test system of the embodiment of the present invention.Such as Fig. 1 institute Showing, described chip test system includes: test machine 10, crystal oscillator 20 and Signal Analysis System 30, described survey Test-run a machine 10 and crystal oscillator 20 are all connected with described Signal Analysis System 30;Described test machine 10 is in order to provide survey Trial signal;Described crystal oscillator 20 is in order to provide clock signal;Described Signal Analysis System 30 is in order to obtain test The signal output time of machine output test signal;Wherein, described test machine 10 exports according to signal output time Test signal.
Refer to Fig. 2, it is the schematic diagram of clock signal of the embodiment of the present invention.As in figure 2 it is shown, described time Clock signal includes two periods of T1 and T2, and wherein, in time period T1, described clock signal is in instability State, namely starting of oscillation state, commonly referred to Induction Peried;In time period T2, described clock signal is in surely Determine state, commonly referred to stabilization time.
In the present embodiment, the signal output time acquired in described Signal Analysis System 30 is according to clock signal Induction Peried and test signal the output used time determine.Concrete, according to the length of time period T1 with And the time that the output test of described test machine 10 is used by signal determines, i.e. obtain the difference between two time. Thus, when described test machine 10 exports test signal again, just it can be avoided that difference between the two time Different, thus realize and clock signal synchronization.
Further, the rising according to clock signal of the signal output time acquired in described Signal Analysis System 30 Shake the time, low and high level redirect the moment and test signal the output used time determine.Concrete, according to In the length of time period T1, time period T2, low and high level redirects moment and described test machine 10 output survey Time used by trial signal determines.Thus can not only obtain the difference between two time, and can obtain Low and high level in clock signal redirect time point, thus believe when described test machine 10 export test again Number time, it is possible to selection is the high level moment in time period T2 or low level moment or low and high level is jumped Turn moment, and then the clock that the test signal that described test machine 10 is exported is exported with described crystal oscillator 20 Signal well coordinates, and improves precision and the reliability of chip testing.
In the present embodiment, described Signal Analysis System 30 can include signal analyzer and the meter of signal acquisition Calculate, analyze the computer of signal, i.e. first pass through signal analyzer seizure test machine 10 and crystal oscillator 20 exports Signal;Then pass through computer and calculate the difference etc. between clock signal and test signal, thus final To information such as signal output times.
Common, when crystal oscillator 20 exports clock signal every time, when Induction Peried T1 and low and high level redirect Quarter differs.It is preferred, therefore, that when using described chip test system, when described crystal oscillator 20 is every During clock signal of output, described Signal Analysis System 30 just obtains the survey corresponding with this clock signal The signal output time of test-run a machine output test signal.Thus so that the letter that described test machine 10 is obtained every time Number output time be correct/reliably, and then make test signal that described test machine 10 exported and described crystalline substance Shake 20 clock signal synchronizations exported, and improves chip testing result.
In the present embodiment, the test signal that described test machine 10 provides includes voltage signal and/or electric current letter Number;The clock signal that described crystal oscillator 20 provides includes square-wave signal.Common, described test machine 10 basis Signal output time output test signal, the test signal that described test machine 10 is exported and described square-wave signal Rising edge or trailing edge synchronize.In the present embodiment, the test signal that described test machine 10 is exported can Tong Bu with any one rising edge in time period T2 or trailing edge.
Further, described chip test system may also include that the probe card (Fig. 1 being connected with described test machine Not shown in), and the probe station (not shown in figure 1) being connected with described probe card.Wherein, described probe Card is in order to connecting test machine and device under test;Described probe station is also referred to as chip positioning device, in order at X, Y With the position that Z-direction adjusts device under test.
Accordingly, the present embodiment also provides for a kind of chip detecting method, refer to Fig. 3, and it is implemented for the present invention The schematic flow sheet of the chip detecting method of example.As it is shown on figure 3, described chip detecting method includes:
Step S10: crystal oscillator 20 exports clock signal, test machine 10 output test signal;
Step S20: Signal Analysis System 30 receives described clock signal and test signal, and obtains test machine The signal output time of output test signal;
Step S30: test machine 10 exports test signal again according to signal output time.
Here, obtain the signal output time of test machine output test signal by Signal Analysis System 30 and carry Supply test machine 10, test machine 10 is according to signal output time output test signal, the thus test machine received The test signal of 10 outputs just with clock signal synchronization, thus can obtain reliable/chip testing result accurately.
As fully visible, obtained the signal output time of test machine output test signal by Signal Analysis System, Test machine exports test signal accordingly, and thus test machine just can select the moment of output test signal, and then Realize and clock signal synchronization, thus obtain reliable/chip testing result accurately.
Foregoing description is only the description to present pre-ferred embodiments, not any limit to the scope of the invention Fixed, any change that the those of ordinary skill in field of the present invention does according to the disclosure above content, modification, all belong to Protection domain in claims.

Claims (13)

1. a chip test system, it is characterised in that including: test machine, crystal oscillator and Signal Analysis System, Described test machine and crystal oscillator are all connected with described Signal Analysis System;Described test machine is in order to provide test signal; Described crystal oscillator is in order to provide clock signal;Described Signal Analysis System is in order to obtain test machine output test signal Signal output time;Wherein, described test machine exports test signal again according to signal output time.
2. chip test system as claimed in claim 1, it is characterised in that described signal output time root Determine according to the Induction Peried of clock signal and the output used time of test signal.
3. chip test system as claimed in claim 1, it is characterised in that described signal output time root Determine according to the Induction Peried of clock signal, the output used time redirecting moment and test signal of low and high level.
4. chip test system as claimed in claim 1, it is characterised in that when described crystal oscillator often exports During secondary clock signal, described Signal Analysis System just obtains the test machine output corresponding with this clock signal The signal output time of test signal.
5. the chip test system as according to any one of Claims 1 to 4, it is characterised in that described test The test signal that machine provides includes voltage signal and/or current signal.
6. the chip test system as according to any one of Claims 1 to 4, it is characterised in that described crystal oscillator The clock signal provided includes square-wave signal.
7. the chip test system as according to any one of Claims 1 to 4, it is characterised in that also include: The probe card being connected with described test machine, and the probe station being connected with described probe card.
8. a chip detecting method, it is characterised in that including:
Crystal oscillator output clock signal, test machine output test signal;
Signal Analysis System receives described clock signal and test signal, and obtains test machine output test signal Signal output time;
Test machine exports test signal again according to signal output time.
9. chip detecting method as claimed in claim 8, it is characterised in that described signal output time root Determine according to the Induction Peried of clock signal and the output used time of test signal.
10. chip detecting method as claimed in claim 8, it is characterised in that described signal output time Induction Peried according to clock signal, low and high level the output used time redirecting moment and test signal really Fixed.
11. chip detecting methods as claimed in claim 8, it is characterised in that when described crystal oscillator often exports During clock signal, it is defeated that described Signal Analysis System just obtains the test machine corresponding with this clock signal Go out to test the signal output time of signal.
12. chip detecting methods as according to any one of claim 8~11, it is characterised in that described survey The test signal that test-run a machine provides includes voltage signal and/or current signal.
13. chip detecting methods as according to any one of claim 8~11, it is characterised in that described crystalline substance The clock signal that shaking provides includes square-wave signal.
CN201310574106.8A 2013-11-15 2013-11-15 Chip test system and chip detecting method Active CN103576079B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201310574106.8A CN103576079B (en) 2013-11-15 2013-11-15 Chip test system and chip detecting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201310574106.8A CN103576079B (en) 2013-11-15 2013-11-15 Chip test system and chip detecting method

Publications (2)

Publication Number Publication Date
CN103576079A CN103576079A (en) 2014-02-12
CN103576079B true CN103576079B (en) 2016-08-10

Family

ID=50048272

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310574106.8A Active CN103576079B (en) 2013-11-15 2013-11-15 Chip test system and chip detecting method

Country Status (1)

Country Link
CN (1) CN103576079B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115632755B (en) * 2022-12-19 2023-03-21 杭州加速科技有限公司 Method and device for detecting signal synchronism among business boards in ATE (automatic test equipment)

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60247942A (en) * 1984-05-23 1985-12-07 Advantest Corp Testing device for semiconductor memory
US6009530A (en) * 1994-11-29 1999-12-28 Gpt Limited Real time clock synchronization in a telecommunications network
JP3057877B2 (en) * 1992-01-24 2000-07-04 安藤電気株式会社 IC tester synchronization circuit
CN1464980A (en) * 2001-06-07 2003-12-31 株式会社艾德温特斯特 Method for calibrating semiconductor test instrument
US6931338B2 (en) * 2003-01-07 2005-08-16 Guide Technology, Inc. System for providing a calibrated path for multi-signal cables in testing of integrated circuits
CN101093244A (en) * 2006-06-22 2007-12-26 夏普株式会社 Semiconductor device, semiconductor device testing method, and probe card
JP2008032543A (en) * 2006-07-28 2008-02-14 Yokogawa Electric Corp Semiconductor integrated circuit testing apparatus and method
CN101494088A (en) * 2008-01-25 2009-07-29 恩益禧电子股份有限公司 Semiconductor integrated circuit device and method of testing same
CN103018649A (en) * 2012-11-26 2013-04-03 西北核技术研究所 Automatic signal delay compensation method and system suitable for radiation effect test

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60247942A (en) * 1984-05-23 1985-12-07 Advantest Corp Testing device for semiconductor memory
JP3057877B2 (en) * 1992-01-24 2000-07-04 安藤電気株式会社 IC tester synchronization circuit
US6009530A (en) * 1994-11-29 1999-12-28 Gpt Limited Real time clock synchronization in a telecommunications network
CN1464980A (en) * 2001-06-07 2003-12-31 株式会社艾德温特斯特 Method for calibrating semiconductor test instrument
US6931338B2 (en) * 2003-01-07 2005-08-16 Guide Technology, Inc. System for providing a calibrated path for multi-signal cables in testing of integrated circuits
CN101093244A (en) * 2006-06-22 2007-12-26 夏普株式会社 Semiconductor device, semiconductor device testing method, and probe card
JP2008032543A (en) * 2006-07-28 2008-02-14 Yokogawa Electric Corp Semiconductor integrated circuit testing apparatus and method
CN101494088A (en) * 2008-01-25 2009-07-29 恩益禧电子股份有限公司 Semiconductor integrated circuit device and method of testing same
CN103018649A (en) * 2012-11-26 2013-04-03 西北核技术研究所 Automatic signal delay compensation method and system suitable for radiation effect test

Also Published As

Publication number Publication date
CN103576079A (en) 2014-02-12

Similar Documents

Publication Publication Date Title
EP1582885B1 (en) Test system with differential signal measurement
CN101718851B (en) Calibrating apparatus for electronic transducer calibration instrument based on alternating current bridge balance principle
US6167001A (en) Method and apparatus for measuring setup and hold times for element microelectronic device
CN105759195A (en) Setup-hold time test system and setup-hold time test method based on fine phase modulation
CN104008033A (en) System and method for I2C bus testing
CN105336635B (en) The bearing calibration of CD-SEM device, method and CD-SEM device using CD-SEM device
CN103267940A (en) Multi-module parallel test system and multi-module parallel test method
CN103675652B (en) A kind of ADC chip testing based on non-homogeneous clock and collecting method
US9341658B2 (en) Fast on-chip oscillator trimming
CN103576079B (en) Chip test system and chip detecting method
CN205880145U (en) Test panel and testing arrangement are surveyed in TRL calibration of passive link
CN103576080A (en) Chip scanning voltage testing method
CN104536282A (en) Time-digital converter and time measuring device and method
JP2003262664A (en) Semiconductor integrated circuit device and method for testing the same
US10520547B2 (en) Transition scan coverage for cross clock domain logic
CN104422801A (en) Load board, automated test equipment and IC test method
KR20100013322A (en) Electronic device and electronic device testing method
CN203688739U (en) Test system for ring oscillator
CN106990343B (en) The test method and system of electronic component
CN216595393U (en) Time delay testing device
CN104133367A (en) Circuit and method for extracting time interval parameters of clock signals to be measured
US9645195B2 (en) System for testing integrated circuit
CN201548680U (en) Electronic type mutual inductor calibrator calibrating apparatus based on alternating current electric bridge balancing principle
CN103592613B (en) Test rectifier, test system and method for testing
US7786718B2 (en) Time measurement of periodic signals

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant