JP3057877B2 - IC tester synchronization circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous circuit between a driver circuit of an IC tester and a decision circuit.

[0002]

2. Description of the Related Art A synchronous circuit between a driver circuit and a decision circuit of an IC tester according to the prior art will be described with reference to FIG. 4 is a pattern memory unit, 2 is a delay circuit, and 3 and 4
Denotes a flip-flop (hereinafter referred to as FF), 6 denotes a driver, 7 denotes a comparator, 8 denotes a judgment circuit, and 10 denotes a device.

A pattern address 11 is input to the pattern memory unit 1 shown in FIG. 4 at the timing of a synchronous clock 12, and pattern data 13 stored in the pattern memory unit 1 is output at a designated address. Output pattern data 1
3 is input to the driver 6, and pattern data 13 is added to the device 10 from the driver 6. The response output of the device 10 is input to the comparator 7, and the output of the comparator 7 is input to the determination circuit 8.

The synchronous clock 12 delayed by the delay circuit 2 is applied to the C terminals of the FFs 3 and 4, the pattern data 13 is input to the D terminal of the FF3, and the address data 14 is input to the D terminal of the FF4. You. FF3 is a comparator 7
And the pattern data 13 is input to the designated address of the judgment circuit 8 at the same time as the output. That is, the response output data input from the device 10 to the determination circuit 8 is stored in the pattern memory unit 1.
The timing is adjusted by the delay circuit 2 so as to be input to the determination circuit 8 in correspondence with the expected value data input to the determination circuit 8 from.

Next, a configuration diagram of an embodiment according to the prior art will be described with reference to FIG. The pattern memory unit 1 in FIG.
A, a pattern memory 1B and an FF 1C. FF1
The output of C is input to the driver modulation circuit 6A. The driver modulation circuit 6A is a circuit that modulates the output of the pattern memory 1B at the timing of the synchronous clock 12.

The output of the pattern memory unit 1 is input to the judgment circuit 8 as an expected value.
The data is held in the FF 3A at the timing of delaying the synchronous clock 12 by the delay time T1 of the delay circuit 2A, and the synchronous clock 12 delayed by the time T1 is further delayed by the delay time T2 of the delay circuit 2B.
B holds the data.

[0007] This is because the output data of the pattern memory 1B passes from the driver modulation circuit 6A to the driver 6, passes from the device 10 to the comparator 7, and is input to the determination circuit 8 at the same time as the expected value data. Circuit 8
This is a circuit for adjusting the time required for inputting the signal to the input terminal. Normally, the time is adjusted by combining a plurality of delay circuits. Therefore, the number of delay circuits and FFs is increased or decreased as necessary.
The FFs 4A to 4D provide an address for storing data in the determination circuit 8 to the determination circuit 8, and the address data 14 of the pattern address is, like the pattern data 13, the timing at which the synchronous clock 12 is delayed by the delay circuit. Is input to the judgment circuit 8.

Next, the operation of FIG. 5 will be described with reference to a time chart of FIG. FIG. 6A is a waveform diagram of the synchronous clock 12 inputting a clock to the pattern memory unit 1, and FIG. 6A is an output of the FF 1A inputting data to the pattern memory unit 1. As shown in FIG.
At this timing, the pattern address data N is input to the FF 1A. FIG. 6C shows the output of the FF 1C of the pattern memory unit 1, and the data (N) of the address N in the pattern memory 1B is output at the timing of n + 1 of the synchronous clock 12 in FIG.

FIG. 6D shows the waveform of the synchronous clock 12 delayed by the time T1 by the delay circuit 2A. Figure 6E is FF
3A, and outputs data (N) at the timing of the synchronous clock in FIG. In FIG. 6E, na of FIG.
Data (N) is output with a pulse of +1. FIG. 6A shows a waveform of the synchronous clock delayed by the time T2 from the synchronous clock of FIG. 6D by the delay circuit 2B. FIG. 6G shows the output of the FF 3B, which outputs data by the synchronous clock of FIG. In FIG. 6B, data (N) is output with the nb + 1 pulse shown in FIG.

As described above, in the conventional synchronization circuit, in order to synchronize the expected value data input to the determination circuit 8 with the response output data of the device 7, the data input from the pattern memory unit 1 to the determination circuit 8 is The synchronous clock 12 is given with a delay of a predetermined time and input to the determination circuit 8.

[0011]

In FIG. 4, a decision circuit 8 is shown.
In order to determine the timing of the expected value data, it is necessary to adjust the timing of the clock given to the FFs while confirming the setup time of the FF data and the synchronous clock. It is necessary to adjust the clock timing. An object of the present invention is to provide a circuit that can easily synchronize input data in the determination circuit 8 by first giving timing of expected value data to be supplied to the determination circuit 8.

[0012]

In order to achieve this object, according to the present invention, a delay circuit 2 for delaying a synchronous clock 12, a pattern address data 11 as an input, and an address designated by an output of the delay circuit 2 are provided. Memory unit 1 for outputting pattern data 13 of the
FF3 having the pattern data 13 of D as the D input and the output of the delay circuit 2 as the C input, the FF4 having the address data 14 of the pattern memory unit 1 as the D input and the output of the delay circuit 2 as the C input, The pattern data 13 of the part 1 is D
An FF5 that has an input and a synchronous clock 12 as a C input;
A driver 6 that receives the output of the FF 5 as an input and outputs pattern data 13 to the device 10, a comparator 7 that receives an output of the device 10 as an input, an output of the comparator 7 as a first input, and an output of the FF 3 as a first input. A determination circuit 8 for determining whether the device 10 is good or bad, and a time period until the pattern data 13 of the pattern memory unit 1 reaches the determination circuit 8 from the device 10. And the delay time of the delay circuit 2 is made equal.

[0013]

Next, the configuration of the synchronous circuit of the IC tester according to the present invention will be described with reference to FIG. Reference numeral 5 in FIG. 1 denotes an FF, and the other components are the same as those in FIG. The delay circuit 2 delays the synchronous clock 12. The pattern memory unit 1 receives the pattern address data 11 as input, and outputs pattern data 13 of the address specified by the output of the delay circuit 2. FF3
Is the pattern data 13 of the pattern memory unit 1 as a D input,
The output of the delay circuit 2 is a C input, the FF 4 has the address data 14 of the pattern memory unit 1 as a D input, and the output of the delay circuit 2 is a C input. The FF 5 receives the pattern data 13 of the pattern memory unit 1 as the D input, receives the synchronous clock 12 as the C input, the driver 6 receives the output of the FF 5 as the input, and outputs the pattern data 13 to the device 10. The connection relationship between the comparator 7, the determination circuit 8, the FF3, and the FF4 is the same as that in FIG. In FIG. 1, the time until the pattern data 13 of the pattern memory unit 1 arrives at the determination circuit 8 from the device 10 is equal to the delay time of the delay circuit 2. That is, the output of the pattern memory unit 1 is input to the FF 5 earlier than the timing of input to the FF 3 by the delay time T of the delay circuit 2, and adjusts the timing of data input to the determination circuit 8.

[0014]

FIG. 2 is a block diagram of the embodiment shown in FIG. In FIG. 2, the synchronous clock 12 is delayed by the delay circuits 2A and 2B, and the pattern memory unit 1 outputs the pattern data 13. The output data of the pattern memory unit 1 is supplied to the FF3A at the timing of the delayed synchronous clock.
To the FF 3B at the next timing.
Address data is sequentially transmitted from the FF 4A to the F at the timing of the synchronous clock 12 delayed by the delay circuit 2A from the FF 1A.
Input to F4B and FF4C.

Since the pattern data 13 and the address data 14 are a pair, the number of FFs to which the address data 14 is input is equal to the number of the FFs to which the pattern data 13 is input. In FIG. 2, there are FF4A to FF4C for FF1C, FF3A, and FF3B. The sum T = T1 + T2 of the delay times of the delay circuits 2A and 2B is obtained by inputting the pattern data 13 from the driver modulation circuit 6A to the device 10 via the driver 6, and from the device 10 to the comparator 7
To arrive at the decision circuit 8 through

Next, the operation of FIG. 2 will be described with reference to the time chart of FIG. 3A shows the pulse waveform of the synchronous clock 12, and FIG. 3A shows the synchronous clock waveform delayed by the time T2 in the delay circuit 2B. FIG. 3C shows the delay circuit 2.
3A is a waveform of a synchronous clock obtained by further delaying the clock of FIG. FIG. 3D shows the output waveform of the FF 1A. The address data M is output at the timing of nb in FIG.
Is input to the FF 1A.

FIG. 3E shows the output waveform of the FF1C.
The pattern data (M) at the address M of the pattern memory 1B is input at the timing of nb + 1. Fig. 3 shows FF3
A is the output waveform of A, and the pattern data (M) is input at the timing of nb + 2 in FIG. FIG. 3G shows the output waveform of the FF 3B. The pattern data (M) is input at the timing of nb + 3 in FIG.

FIG. 3C shows the output waveform of the FF 5A.
Pattern memory data (M) at the timing of nb + 2
Enter Here, the data input to FF5A is FF5A.
3A, but the timing of the clock is longer than that of the clock input to the FF 3A by the delay element 2A.
Faster by the delay time T1. FIG. 3 shows the output waveform of the FF 5B. The pattern memory data (M) is input at the timing of n + 3 in FIG. Here, the data input to the FF 5B is the data from the FF 5A, but the timing of the clock is the delay element 2B from the clock input to the FF 5A.
Is faster by the delay time T2.

The data input to the FF 5B is input to the device 10 via the driver 6 at the timing shown in FIG. 3A, and is input to the determination circuit 8 via the comparator 7 simultaneously with the output of the FF 3B.

[0020]

According to the present invention, in order to synchronize the fixed delay time T between the driver circuit of the IC tester and the comparator circuit, the determination reference timing of the comparator is first determined, and then the driver circuit side Is determined, the input data can be easily synchronized in the determination circuit.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a synchronous circuit of an IC tester according to the present invention.

FIG. 2 is a configuration diagram of the embodiment of FIG.

FIG. 3 is a time chart showing the operation of FIG. 2;

FIG. 4 is a configuration diagram of a synchronous circuit of an IC tester according to the related art.

FIG. 5 is a configuration diagram of the embodiment of FIG. 4;

FIG. 6 is a time chart showing the operation of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Pattern memory part 2 Delay circuit 3 FF (flip-flop) 4 FF 5 FF 6 Driver 7 Comparator 8 Judgment circuit 10 Device

Claims (1)

(57) [Claims] 1. A delay circuit for delaying a synchronous clock (12)
(2) and a pattern memory unit (1) that receives pattern address data (11) as input and outputs pattern data (13) of an address specified by an output of the delay circuit (2); and a pattern memory unit (1). And the pattern data (13) of
A first flip-flop (3) having the output of the delay circuit (2) as a C input, an address data (14) of the pattern memory section (1) as a D input, and an output of the delay circuit (2) as a C input. The second flip-flop (4) to be executed and the pattern data (13) of the pattern memory section (1) are input to D inputs,
A third flip-flop (5) having a synchronous clock (12) as a C input; and a driver (6) having an input of an output of the third flip-flop (5) and outputting a pattern data (13) to a device (10). ), A comparator (7) having an output of the device (10) as an input, an output of the comparator (7) as a first input, and an output of the first flip-flop (3) as a second input. A decision circuit (8) for judging whether the device (10) is good or bad, using the output of the second flip-flop (4) as a third input, and the pattern data (13) of the pattern memory unit (1) (Ten)
From the time it arrives at the decision circuit (8) and the delay circuit
(2) A synchronous circuit for an IC tester, wherein the delay times are equalized.