JP2000123597A - Semiconductor test device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor test device provided with a pattern generator which can generate easily a pattern corresponding to arrangement of a memory cell. SOLUTION: This device is provided with an address conversion means 350, first, generating successively even number address signals in which values of an address signals are doubled and outputting them, and generating successively odd number address signals in which values of an address signals are doubled and '1' is added to the result, and outputting them. Further the device is provided with a generated pattern reversing means 325 generating successively even inversion signals making one side of even number address signals from the address conversion means 350 as a function, reversing even number pattern signals generated by one side of a pattern generating means of pattern generating means of two systems by the even number inversion signals as the prescribed condition and outputting them, generating successively odd number inversion signals making the other side of odd number address signals from the address conversion means 350 as a function, reversing odd number pattern signals generated by the other side of a pattern generating means 350 of pattern generating means of two systems by the odd number inversion signals to the prescribed condition and outputting them.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a pattern generator for a semiconductor test device. In particular, the present invention relates to a pattern generator that multiplexes two generation patterns related to a memory address line and can supply a high-speed test pattern to a DUT.

[0002]

2. Description of the Related Art First, a conceptual configuration of a main part of a semiconductor test apparatus will be described with reference to FIG. Since the semiconductor test apparatus is well-known and well-known in the art, detailed description of the entire system is omitted. The main configuration is a pattern generator (PG) 1
50, waveform shaper (FC), and logical comparator (DC)
And a fail memory (FM). The main signals generated by the PG 150 include an address signal, a write data signal, a control signal, and an expected value. Note that the address signal is supplied to the DUT via the FC and the FM
And both address information is usually the same address information. In DC, the signal output from the DUT and the PG
Fail signals FD1 to FDn as a result of the pass / fail judgment by comparing with the expected value supplied from 150 are supplied to FM.
The FM has a fail storage memory corresponding to the address space of the DUT. The fail signal from DC is D
It is required that the data be stored at an address position in the FM corresponding to the fail address of the UT on a 1: 1 basis. As a result, as a result of performing the device test, referring to the contents of the memory for storing the fail in the FM, it is possible to perform a fail analysis on which address position and which data bit position of the DUT has failed.

[0003] Next, a main configuration of the pattern generator according to the present invention will be described with reference to FIG. The main components are a sequence generator 100 and an address signal generator 200.
, A data signal generator 300 and a control signal generator 400.

The sequence generator 100 sequentially generates sequence data 100 s enabling generation of an arbitrary test pattern corresponding to a device, and outputs the sequence data 100 s to the address signal generator 200, the data signal generator 300, and the control signal generator 400. Supply to This sequence data 10
0s is an address signal for accessing a memory provided in each of the three generation units.

The address signal generator 200 generates a pattern signal related to the X and Y addresses in the memory configuration of the DUT, and outputs the pattern signal to the FC, FM and data signal generators 30.
0. In the FC, a waveform-shaped or pin-multiplexed signal is supplied to the DUT through a driver circuit in accordance with the timing condition of the address IC pin of the DUT through the driver circuit, and in the FM, a fail signal as a pass / fail judgment result is transmitted. Used for the address of the fail memory to be stored. The data signal generation unit 300 generates a pattern signal related to write data, expected value data, and the like in the memory configuration of the DUT, and supplies this to FC and DC. The control signal generator 400 generates a pattern signal such as an R / W control signal (/ WE, / OE, / CE) and a DRE in the memory configuration of the DUT, and supplies the generated signal to the DUT or the like via the FC.

Next, the internal configuration of the data signal generator 300 will be described with reference to FIGS. 5, 6, and 7. FIG. The data signal generator 300 includes a data operation control memory 310 and a data generator 320, as shown in FIG.

The data operation control memory 310 is a memory means for storing operation instructions for enabling various operations by the data generation section 320 described later, and receives the sequence data 100s as an address input of the memory. , Control data 310s having read out the stored contents.
Is supplied to each unit of the data generation unit 320.

The main components of the data generator 320 include a first data generator 321a, a second data generator 321b,
Address function generator 322 and data topology controller 3
23, a first inversion unit 325a, and a second inversion unit 325b
And a first topology inversion unit 326a and a second topology inversion unit 326b. The data topology control unit 323
There is also a semiconductor test apparatus having a configuration that does not include the configuration and the topology inverting unit 326.

[0009] The first data generator 321a and the second data generator 321b are the same constituent elements, but have the same structure as that of the second test cycle.
When applying a test pattern to the DUT at twice the rate, F
For multiplexing in C, for example, the first data generator 321a
The side is used for generating even-numbered patterns, and the side of the second data generator 321b is used for generating odd-numbered patterns. Accordingly, control data 310s received from data operation control memory 310 receives individual signals. These two
The n output signals of the system data generator pass through the corresponding first inverting unit 325a, second inverting unit 325b, first topology inverting unit 326a, and second topology inverting unit 326b, and the first data signal 326as and , The second data signal 326
bs. The two output data are 2n data signals 300s.

The address function generator 322 generates data inversion information by using the input address line as a function. This is a lattice-like X, Y in an IC chip.
This facilitates generation of a test pattern focusing on the relationship between memory cells physically arranged on an address line and peripheral memory cells. To this end, it receives an address signal A200s from the address signal generator 200, receives the individual control data 310s and receives a predetermined test pattern corresponding to the X and Y addresses of the DUT, for example, a checker board (checkerboard), diagonal. , Etc., and generates and outputs inversion information for inversion. FIG. 6 is an explanatory diagram of this concept. In this example, X address = 4,
This is a case where a checkerboard-shaped generation pattern is generated in 16 memory cells in the address space where Y address = 4. The address function generator 322 generates 1-bit inversion information in which the even address in the X and Y addresses is "1" and the odd address is "0" (FIG. 6).
C) and supplies it to the data inversion means (see FIG. 6D). On the other hand, the first data generator 321a or the second data generator 321b may have a generation pattern of all "1" (see FIG. 6B). As a result, as shown in FIG. 6E, it is possible to easily generate a checkerboard-shaped generation pattern using the address signal as a function.

Next, depending on the type of DUT, due to the difference in the physical formation structure of the internal memory cell, the same write data may be charged by the memory cell, discharged, or by the row / column address. Some have different charge / discharge states. Even if the memory cell structure is physically different, the data topology control unit 323 performs inversion for allowing the target cell to logically charge or discharge a target charge without being aware of this. It generates information. For this purpose, data inversion information is generated using the input address signal as a function. That is, the address signal A2 from the address signal generator 200
In response to the individual control data 310s, the control unit 310 generates and outputs inversion information for inverting a predetermined address position corresponding to the X and Y addresses of the DUT. FIG. 7 illustrates this concept. In this example, a cell charged when an odd address in the X address is "0" (see FIG. 7B)
Assuming that the DUT is a DUT, the data topology control unit 323 generates inversion information that becomes “1” at an odd address in the X address (see FIG. 7D), and uses data inversion means (FIG. 7E).
Supply). On the other hand, the first data generator 321a or the second data generator 321b may have a generation pattern of all "1" (see FIG. 7C). As a result, a generation pattern in which all the memory cells are charged as shown in FIG. 7F can be easily generated. It should be noted that the condition for forming the charge / discharge of the memory cell charge is different not only in the address direction but also in a device developed for a plurality of bits of parallel data. Are supplied to the first topology inverting unit 326a and the second topology inverting unit 326b.

The first inverting section 325a receives the n-bit even pattern signal 32 from the first data generator 321a.
In response to 1as, the n-bit width data inverted by the address inversion signal 322s of the address function generation unit 322 is supplied to the first topology inversion unit 326a. Second
The same applies to the inversion unit 325b, and the second data generator 3
Odd pattern signal 321bs of n-bit width from 21b
Then, the n-bit width data inverted by the address inversion signal 322s of the address function generation unit 322 is supplied to the second topology inversion unit 326b.

The first topology inverting section 326 a
Upon receiving the n-bit width data from the inversion unit 325a, the data topology control unit 323 outputs the n-bit first data signal 326as inverted by the n-bit corresponding topology inversion signal 323s to the outside. The same applies to the second topology inversion unit 326b, and the second topology inversion unit 3
Receiving the n-bit data from 25b, the n-bit second data signal 326bs inverted by the n-bit corresponding topology inversion signal 323s of the data topology control unit 323 is output to the outside.

Next, an example of pattern generation corresponding to a high-speed memory device will be described with reference to FIG. In this example, write data is supplied to the DUT at twice the speed of the test period Trate. For this reason, 2 which occurs in the test cycle Trate
This is performed by a method of multiplexing the generation pattern of the system and supplying it to the DUT. In FIG. 8, an address signal generator 200
Signal A200s generated from the test period Trate
Assume that consecutive address values A0, A1, A2 are generated (see FIG. 8D). For example, synchronous D
A high-speed memory such as a RAM (SDRAM) has a burst addressing function, and after supplying a start address (see FIGS. 8A and 8B) first, it is necessary to continuously supply high-speed write data (see FIG. 8C). There is. Here, the continuous data cycle is assumed to be a 200 MHz cycle. On the other hand, on the pattern generator side, it is assumed that the test period Trate that can be generated is 100 MHz. In order to supply the above-mentioned high-speed continuous write data, it is necessary to generate two systems of write data from the PG, multiplex the two systems of write data by FC, and supply the multiplexed data to the DUT. That is, the first data generator 321a shown in FIG. 5 outputs the even data Di0, Di2,
The generation of the first data of Di4 (see FIG. 8F)
The data generator 321b is in charge of generating the second data (see FIG. 8G) of the odd data Di1, Di3 and Di5. And F
A signal obtained by multiplexing even-numbered data and odd-numbered data at C (FIG. 8J).
(See FIG. 2) to the I / O pins of the DUT.

By the way, the above-mentioned address function generator 3
22 and the data topology control unit 323 receive the same address signal A200s and generate an inverted signal. on the other hand,
Inside the DUT, an address signal twice as fast as the test cycle is automatically generated, and the multiplexed signal (see FIG. 8J) is received and written to corresponding memory internal addresses one after another. This is because the PG-side address function generator 322 and the data topology controller 323 receive the same address signal A200s and generate an inverted address 322s or a first / second data inverted by a topology inverted signal 323s. (Refer to FIGS. 8F and 8G) There is a problem in that there is no consistency and the normal data inversion cannot be performed in the arrangement relation of the addresses with the memory cells in the DUT. The generation of the double-speed address signal A200s from the address signal generation unit 200 in order to match the DUT means that the test period Trate of the semiconductor test device itself is doubled, which means that Is very difficult in practice because the apparatus becomes extremely expensive.

[0016]

SUMMARY OF THE INVENTION As described above,
In the case where write data or the like is supplied to the DUT at twice the speed of the test period Trate, a method of multiplexing two generation patterns generated in the test period Trate and supplying the multiplexed pattern to the DUT is performed. In this case, address inversion is performed. The address function generation unit 322 and the data topology control unit 323 that generate signals and topology inverted signals can not generate an inverted signal properly inverted due to not receiving the original double-speed address information. Become. This means that the DUT
The test pattern applied to is not the desired test pattern. In this regard, conventional pattern generators are not preferred and have practical difficulties. Therefore, the problem to be solved by the present invention is that it is easy to generate a pattern corresponding to the arrangement of the memory cells, or it is possible to generate a pattern corresponding to the difference in the topology of charge / discharge of the memory cells. Test period T with pattern generation
An object of the present invention is to provide a semiconductor test apparatus including a pattern generator capable of supplying a test pattern multiplexed at twice the rate to a DUT.

[0017]

First, in order to solve the above-mentioned problems, according to the structure of the present invention, an address signal generating section for generating a test pattern mainly related to an address line of a memory in a device under test. 200, a data signal generator 300 for generating test patterns mainly related to data lines of the memory in the DUT, and a control signal generator mainly responsible for generating test patterns related to write / read control lines of the memory in the DUT. The data signal generating unit 300 includes a data operation control memory 310 for storing operation instruction information and reads out the operation instruction information to generate a predetermined generation pattern. A data generating unit 320;
20 includes two patterns of pattern generating means (for example, a first data generator 321a and a second data generator 321b) per tester pin for multiplexing by a waveform shaper (FC). In the semiconductor test apparatus, the pattern generator includes a generation pattern inverting unit that receives an address signal A200s generated and output by the address signal generation unit 200 with respect to a generation pattern output from the generation unit, and inverts the generated signal in a predetermined manner. In the data generating section 320, in response to the address signal A200s generated and output by the address signal generating section 200, first, the even numbered address signals 350as obtained by multiplying the value of the address signal A200s by twice are successively generated and output. Second, the result of multiplying the value of the address signal A200s by a factor of two is
An address conversion means for successively generating and outputting one odd address signal 350bs, and one even address signal 350a from the address conversion means 350;
generating even inversion signals (for example, address inversion signal 322as or both inversion signals of address inversion signal 322as and topology inversion signal 323as) with s as a function,
One of the two pattern generators (for example, the first data generator 321) is used in response to the even-number inverted signal.
a) generates an even pattern signal 321as, inverts it by a first inverting unit 325a, or both inverting units of the first inverting unit 325a and the first topology inverting unit 326a, and outputs the inverted signal. Of the other odd address signal 350bs as a function (for example, the address inverted signal 322bs or the address inverted signal 32bs).
2bs and the topology inverted signal 323bs) are generated one after another, and the odd pattern signal 321 generated by the other pattern generating means (for example, the second data generator 321b) of the two systems of pattern generating means according to the odd inverted signal.
bs to the second inversion unit 325b or the second inversion unit 325b
And a second pattern inverting unit of the second topology inverting unit 326b. According to the above invention,
It is possible to easily generate a pattern corresponding to the arrangement of physical memory cells in the DUT, or to easily generate a pattern corresponding to a difference in charge / discharge topology of a memory cell depending on a device. A semiconductor test apparatus including a pattern generator capable of supplying a test pattern multiplexed at twice the test period Trate and having a pattern generation to the DUT with pattern generation can be realized.

FIG. 1 shows a solution according to the present invention. The generation pattern inversion means includes DU
First address function generator 3 for even addresses for inverting the generation pattern related to the address function of the X and Y memories of T
22a and a second address function generator 3 for odd addresses
22b, a first inversion unit 325a, and a second inversion unit 325b
A first data topology control unit 323a for an even address for inverting a generation pattern related to a topology address of charge / discharge of memory cell charges at X and Y memory addresses of the DUT, and a second data topology control unit 323b and the first topology inversion unit 326
a and a second topology inverting unit 326b for odd addresses.

FIG. 9 shows a solution according to the present invention. The generation pattern inversion means includes DU
First address function generator 3 for even addresses for inverting the generation pattern related to the address function of the X and Y memories of T
22a and a second address function generator 3 for odd addresses
22b, a first inversion unit 325a, and a second inversion unit 325b
The semiconductor test apparatus described above is characterized by comprising:

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings together with embodiments.

With respect to the present invention, an example of the internal configuration of the data signal generator 300 shown in FIG. 1 and the data signal generator 300 shown in FIG.
The operation will be described below with reference to a time chart example for explaining the operation of FIG. Elements corresponding to the conventional configuration are denoted by the same reference numerals.

The main configuration of the data generation section 320 of the present invention is such that an address conversion section 350 is added, and the first address function generation section 3 is replaced with the conventional address function generation section 322.
22a and a second address function generating section 322b, and further includes a first data topology control section 323a and a second data topology control section 323b with respect to the conventional data topology control section 323. Become.

The address conversion means 350 comprises a first address conversion means 350a and a second address conversion means 350b. The address conversion means 350 receives the address signals A200s of the test cycle Trate generated and output by the address signal generation section 200 one after another, and An address signal corresponding to twice the rate of Trate is generated and output. That is, one first address conversion means 350
a, the address signal A200s is received and the even address signal 350as resulting from doubling the value is sent to the first address function generator 322a and the first data topology controller 32.
3a. The other second address translation means 350b
In response to the address signal A200s, an odd address signal 350bs obtained by doubling the result of doubling this value is added to the second signal.
It is supplied to the address function generator 322b and the second data topology controller 323b.

The first address function generator 322a receives the even address signal 350as from the first address conversion means 350a, and inverts data using the input address line as a function in the same manner as in the prior art, that is, the first address function generator 322a. An address inversion signal 322as is generated and supplied to the first inversion unit 325a. The second address function generating section 322b is configured to
Odd address signal 35 from address conversion means 350b
Receiving 0ab, as in the conventional case, it generates inversion information of data using the input address line as a function, that is, generates an address inversion signal 322bs and supplies it to the second inversion unit 325b. As a result, there is obtained a great advantage that the write data corresponding to the address signal twice as fast as the test cycle internally generated by the DUT itself and multiplexed by the FC can be inverted and supplied. Therefore, even at a double speed of the test cycle, a target test pattern corresponding to X and Y addresses such as a checker board can be easily generated.

The first data topology control section 323a receives the even address signal 350as from the first address conversion means 350a and, in the same manner as in the prior art, makes the topology corresponding to the memory cell charge charge / discharge formation structure. An inverted signal 323as is generated and supplied to the first topology inverting unit 326a. The second data topology control unit 323b receives the odd address signal 350ab from the second address conversion means 350b, and in the same manner as in the related art, the topology inversion signal 323bs corresponding to the memory cell charge charge / discharge formation structure. Is generated and supplied to the second topology inverting unit 326b. As a result,
A great advantage is obtained in that the write data corresponding to the address signal twice as fast as the test cycle generated internally by the DUT in the DUT itself, which is multiplexed by the FC, can be supplied with inverted topology. Therefore, even at the double speed of the test cycle, a test pattern with an appropriate topology inverted corresponding to the X and Y addresses can be easily generated.

Next, the operation of the above configuration will be further described with reference to FIG. Here, the address signal generator 200
As in the case of FIG. 8, the address signal A200s from address values A0, A1,
A2 ,. is generated (see FIG. 2A). D
In the UT, an address at twice the test period is automatically generated.
0 receives the address signal A200s and doubles it to generate twice even address signals TA0, TA2, TA4, (see FIG. 2B). Odd address signals TA1, TA3, T obtained by adding +1 to the doubled even address signal.
A5, are generated (see FIG. 2C). This makes the DUT
An address signal corresponding to a double speed address automatically generated internally is obtained. As a result, the first data (see FIG. 2F) of the even data Di0, Di2, Di4 properly inverted by the even address is output from the PG, and the odd data Di1, D properly inverted by the odd address.
The second data of i3 and Di5 (see FIG. 2G) can be output from the PG. Therefore, there is obtained a great advantage that a pattern can be generated that is consistent with an address automatically generated in the DUT.

The means for realizing the present invention is not limited to the above embodiment. For example, in a semiconductor test apparatus having a configuration not including the data topology control unit 323 and the topology inverting unit 326 illustrated in FIG. 5, the configuration is realized by the configuration unit illustrated in FIG. In this case, the number of address inversion signals output from the first address function generator 322a and the second address function generator 322b is changed from 1 to n, and each line of the even / odd pattern signal is individually controlled. Can practically cope with topology control for devices of normal data topology that are not complicated.
In the above-described solution, the input function for inverting the memory address is a specific example. However, it is also possible to invert other parameters as a function. Providing two systems of parameter generation means corresponding to generation enables generation of a multiplexed and twice as fast test pattern. It goes without saying that the DUT can be applied not only to a high-speed memory IC but also to a system LSI that incorporates a high-speed memory and performs high-speed continuous writing.

[0028]

According to the present invention, the following effects can be obtained from the above description. As described above, according to the present invention, in applying a multiplexed test pattern to a DUT, a configuration is provided that enables generation of a pattern consistent with an address automatically generated in the DUT. A pattern with good consistency corresponding to the arrangement of the physical memory cells in the DUT can be generated, and a pattern with good consistency corresponding to the difference in the charge / discharge topology of memory cells depending on the device can be generated. .

[Brief description of the drawings]

FIG. 1 shows an example of the internal configuration of a data signal generator 300 according to the present invention.

FIG. 2 is a time chart example illustrating the operation of FIG.

FIG. 3 is a conceptual configuration diagram of a semiconductor test apparatus.

FIG. 4 is a configuration diagram of a main part of the pattern generator according to the present application.

FIG. 5 shows a conventional internal configuration example of a data signal generator 300 according to the present application.

FIG. 6 is a conceptual diagram illustrating data inversion using an address line as a function.

FIG. 7 is a conceptual diagram illustrating data inversion of charge / discharge of a memory cell charge using an address line as a function.

FIG. 8 shows an example of a time chart for supplying a test pattern to a DUT after being multiplexed and an example of a time chart for generating a test pattern corresponding to a high-speed memory device.

FIG. 9 is an example of the internal configuration of another data signal generation unit 300 according to the present invention.

[Explanation of symbols]

 Reference Signs List 100 sequence generator 150 pattern generator (PG) 200 address signal generator 300 data signal generator 310 data operation control memory 320 data generator 321a first data generator 321b second data generator 322 address function generator 322a first Address function generator 322b Second address function generator 323 Data topology controller 323a First data topology controller 323b Second data topology controller 325a First inverter 325b Second inverter 326 Topology inverter 326a First topology inverter 326b Second topology inversion unit 350 Address conversion unit 350a First address conversion unit 350b Second address conversion unit 400 Control signal generation unit DUT Device under test

Claims (3)

[Claims] 1. An address signal generator for generating a test pattern mainly for an address line of a memory in a device under test (DUT), and for generating a test pattern mainly for a data line of a memory in the DUT. A data signal generator,
A control signal generator for generating a test pattern mainly related to a write / read control line of a memory in the DUT, and a control signal generator in the pattern generator of the semiconductor test apparatus, wherein the data signal generator stores data for storing operation instruction information; It comprises an operation control memory and a data generator for reading out the operation instruction information and generating a predetermined generation pattern. In the data generator, two patterns per tester pin for multiplexing by a waveform shaper (FC) are provided. Generating means for inverting a pattern generated by the address signal generating section in response to an address signal generated and output by the address signal generating section with respect to a generated pattern output from the two systems of pattern generating means, and inverting the generated signal in a predetermined manner; In the semiconductor test apparatus provided in the device, an address generated and output by the address signal generating unit in the data generating unit In response to the received signal, first, an even number address signal obtained by multiplying the value of the address signal by two is successively generated and output, and second, an odd number obtained by adding +1 to a result obtained by multiplying the value of the address signal by two times Address conversion means for successively generating and outputting address signals; and generating successively inverted even number signals as a function of one of the even number address signals from the address conversion means, and generating two systems of patterns by the even number inverted signal. One of the means for generating a pattern inverts an even pattern signal generated by one of the means and outputs the inverted signal, and generates the odd inverted signal as a function of the other odd address signal from the address conversion means one after another. Generating pattern inverting means for inverting an odd pattern signal generated by the other pattern generating means of the two systems of pattern generating means in response to the inverted signal and outputting the inverted signal in a predetermined manner. Semiconductor test apparatus for the butterflies. 2. The generation pattern inversion means includes: a first address function generation unit for an even address for inverting a generation pattern related to an address function of an X, Y memory of a DUT; and a second address function generation for an odd address. , A first inverting unit, and a second inverting unit, and a first for an even address for inverting a generation pattern related to a topology address of charge / discharge of memory cell charges in X, Y memory addresses of the DUT. A data topology control unit;
2. The semiconductor test apparatus according to claim 1, further comprising a data topology control unit, a first topology inversion unit, and a second topology inversion unit for odd addresses. 3. The generation pattern inversion means includes: a first address function generation unit for an even address for inverting a generation pattern related to an address function of an X and Y memory of a DUT; and a second address function generation for an odd address. The semiconductor test apparatus according to claim 1, further comprising a unit, a first inversion unit, and a second inversion unit.