JPH0330879U - - Google Patents

Info

Publication number
JPH0330879U
JPH0330879U JP9125589U JP9125589U JPH0330879U JP H0330879 U JPH0330879 U JP H0330879U JP 9125589 U JP9125589 U JP 9125589U JP 9125589 U JP9125589 U JP 9125589U JP H0330879 U JPH0330879 U JP H0330879U
Authority
JP
Japan
Prior art keywords
inspection
semiconductor integrated
functions
semiconductor
devices
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9125589U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP9125589U priority Critical patent/JPH0330879U/ja
Publication of JPH0330879U publication Critical patent/JPH0330879U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Testing Of Individual Semiconductor Devices (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図はこの考案の一実施例による半導体検査
装置のシステム構成を示すブロツク図、第２図は
第１図のシステムにおけるプログラムを示す概念
図、第３図は従来の半導体検査装置のシステム構
成を示すブロツク図である。 図において、１……テスタＡ、２……テスタＢ
、３，４……ＣＰＵ、５，６……メモリ、７，８
……計測回路、９……インタフエース、１０……
ＩＣハンドラ、１１……ＤＵＴ、１２……ＩＣハ
ンドラ測定部、１３……マルチプレクサ、１４，
１５……ケーブル、１６，１７……プログラムで
ある。なお、図中、同一符号は同一、又は相当部
分を示す。 Fig. 1 is a block diagram showing the system configuration of a semiconductor inspection device according to an embodiment of this invention, Fig. 2 is a conceptual diagram showing a program in the system of Fig. 1, and Fig. 3 is a system configuration of a conventional semiconductor inspection device. FIG. In the figure, 1...Tester A, 2...Tester B
, 3, 4... CPU, 5, 6... Memory, 7, 8
...Measurement circuit, 9...Interface, 10...
IC handler, 11...DUT, 12...IC handler measurement section, 13...Multiplexer, 14,
15... Cable, 16, 17... Program. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 半導体集積回路を検査する検査装置において、
半導体集積回路の機能や仕様に応じて検査機能の
異なる複数台の検査装置を組み合せ、それらの検
査装置を制御する装置を構成した事を特徴とする
半導体検査装置。 In inspection equipment that inspects semiconductor integrated circuits,
A semiconductor inspection device comprising a device that combines a plurality of inspection devices with different inspection functions according to the functions and specifications of a semiconductor integrated circuit, and controls the inspection devices.
JP9125589U 1989-08-02 1989-08-02 Pending JPH0330879U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9125589U JPH0330879U (en) 1989-08-02 1989-08-02

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9125589U JPH0330879U (en) 1989-08-02 1989-08-02

Publications (1)

Publication Number Publication Date
JPH0330879U true JPH0330879U (en) 1991-03-26

Family

ID=31640753

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9125589U Pending JPH0330879U (en) 1989-08-02 1989-08-02

Country Status (1)

Country Link
JP (1) JPH0330879U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004111029A (en) * 2002-08-30 2004-04-08 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit and memory testing method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6283678A (en) * 1985-10-09 1987-04-17 Hitachi Ltd Test pattern generator

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6283678A (en) * 1985-10-09 1987-04-17 Hitachi Ltd Test pattern generator

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004111029A (en) * 2002-08-30 2004-04-08 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit and memory testing method

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