JPS63188949U - - Google Patents
Info
- Publication number
- JPS63188949U JPS63188949U JP8168187U JP8168187U JPS63188949U JP S63188949 U JPS63188949 U JP S63188949U JP 8168187 U JP8168187 U JP 8168187U JP 8168187 U JP8168187 U JP 8168187U JP S63188949 U JPS63188949 U JP S63188949U
- Authority
- JP
- Japan
- Prior art keywords
- input
- pad
- output circuit
- used during
- signal pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 3
- 230000002093 peripheral effect Effects 0.000 claims 1
- 238000009792 diffusion process Methods 0.000 description 3
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Description
第１図〜第５図は本考案の一実施例、第６図と
第７図は本実施例による一回路例、第８図〜第１
４図は従来例および第１５図は本従来例による一
回路例をそれぞれ示す。
１…半導体基板、２，３２，５５〜６１，１０
２〜１０６…入出力回路ブロツク、３…基本セル
、４…電源固定パツド、５…グランド固定パツド
、６，４０，６２，８８…入力信号パツド、７，
１２，１７，１９，２７，２９，４１，４４，４
６…接続孔、８，４２…入力接続配線、９，９７
…入力バツフア、１０…入力バツフア引出し線、
１１，２１，３１，４８…電源接続配線、１３，
８０…電源線、１４，１８，２８，４５…グラン
ド接続配線、１５，８１…グランド線、１６，２
６，４３，６３，８９…グランドパツド、２０，
３０，４７，６７，９４…電源パツド、２２…出
力バツフア引出し線、２３，７７〜７９，９８〜
１０１…出力バツフア、２４，５０…出力接続配
線、２５，４９，６４〜６６，６８，９０〜９３
…出力信号パツド、３３…Ｐ＋型拡散層、３４，
３５…Ｐチヤネルゲート電極層、３６…Ｐ型島拡
散層、３７…Ｎ＋型拡散層、３８，３９…Ｎチヤ
ネルゲート電極層、５１，５３…８ビツトカウン
タ、５２…排他的論理和回路、５４…ラツチ、６
９…パツケージ、７０〜７６，１１０〜１１４…
内部リード。
Figures 1 to 5 are one embodiment of the present invention, Figures 6 and 7 are examples of circuits according to this embodiment, and Figures 8 to 1
FIG. 4 shows a conventional example, and FIG. 15 shows an example of a circuit according to this conventional example. 1...Semiconductor substrate, 2,32,55-61,10
2 to 106... Input/output circuit block, 3... Basic cell, 4... Power supply fixing pad, 5... Ground fixing pad, 6, 40, 62, 88... Input signal pad, 7,
12, 17, 19, 27, 29, 41, 44, 4
6... Connection hole, 8, 42... Input connection wiring, 9, 97
...Input buffer, 10...Input buffer leader line,
11, 21, 31, 48...Power connection wiring, 13,
80... Power supply line, 14, 18, 28, 45... Ground connection wiring, 15, 81... Ground line, 16, 2
6,43,63,89...Grand pad, 20,
30,47,67,94...Power pad, 22...Output buffer lead wire, 23,77~79,98~
101... Output buffer, 24, 50... Output connection wiring, 25, 49, 64-66, 68, 90-93
...output signal pad, 33...P + type diffusion layer, 34,
35...P channel gate electrode layer, 36...P type island diffusion layer, 37...N + type diffusion layer, 38, 39...N channel gate electrode layer, 51, 53...8 bit counter, 52... exclusive OR circuit, 54...Latch, 6
9...Package, 70-76, 110-114...
Internal lead.
Claims (1)
および供用時に使用される入出力回路ブロツクを
配置したマスタースライス方式の半導体集積回路
装置において、 前記入出力回路ブロツクに、出力信号パツドま
たは入力信号パツドとグランドパツドまたは電源
パツドとの各一つを近接して設け、 前記試験時に使用される入出力回路ブロツクに
あつては、前記試験時と前記供用時とで前記出力
信号パツドまたは前記入力信号パツドと前記グラ
ンドパツドまたは前記電源パツドとを切替え接続
して外部に引出すようにしたことを特徴とする半
導体集積回路装置。[Claims for Utility Model Registration] In a master slice type semiconductor integrated circuit device in which input/output circuit blocks used during testing and use of the basic cell unit are arranged in the outer peripheral area of the basic cell unit, the input/output circuit block In the case of an input/output circuit block used during the test, an output signal pad or an input signal pad and a ground pad or power supply pad are provided in close proximity to each other, and the input/output circuit block used during the test and the use 1. A semiconductor integrated circuit device, characterized in that an output signal pad or the input signal pad and the ground pad or the power supply pad are switched and connected so as to be drawn out to the outside.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8168187U JPS63188949U (en) | 1987-05-27 | 1987-05-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8168187U JPS63188949U (en) | 1987-05-27 | 1987-05-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63188949U true JPS63188949U (en) | 1988-12-05 |
Family
ID=30933642
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8168187U Pending JPS63188949U (en) | 1987-05-27 | 1987-05-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63188949U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1992002043A1 (en) * | 1990-07-23 | 1992-02-06 | Seiko Epson Corporation | Semiconductor integrated circuit device |
| JP2007335486A (en) * | 2006-06-13 | 2007-12-27 | Sharp Corp | Semiconductor integrated circuit |
-
1987
- 1987-05-27 JP JP8168187U patent/JPS63188949U/ja active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1992002043A1 (en) * | 1990-07-23 | 1992-02-06 | Seiko Epson Corporation | Semiconductor integrated circuit device |
| JP2007335486A (en) * | 2006-06-13 | 2007-12-27 | Sharp Corp | Semiconductor integrated circuit |
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