JPH11203159A - Interface device, parallel data synchronous circuit and parallel data synchronizing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an interface device which appropriately performs input and output of parallel data against the acceleration of data transfer due to the rising of a clock signal frequency. SOLUTION: In a test sequence that tests whether or not a clock signal latches the data of the same address to parallel data in the same timing, a test data generation circuit 2 outputs a test signal which makes one clock of a clock signal (CK) an H level and the other an L level and it is latched by a clock signal at a flip-flop 4. An output signal of the flip-flop 4 is latched by the hold signal at flip-flop 6 and a signal that is held by the flip-flop 6 is outputted to a switch 7 as a control signal which selects either in output signals of the flip-flop 4 and 5 at the time of data access.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an interface device for inputting / outputting data between devices, a parallel data synchronization circuit and a parallel data synchronization method used for the interface device.

[0002]

2. Description of the Related Art Generally, in an interface device for inputting and outputting data (reading and writing of data) between a device and a memory, data access to an access target, which is a device or a memory, is synchronized with a clock signal. Configured to run.

In recent years, the operating frequency of the CPU has been increased and the processing capacity has been further improved. However, with the improvement in the processing capacity of the CPU, the amount of processed data has been increased, and a large amount of data can be transferred at high speed. Thus, it is required to increase the data transfer speed. In order to increase the data transfer speed, in the interface device, a method of increasing the frequency of the clock signal is considered. However, as the frequency of the clock signal increases, the setup time and the hold time of the clock signal become shorter. That is, the timing margin for data access becomes short, and it is difficult to secure a timing margin for stable data access. Therefore, it is very difficult to meet the demand for increasing the data transfer rate by increasing the frequency of the clock signal.

Therefore, as a means for solving the above problem, a clock phase adjusting circuit (Japanese Patent Laid-Open No. 9-185427)
Publication).

An interface device incorporating the clock phase adjusting circuit will be described with reference to FIG. FIG. 5 is a block diagram showing a configuration of an interface device for inputting and outputting data between a conventional device and a memory.

As shown in FIG. 5, this interface device converts a clock signal input from the outside into a clock signal having a frequency which is N times as high as a PLL (Phase locked signal).
oop) circuit 11, and the clock signal output from the PLL circuit 11 is input to the clock phase adjustment circuit 300 and each of the flip-flops 20, 21, and 22 via the buffer 12. The clock phase adjustment circuit 300
An inverter 13 for inverting the phase of the input clock signal by 180 degrees and outputting the same, and four delays for shifting the phase of the clock signal input from the inverter 13 to a predetermined phase and outputting clock signals having different phases, respectively And a selector 15 that receives clock signals of different phases from the delay units 14 and selects and outputs one clock signal from the input clock signals based on the phase selection signal. With such a configuration,
The clock phase adjustment circuit 300 inverts and shifts the phase of the clock signal serving as an operation reference by 180 degrees, and selects and outputs a clock signal having a corresponding phase. This clock signal is input to the SDRAM 23 via the buffer 16 as an external clock signal.

The flip-flop 20 latches an externally input address signal, and outputs the address signal in synchronization with a clock signal input via the buffer 12. The output address signal is input to the SDRAM 17 via the buffer 17. The flip-flop 21 latches externally input write data,
The write data is output in synchronization with the clock signal input via the buffer 12. The output write data is input to the SDRAM 17 via the buffer 18. The flip-flop 22 latches the read data input from the SDRM 23 via the buffer 19,
The read data is output in synchronization with the clock signal input via the buffer 12. The output write data is sent to the outside.

In this interface device, a phase test sequence for executing an appropriate data access is executed, and a clock signal of an appropriate phase is selected by a selector 15 based on a result of the execution of the phase test sequence.
Specifically, when execution of the phase test sequence is instructed, the SDRAM 23 is executed by the phase test sequence.
Data access is performed on a trial basis using a plurality of clock signals with different phases, and a clock signal of an appropriate phase is selected from each clock signal based on the result of the trial based on the phase selection signal. I do.

By selecting a clock signal having an appropriate phase in this way, data can be latched by flip-flops 20, 21, 22 on the interface device side in response to a difference in skew due to a variation in quality of circuit elements. Setup time and hold time necessary to perform

[0010]

However, when data to be input / output is parallel data, a delay of a different value may exist in each data line. In the interface device for inputting and outputting parallel data,
For example, as shown in FIG. 6A, when the time τ1 and τ2 are secured as the setup time and the hold time with respect to the time T1 which is the cycle of the clock signal, a delay of a different value exists in each data line. It is assumed that a timing margin for executing stable data access to parallel data to be executed can be secured.

Here, in order to increase the data transfer speed,
Considering an increase in the frequency of the clock signal, the time T1, which is the period of the clock signal, becomes a shorter time T2.
When it is necessary to secure 1, τ2, it is difficult to latch the data at the same address of each data line at the same clock signal timing with respect to the parallel data having different values of delay in each data line. For example, as shown in FIG. 3A, each DATA (a), DATA
When (b), DATA (c), and DATA (d) have different phases, each of DATA (a), DATA (b), DATA at the same clock signal timing.
The (N) th data is latched for (c), the (N-1) th data is latched for DATA (c), and the data at the same address on each data line is the same clock signal. Is not latched at the timing of. Therefore,
When the frequency of the clock signal is increased to increase the data transfer rate for parallel data, it is difficult to secure a timing margin for performing stable data access to parallel data, and parallel data input / output is appropriate. Can not be done.

An object of the present invention is to provide an interface device, a parallel data synchronizing circuit, and a parallel data synchronizing method capable of appropriately performing input and output of parallel data for speeding up data transfer by increasing the frequency of a clock signal. Is to provide.

[0013]

According to the first aspect of the present invention,
In order to input and output data between devices, n-bit parallel data transferred from one of the devices to the other is received, the received parallel data is latched by a clock signal, and the latched parallel data is An interface device for synchronizing and outputting to the other of the devices, test data generating means for generating n-bit test parallel data in which one clock of the clock signal is at a high level and the other is at a low level; First latch means for latching each data of the first latch means with a clock signal, second latch means for receiving each output data of the first latch means as an input, and latching with the clock signal, and the first and second latches Means for inputting each output data, and as the data of the parallel data, the first data
Switch means for selecting and outputting one of the output data of the first and second latch means, and holding means for holding each output data of the first latch means;
A test sequence for inserting the test parallel data at the time of non-data access and testing whether or not the same address data is latched at the same timing by the clock signal with respect to the n-bit parallel data is executed. Each output data of the first latch means during the sequence execution period is held by the holding means, and at the time of data access, each output during the test sequence execution period of the first latch means held by the hold means is held. The operation of the switch means is controlled based on data.

According to a second aspect of the present invention, in the interface device according to the first aspect, the first latch means held by the hold means for each data of the parallel data at the time of the data access. When the output data during the test sequence execution period is at a low level, the output data of the first latch means is selected by the switch means, and the test sequence of the first latch means held by the hold means is selected. When the output data during the execution period is at a high level, the output data of the second latch means is selected by the switch means.

The third aspect of the present invention provides the first or second aspect.
The interface device according to claim 1, further comprising an instruction unit that instructs the test parallel data generation unit to generate the parallel data, and an instruction unit that instructs start of execution of the test sequence, wherein the test parallel data generation unit and the instruction unit include: It is characterized in that it is incorporated in any one of the devices.

According to a fourth aspect of the present invention, there is provided a parallel data synchronizing circuit used in an interface device for inputting and outputting data between devices, wherein the parallel data synchronizing circuit receives n-bit parallel data transmitted and received between the devices. A parallel data synchronizing circuit for latching the received parallel data with a clock signal and synchronizing and outputting the latched parallel data, wherein one clock of the clock signal is at a high level and the other is at a low level. Test data generating means for generating test parallel data, first latch means for latching each piece of the parallel data with a clock signal, and inputting each output data of the first latch means for latching with the clock signal A second latch means for receiving output data of the first and second latch means; Switch means for selecting and outputting one of the output data of the first and second latch means as each data of the parallel data; and holding means for holding each output data of the first latch means. Executing a test sequence for inserting the test parallel data during non-data access and testing whether or not the same address data is latched at the same timing by the clock signal with respect to the n-bit parallel data; Each output data of the first latch means during the test sequence execution period is held by the holding means, and at the time of data access, each output data of the first latch means held by the hold means during the test sequence execution period The operation of the switch means is controlled based on the output data.

According to a fifth aspect of the present invention, in the parallel data synchronization circuit according to the fourth aspect, the first latch means held by the hold means for each of the parallel data at the time of the data access. When the output data during the test sequence execution period is low level, the output data of the first latch means is selected by the switch means, and the test of the first latch means held by the hold means is performed. When the output data during the sequence execution period is high level,
The output data of the second latch means is selected by the switch means.

According to a sixth aspect of the present invention, there is provided a parallel data receiving means for receiving n-bit parallel data transferred between devices, latching the received parallel data with a clock signal, and synchronizing and outputting the latched parallel data. In the data synchronization method, during non-data access, n-bit test parallel data in which one clock of the clock signal is set to a high level and the other is set to a low level is generated, and the test parallel data is inserted to generate the n-bit parallel data. Executing a test sequence for testing whether or not the data at the same address is latched at the same timing by the clock signal, and latching each data of the test parallel data with a clock signal by first latch means;
Each output data of the first latch means is held by the hold means, and each output data of the first latch means is held by the hold means during the test sequence execution period. Latching each data of the parallel data with a clock signal, latching each output data of the first latch with the clock signal as input, and latching with the clock signal by a second latch. The first held in
And selecting and outputting one of the output data of the first and second latch means as each data of the parallel data based on each output data of the latch means during the test sequence execution period. .

According to a seventh aspect of the present invention, in the parallel data synchronizing method according to the sixth aspect, the first latch means held by the hold means for each of the parallel data during the data access. When the output data during the test sequence execution period is low level, the output data of the first latch means is selected by the switch means, and the test of the first latch means held by the hold means is performed. When the output data during the sequence execution period is high level,
The output data of the second latch means is selected by the switch means.

[0020]

Embodiments of the present invention will be described below with reference to the drawings.

First, the basic principle of the parallel data synchronization method in the interface device of the present invention will be described with reference to FIG. FIG. 1 is a block diagram showing a basic configuration of a parallel data synchronization circuit in an interface device according to the present invention. Here, an example of an interface for transferring data processed or generated inside a personal computer as parallel data to an external device is taken as an example, and one data line of the parallel data is represented by the parallel data synchronization of the present invention. The basic principle of the method will be described.

As shown in FIG. 1, the personal computer includes an interface 200 for inputting and outputting data between the transmission circuit 100 and an external device (not shown). The transmission circuit 100 includes a test data generation circuit 2 that generates a test signal based on a test start signal, and a parallel data output circuit 1 that selectively outputs a test signal generated from the test data generation circuit 2 and generated parallel data. And Here, the test signal refers to one clock of the clock signal (CK) as H, as described later.
A signal whose other level is L level.

The interface 200 includes a flip-flop 4 for latching and outputting parallel data input from the parallel data output circuit 1 with a clock signal, and a flip-flop 5 for latching and outputting the output signal of the flip-flop 4 with a clock signal. And a switch 7 for inputting output signals of the flip-flops 4 and 5 and selecting and outputting one of the input output signals.
And a flip-flop 6 for inputting and holding the output signal of the flip-flop 4 during non-data access.

At the time of non-data access, a test sequence for inserting the test signal described above and testing whether or not data at the same address is latched at the same timing by a clock signal with respect to parallel data is executed. Is set to When executing this test sequence, first, a test start signal is input to the test data generation circuit 2, and the test data generation circuit 2 generates the above-described test signal. The generated test signal is output to the interface 200 via the parallel data output circuit 1.

In the interface 200, the test signal is latched by the flip-flop 4 with the clock signal. The output signal of the flip-flop 4 is input to the flip-flop 6, and the flip-flop 6 latches the output signal of the flip-flop 4 according to the hold signal output from the test data generation circuit 2. The signal held by the flip-flop 6 is output as a control signal for the selection operation of the switch 7 at the time of data access.

The output timing of each signal during execution of the test sequence will be described with reference to FIG. FIG. 2 is a timing chart showing the output timing of each signal when the test sequence is executed in the interface of FIG.

When a test start signal is input, FIG.
As shown in FIG. 2B, the test data generating circuit 2 generates a signal in which one clock of a clock signal (shown in FIG. 2A) is at H level and the other is at L level. The generated test signal is output to the interface 200 via the parallel data output circuit 1.

In the interface 200, the test signal is latched by the flip-flop 4 with the clock signal. Here, considering the case where the flip-flop 4 latches the H-level signal portion of the test signal at the timing of N of the clock signal, the output signal of the flip-flop 4 becomes H-level as shown in FIG. , This H-level output signal is input to flip-flop 6. The flip-flop 6 latches the input output signal of the flip-flop 4 by a hold signal from the test data generation circuit 2. This hold signal is output so as to match the N-th falling timing of the clock signal, as shown in FIG. The output signal latched by the hold signal is an H level signal, and the H level signal is held in the flip-flop 6. The signal held in the flip-flop 6 is input to the switch 7 as a control signal. Here, as shown in FIG. 2D, the signal input to the switch 7 as the control signal is an H-level signal, and the switch 7 selects the output signal of the flip-flop 5 by the H-level control signal. The input terminal is switched to the H-side input terminal. As described above, when the flip-flop 4 latches the H-level signal portion of the test signal at the timing of the clock signal N, the test signal transmitted to the corresponding data line is latched at the predetermined timing of the clock signal. Therefore, it is determined that the delay for the data line is a delay allowed at the time of data access, and the switch 7 selects the output signal of the flip-flop 5. The delay allowed at the time of data access is such a delay that the data at the same address can be latched at the same clock signal timing for each piece of parallel data.

On the other hand, to the extent that the flip-flop 4 cannot latch the H-level signal portion of the test signal at the timing of N of the clock signal, the test signal sent to the corresponding data line 2 (e), the test signal latched by the flip-flop 4 at the timing N of the clock signal becomes an L-level signal portion. Accordingly, as shown in FIG. 2F, the output signal of the flip-flop 4 becomes L level, and this L-level output signal is input to the flip-flop 6. Flip-flop 6
Latches the input output signal of the flip-flop 4 with the hold signal output from the test data generation circuit 2 at the above-described timing. The output signal latched by the hold signal is an L level signal.
The level signal is held in the flip-flop 6. The L-level signal held in the flip-flop 6 is input to the switch 7 as a control signal. The switch 7 is shown in FIG.
As shown in (d), the input terminal is switched to the L-side input terminal so that the output signal of the flip-flop 4 is selected by the L-level signal input as the control signal. As described above, when the flip-flop 4 latches the L level signal portion of the test signal at the timing of the clock signal N, the test signal transmitted to the corresponding data line is not latched at the predetermined timing of the clock signal. Therefore, it is determined that the delay for the data line is an unacceptable delay at the time of data access, and the switch 7 selects the output signal of the flip-flop 4.

By executing this test sequence, it is possible to detect the presence or absence of a data delay based on a clock signal (whether or not the delay is acceptable) for each data line of the parallel data. When the test signal transmitted to the data line is not delayed with respect to the clock signal, the output signal of the flip-flop 5 is selected by the switch 7, and the test signal transmitted to the data line is delayed with respect to the clock signal. The switch 7 selects the output signal of the flip-flop 4. The switching state of the switch 7 is maintained at the time of subsequent data access.

Next, an interface for inputting and outputting 4-bit parallel data using the principle of the present invention will be described with reference to FIGS. FIG. 3 is a block diagram showing the configuration of the first embodiment of the interface device of the present invention, and FIG. 4 is a timing chart showing data input / output timing in the interface device of FIG.

In the present embodiment, the parallel data to be input / output is DATA (a), DATA (b), DAT
A description will be given of an interface 200 in which 4-bit data of A (c) and DATA (d) is input and output between the transmission circuit 100 and an external device (not shown). The transmission circuit 100 includes a test data generation circuit 2 and a parallel data output circuit 1, as described above.
Note that the parallel data output circuit 1 outputs test data,
DATA (a), DATA (b), D of parallel data
ATA (c) and DATA (d) are selectively transmitted to the interface 200 via the corresponding data lines.

The interface 200 includes the parallel data DATA (a), DATA (b), DATA (c),
It has a plurality of flip-flops and a plurality of switches provided for each data line for transmitting each data of DATA (d), and has a clock signal generator 9 for generating a clock signal serving as an operation reference. Specifically, for the data line of DATA (a), a flip-flop 4a that latches parallel data input from the parallel data output circuit 1 and outputs the latched data in synchronization with a clock signal, and an output signal of the flip-flop 4a And a switch 7a for inputting output signals of the flip-flop 4a and the flip-flop 5a and selecting and outputting one of the input output signals. A flip-flop 6a for inputting and holding an output signal of the flip-flop 4a at the time of data access is provided. Similarly, the flip-flop 4b, the flip-flop 5b, the switch 7b, and the flip-flop 6b are applied to the DATA (b) data line, and the flip-flop 4c, the flip-flop 5c, the switch are applied to the DATA (c) data line. 7c and flip-flop 6c
However, a flip-flop 4d, a flip-flop 5d, a switch 7d, and a flip-flop 6d are provided for the data line of DATA (d).

In the present embodiment, a test signal is transmitted to each data line to execute a test sequence, and the switches 7a, 7b, 7c, 7d for each data line are switched according to the execution result of the test sequence. Set the operating state.

Here, for example, as shown in FIG. 4A, DATA (a), DATA (b), DATA (b)
(C), each data line of DATA (d) has a different data delay.
The respective delays for the data lines TA (b) and DATA (d) are such that the data at the same address can be latched by the clock signal, and DATA (c)
Is assumed to be a delay in which it is impossible to latch data at the same address as the above-mentioned DATA with a clock signal. In this case, depending on the execution result of the test sequence, DATA (a), DATA
(B) The fact that the data at the same address can be latched by a clock signal for each data line of DATA (d), and that the data at the same address can be latched by a clock signal for the data line of DATA (c). It is detected that latching is impossible, and DATA (a), DATA (b), DATA
The switches 7a, 7b,
7d selects the H-side input terminal, and the switch 7c for the DATA (c) data line selects the L-side input terminal. The switching state of each of the switches 7a, 7b, 7c, 7d is maintained during the subsequent data access. Therefore, as shown in FIG. 4B, DATA (a), DAT
Output signals of flip-flops 5a, 5b and 5d are selected for data lines A (b) and DATA (d), and output signals of flip-flop 4c are selected for data lines of DATA (c). Being, DATA
(A), output (a), output (b), output (d) and D for each data line of DATA (b) and DATA (d)
The output (c) for the data line of the ATA (c) is
Each becomes the data of the same address.

As described above, in the present embodiment, a plurality of flip-flops and switches are provided for each data line for transmitting each data of the parallel data, and a test signal is transmitted to each of the data lines to perform a test sequence. And switches 7a, 7b, 7c, 7d for each data line corresponding to the execution result of the test sequence.
, The flip-flops 4a, 4b, 4c,
4d and one of the flip-flops 5a, 5b, 5c and 5d are selected. Therefore, in order to increase the data transfer speed by increasing the frequency of the clock signal, the delay of different values can be achieved with a small-scale circuit configuration. Can be performed in synchronization with the clock signal.

[0037]

As described above, according to the interface device of the first aspect, test data for generating n-bit test parallel data in which one clock signal of a clock signal is at a high level and the others are at a low level. Generating means, first latch means for latching each piece of parallel data with a clock signal, second latch means for receiving each output data of the first latch means as an input, and latching with a clock signal; Switch means for inputting each output data of the second latch means, selecting and outputting one of the output data of the first and second latch means as each data of the parallel data, and each of the first latch means. Holding means for holding the output data, and inserting test parallel data during non-data access so as to be compatible with n-bit parallel data. A test sequence for testing whether data at the same address is latched at the same timing by a clock signal, and holding each output data of the first latch means during the test sequence execution period by a holding means; At the time of data access, the operation of the switch means is controlled based on each output data of the first latch means held by the hold means during the test sequence execution period, so that the speed of data transfer is increased by increasing the frequency of the clock signal. In this case, parallel data input / output can be appropriately performed.

According to the interface device of the present invention, the output data of the first latch means held by the hold means during the test sequence execution period is provided for each of the parallel data at the time of data access. When the output data of the first latch means is selected by the switch means when the output data is at the low level, and when the output data of the first latch means held by the hold means during the test sequence execution period is at the high level, the switch means is selected. Selects the output data of the second latch means,
Synchronization of each data of the parallel data can be easily obtained.

According to the third aspect of the present invention, the interface device further includes instruction means for instructing the test parallel data generation means to generate parallel data and for instructing start of execution of the test sequence. The indicating means may be configured to be incorporated in any one of the devices.

According to the parallel data synchronizing circuit of the fourth aspect, test data generating means for generating n-bit test parallel data in which one clock of a clock signal is at a high level and the other is at a low level, and First latch means for latching each data with a clock signal, second latch means for receiving each output data of the first latch means as an input and latching with the clock signal, and each of the first and second latch means; Switch means for inputting output data and selecting and outputting one of the output data of the first and second latch means as parallel data, and a hold for holding each output data of the first latch means Means for inserting test parallel data at the time of non-data access so that data of the same address is applied to n-bit parallel data. A test sequence for testing whether or not the data is latched at the same timing by a clock signal. Each output data of the first latch means is held by the holding means during the test sequence execution. Since the operation of the switch means is controlled based on each output data during the test sequence execution period of the first latch means held by the hold means, the parallel data is prevented from increasing in the data transfer speed by increasing the frequency of the clock signal. Input and output can be performed properly.

According to the parallel data synchronizing circuit of the present invention, the output data during the test sequence execution period of the first latch means held by the holding means is provided for each of the parallel data at the time of data access. When the output data of the first latch means is selected by the switch means when it is at the low level, and when the output data of the first latch means held by the hold means during the test sequence execution period is at the high level, the switch is selected. Since the output data of the second latch means is selected by the means, synchronization of each data of the parallel data can be easily obtained.

According to the parallel data synchronizing method of the present invention, during non-data access, n-bit test parallel data is generated in which one clock of a clock signal is at a high level and the others are at a low level. To execute a test sequence for testing whether or not data of the same address is latched at the same timing by a clock signal with respect to n-bit parallel data. Is latched by a clock signal, each output data of the first latch means is held by the holding means, and each output data of the first latch means is held by the holding means during a test sequence execution period. Each of the parallel data is latched by a latch means with a clock signal, The latch means receives each output data of the first latch means as an input, latches the output data with a clock signal, and switches the parallel data based on each output data of the first latch means held by the hold means during a test sequence execution period. Output data of the first and second latch means is selected and output as each data of the first and second latch means, so that parallel data input / output is appropriate for speeding up data transfer by increasing the frequency of the clock signal. Can be done.

According to the parallel data synchronizing method of the present invention, for each data of the parallel data at the time of data access, the output data of the first latch means held in the hold means during the test sequence execution period. Is low level, the switch means
The output data of the second latch means is selected by the switch means when the output data of the first latch means held by the hold means during the test sequence execution period is at a high level. Therefore, synchronization of each data of the parallel data can be easily obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of a parallel data synchronization circuit in an interface device of the present invention.

FIG. 2 is a timing chart showing output timings of signals when a test sequence is executed in the interface of FIG. 1;

FIG. 3 is a block diagram illustrating a configuration of an interface device according to a first embodiment of the present invention.

FIG. 4 is a timing chart showing data input / output timings in the interface device of FIG. 3;

FIG. 5 is a block diagram showing a configuration of an interface device for inputting and outputting data between a conventional device and a memory.

FIG. 6 is a diagram showing a relationship between a setup time and a hold time with respect to a conventional clock signal.

[Explanation of symbols]

Reference Signs List 1 parallel data output circuit 2 test data generation circuit 4, 4a, 4b, 4c, 4d flip-flop (first
5, 5a, 5b, 5c, 5d flip-flops (second
6, 6a, 6b, 6c, 6d Flip-flop (holding means) 7, 7a, 7b, 7c, 7d Switch (switching means) 9 Clock signal generator 100 Transmission circuit 200 Interface

Claims (7)

[Claims] In order to input and output data between devices, n-bit parallel data output from one of the devices is received and latched by a clock signal, and the latched parallel data is synchronized to obtain the data of the device. An interface device for outputting to the other side, test data generating means for generating n-bit test parallel data in which one clock of the clock signal is at a high level and the other is at a low level; A first latch unit for latching the output data of the first latch unit, a second latch unit for latching the output data of the first latch unit with the clock signal, and an output unit of the first and second latch units. One of each of the output data of the first and second latch means as the parallel data. Switch means for selecting and outputting the data, and holding means for holding each output data of the first latch means. The test parallel data is inserted during non-data access to A test sequence for testing whether data at the same address is latched at the same timing by the clock signal is executed, and each output data of the first latch unit is held by the holding unit during the test sequence execution period. And an interface device for controlling the operation of the switch means based on each output data of the first latch means held in the hold means during the test sequence execution period at the time of data access. 2. For each data of the parallel data at the time of the data access, when output data of the first latch means held in the hold means during the test sequence execution period is at a low level,
The output data of the first latch means is selected by the switch means, and the first data held by the hold means is selected.
2. The interface device according to claim 1, wherein when the output data of the latch means during the test sequence execution period is at a high level, the switch means selects the output data of the second latch means. 3. The test parallel data generating means further includes an instruction means for instructing the test parallel data generating means to generate the parallel data and an instruction to start execution of the test sequence. 3. The interface device according to claim 1, wherein the interface device is incorporated in any one of the following. 4. A parallel data synchronization circuit for use in an interface device for inputting and outputting data between devices, the circuit receiving n-bit parallel data transmitted and received between the devices, and receiving the received parallel data. Is latched by a clock signal, and the parallel data synchronous circuit that synchronizes and outputs the latched parallel data generates n-bit test parallel data in which one clock of the clock signal is set to a high level and the others are set to a low level. Test data generating means, first latch means for latching each piece of the parallel data with a clock signal, and second latch means for receiving each output data of the first latch means and latching with the clock signal; , Each output data of the first and second latch means is inputted, and each data of the parallel data is inputted. Switch means for selecting and outputting one of the output data of the first and second latch means as data, and holding means for holding each output data of the first latch means. Executing a test sequence for inserting the test parallel data at the time of access and testing whether or not the same address data is latched at the same timing by the clock signal with respect to the n-bit parallel data; Each output data of the first latch means during the period is held by the hold means, and at the time of data access, each output data of the first latch means held by the hold means is output during the test sequence execution period. A parallel data synchronization circuit for controlling the operation of the switch means based on the control signal. 5. For each data of the parallel data at the time of the data access, when output data of the first latch means held by the hold means during the test sequence execution period is at a low level,
The output data of the first latch means is selected by the switch means, and the first data held by the hold means is selected.
5. The parallel data synchronization circuit according to claim 4, wherein when the output data of the latch means during the test sequence execution period is at a high level, the output data of the second latch means is selected by the switch means. . 6. A parallel data synchronization method for receiving n-bit parallel data transferred between devices, latching the received parallel data with a clock signal, and synchronizing and outputting the latched parallel data. At the time of data access, n-bit test parallel data in which one clock of the clock signal is at a high level and the others are at a low level is generated, and the test parallel data is inserted to the n-bit parallel data at the same address. A test sequence for testing whether or not data is latched at the same timing by the clock signal, and each data of the test parallel data is latched by a first latch means with a clock signal; Each of the output data is held by the holding means, and the test sequence The output data of the first latch means in the middle is held by the hold means, and at the time of data access, each data of the parallel data is latched by the first latch means by a clock signal; Then, each output data of the first latch means is input and latched by the clock signal, and each output data of the first latch means held by the hold means during the test sequence execution period is held by the switch means. Based on the first and second data as each data of the parallel data.
And selecting one of the output data of the latch means and outputting the selected data. 7. For each data of the parallel data at the time of the data access, when output data of the first latch means held by the hold means during the test sequence execution period is at a low level,
The output data of the first latch means is selected by the switch means, and the first data held by the hold means is selected.
7. The parallel data synchronizing method according to claim 6, wherein when the output data of the latch means during the test sequence execution period is at a high level, the output data of the second latch means is selected by the switch means. .