JP2004219336A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To facilitate a determination method for determining a condition of the presence of a trouble in every stress impression, in burn-in for a semiconductor device using a scanning chain. <P>SOLUTION: This device is provided with the scanning chain having an input terminal and an output terminal to input a rectangular data equal to a period of a scanning clock from the input terminal, an EOR circuit using, as inputs, output terminals of two flip-flops distant by an odd number of stages on the scanning chain, and a monitor terminal wired to an output of the EOR circuit. An oscilloscope or the like is connected to an output of the monitor terminal to display the output, the output of the monitor terminal is brought into an H output all the time when no trouble exists on the scanning chain, and is brought into an L output all the time when the trouble exists thereon. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a semiconductor device that applies a scan chain to a circuit that performs burn-in.
[0002]
[Prior art]
FIG. 12 shows a block diagram of a conventional semiconductor device.
In FIG. 12, 31 is an input terminal, 41 is an output terminal, and 2 is a burn-in target circuit.
[0003]
Next, a scan chain in this semiconductor device will be described.
The scan chain is a circuit (chain) in which an output of a flip-flop is connected to an input of another flip-flop in a scan test, and the connected flip-flops are connected in a daisy chain.
[0004]
The burn-in target circuit 2 in FIG. 12 shows one chain 21 in a daisy chain state and a combination circuit associated therewith. In the figure, reference numeral 60 denotes a flip-flop, which is input and output by a scan chain 21 between an input terminal 31 and an output terminal 41 and is tested. In the test using the scan chain, the flip-flops are connected in a daisy chain from the scan input terminal to the scan output terminal at the time of the test, so that the scan input terminal is used during the scan test (hereinafter referred to as scan shift). , Data can be set in an arbitrary flip-flop. When the setting of the data in the flip-flop is completed, the normal operation is performed, the combinational circuit is operated, the scan shift is performed again, and the signal from the scan output terminal is compared (compared). Thus, the circuit is inspected.
[0005]
Therefore, when performing burn-in, the circuit can be moved further by repeating scan shift and normal operation using a scan chain, so that a large stress can be applied.
[0006]
Although not shown in the figure, the scan clock terminal 5 is wired to the clock input terminals of all flip-flops, and the scan test is synchronized with a clock generated from the scan clock terminal 5 (hereinafter referred to as a scan clock). It works in the form.
[0007]
As a burn-in method for a semiconductor device, there is a method called monitor burn-in, in which a semiconductor device is operated under a high-temperature and high-voltage condition for a certain period of time to apply a stress, inspect the semiconductor device every time a certain stress is applied, and exclude a broken semiconductor device. As a simple method of realizing the monitor burn-in, when performing a scan shift operation, rectangular data of 101010... Is input from the input terminal 31 for each scan clock, and after a while, the same as the input data 101010. Is output, there is no failure on the scan chain (that is, the semiconductor device is not destroyed). If different data is output, there is a failure on the scan chain (that is, the semiconductor device is destroyed). Has been determined).
[0008]
Next, FIG. 13 shows a block diagram of another conventional semiconductor device.
In FIG. 13, reference numeral 31 denotes a first input terminal, 32 denotes a second input terminal, 41 denotes a first output terminal, 42 denotes a second output terminal, and 2 denotes a burn-in target circuit. is there.
[0009]
Next, as a description of this semiconductor device, the semiconductor device of FIG. 12 has two scan chains 21 and 22 corresponding to one scan chain 21.
[0010]
In FIG. 13, reference numeral 60 denotes a flip-flop, which is input / output by the scan chain 21 between the first input terminal 31 and the first output terminal 41, and is connected to the second input terminal 32 by the flip-flop. Input / output is performed in the scan chain 22 between the output terminals 42 of the second and the second output terminals 42, and the test is performed.
[0011]
The operation of the test using this scan chain is the same as that of the semiconductor device of FIG. Further, in the case of performing burn-in, the circuit can be moved further by repeating the scan shift and the normal operation using the scan chain, so that a large stress can be applied.
[0012]
With the recent increase in the scale and integration of semiconductor devices, there are two types of scan chains and two or more combinational circuits associated therewith, and some have three or more sets.
[0013]
The burn-in method of the semiconductor device is the same as that of the semiconductor device shown in FIG. 6 for each scan chain.
[0014]
[Patent Document 1]
JP-A-2000-357783 [Non-Patent Document 1]
Ed. Takuo Sugano et al., Dictionary of Semiconductors, Industrial Research Committee, 1999, p. 649, p. 1169
[0015]
[Problems to be solved by the invention]
However, in the above-described conventional configuration, it is necessary to create an expected value for determining whether the output signal from the output terminal 41 or the output terminal 42 is correct, and it is expensive and complicated to make the determination. Equipment was needed.
[0016]
The present invention has been made to solve the above-described problems, and has as its object to provide an inexpensive and simple burn-in inspection device.
[0017]
[Means for Solving the Problems]
In order to solve the above problem, a semiconductor device according to claim 1 of the present invention has an input terminal and an output terminal, and a scan chain in which rectangular data equal to a cycle of a scan clock is input from the input terminal. The circuit includes an EOR circuit that receives the output terminals of two flip-flops separated by an odd number of stages on the scan chain as inputs, and a monitor terminal that is wired to the output of the EOR circuit.
[0018]
The semiconductor device according to claim 2 of the present invention has an input terminal and an output terminal, and a scan chain in which rectangular data having a cycle of an integer multiple of 2 or more of a scan clock is input from the input terminal, Two AND circuits each having an output of two flip-flops separated by a different odd number of stages on the scan chain as its two inputs, two EOR circuits each having an output of the two AND circuits as inputs, A selector circuit having the two EOR circuits as inputs and a monitor terminal wired to an output of the selector circuit are provided.
[0019]
According to a third aspect of the present invention, in the semiconductor device according to the first aspect, an EOR circuit having an output terminal of two flip-flops separated by an odd number of stages on a scan chain as inputs, and wiring to an output of the EOR circuit. A scan chain having a plurality of monitored terminals respectively, wherein the EOR circuit inputs to the other EOR circuit two output terminals of the flip-flops separated by an odd number of stages on the scan chain; The output terminals of two flip-flops separated by different odd-numbered stages are input.
[0020]
A semiconductor device according to a fourth aspect of the present invention is the semiconductor device according to the first aspect, having an input terminal and an output terminal, and having an input terminal of an output terminal of two flip-flops separated by an odd number of stages on the scan chain. A plurality of scan chains each having a circuit and a monitor terminal wired to the output of the EOR circuit.
[0021]
According to a fifth aspect of the present invention, there is provided the semiconductor device according to the first aspect, further comprising a flip-flop having the output of the EOR circuit as an input, and having the output wired to the monitor terminal.
[0022]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
FIG. 1 shows a circuit configuration of a semiconductor device according to a first embodiment of the present invention. Note that the same components as those of the prior art shown in FIG. 12 are denoted by the same reference numerals. Therefore, in principle, the description thereof will be omitted.
[0023]
In FIG. 1, reference numeral 70 denotes an output terminal Qn of the n-th stage flip-flop and an output terminal Qn-1 of the (n-1) -th stage flip-flop (hereinafter, the output terminal of the k-th stage flip-flop is abbreviated as Qk). (Also referred to as an exclusive OR or an exclusive OR) circuit, and a monitor terminal 80 wired to the output of the EOR circuit 70.
[0024]
First, rectangular data of 101010... Is input from the input terminal 31 for each scan clock.
When there is no failure on the scan chain, this data propagates for each scan clock as Q1, Q2,..., And the state of Qn, Qn-1 when this data propagates to Qn. Considering this, there are two types (Qn, Qn-1) = (0, 1) and (1, 0). If the respective states are S1 and S2,... → S1 → S2 → S1 → S2 →. The state changes cyclically. FIG. 2 shows a timing chart in each state of this circuit.
[0025]
As shown in FIG. 2, when there is no failure, the output from the EOR circuit 70 is 1 in any case, and the output from the monitor terminal 80 is always H.
However, when there is a failure, for example, when the power supply is short-circuited at Q1, (Q1, Q2,..., Qn) = (1, 1,. 1) = (1, 1), and the monitor terminal 80 always outputs L.
[0026]
As described above, according to the first embodiment, the outputs from the flip-flops that are an odd number of stages apart from each other are input to the EOR circuit, the output of the EOR circuit is input to the monitor terminal, and the oscilloscope or the like is connected to the monitor terminal. Is connected to display the output, so that the output of the monitor terminal can always be H output if there is no failure in the scan chain, and can always be L output if there is a failure. Therefore, it is not necessary to create an expected value for determining whether an output signal from an output terminal is correct or not, and a complicated device for performing the determination is unnecessary, and it is possible to easily determine the presence or absence of a failure. This has the effect.
[0027]
(Embodiment 2)
FIG. 3 shows a circuit configuration of a semiconductor device according to the second embodiment of the present invention.
3, reference numeral 91 denotes an AND circuit that inputs Qn and Qn-1; 92, an AND circuit that inputs Qn-2 and Qn-3; 93, Qn-1 and Qn- 2, an AND circuit 94 having Qn-3 and Qn-4 as inputs, and an EOR circuit 71 having an output of an AND circuit 91 and an output of an AND circuit 92 as inputs. , 72 are EOR circuits that receive the output of the AND circuit 93 and the output of the AND circuit 94 as inputs, 100 is the data input that uses the output of the EOR circuit 71 and the output of the EOR circuit 72, and A selector circuit for selectively outputting the output of the EOR circuit 71 when the output of the selector 5 is a select input and the output of the EOR circuit 71 when the select input is 0, and a selector circuit 81 for selectively outputting the output of the EOR circuit 72 when the select input is 1. 10 A wired monitor terminal to the output of.
[0028]
First, rectangular data of 11001100... Twice the cycle of the scan clock is input from the input terminal 31 for each scan clock.
[0029]
When there is no failure on the scan chain, this data propagates as Q1, Q2,... Every two periods of the scan clock. Considering the states of Qn to Qn-4 when this data propagates to Qn,
(Qn, ..., Qn-4)
= (0,1,1,0,0),
(0,0,1,1,0),
(1, 0, 0, 1, 1),
(1,1,0,0,1),
If the respective states are S1, S2, S3, and S4, the states change cyclically in the order of... → S1 → S2 → S3 → S4 → S1 → S2 → S3 → S4 →. FIG. 4 shows a timing chart in each state of this circuit.
[0030]
71 is 1 in S2 and S4, 72 is 1 in S1 and S3, and the selector circuit 100 selects 71 when the scan clock is 0 and 72 when the scan clock is 1, so that the monitor terminal 81 is selected. , The H output is always output.
[0031]
However, when there is a failure, for example, when the power supply is short-circuited at Q1, (Q1,..., Qn) = (1, 1,..., 1), so that 91 = 92 = 93 = 94. = 1, that is, 71 = 72 = 0, and the L output is always output from the monitor terminal 81. Here, 91 = 1 is an abbreviation that the output of the AND circuit 91 is 1.
[0032]
As described above, according to the second embodiment, the outputs from the flip-flops that are an odd number of stages apart from each other are input to the respective AND circuits, and the outputs of the AND circuits different from each other are input to the two EOR circuits. The outputs of the two EOR circuits are input to a selector circuit, the output of the selector circuit is wired to a monitor terminal, and an oscilloscope or the like is connected to the monitor terminal to display the output. However, the selector circuit can select the output of the EOR circuit so that the output is always H if there is no failure on the scan chain and L if there is a failure. Input, a complicated device for creating an expected value for determining whether the output signal from the output terminal is correct or not and for making the determination is not necessary. It, there is an effect that it is possible to determine the presence of faults in a simple manner.
[0033]
In the above, the case of data having a period twice as long as the scan clock has been described. However, the above description is not particularly limited to twice, and is generalized by a combination of an AND circuit, an EOR circuit, and a multi-input selector circuit. The present invention can be applied to data having a cycle of an integral multiple.
[0034]
(Embodiment 3)
FIG. 5 shows a circuit configuration of a semiconductor device according to a third embodiment of the present invention.
In FIG. 5, reference numeral 70 denotes an EOR circuit inputting Qn and Qn-1; 80, a monitor terminal wired to the output of the EOR circuit 70; 73, input Qn and Qn-3; Reference numeral 82 denotes a monitor terminal wired to the output of the EOR circuit 73.
[0035]
First, rectangular data of 101010... Is input from the input terminal 31 for each scan clock.
[0036]
When there is no failure on the scan chain, this data propagates for each scan clock as Q1, Q2,..., And the state of Qn, Qn-1 when this data propagates to Qn. Considering this, there are two types (Qn, Qn-1) = (0, 1) and (1, 0). If the respective states are S1 and S2,... → S1 → S2 → S1 → S2 →. The state changes cyclically. FIG. 6 shows a timing chart in each state of this circuit.
[0037]
However, as shown in FIG. 6 (b), when multiple failures occur on the scan chain, that is, Qn is short-circuited to GND and Qn-1 is short-circuited to the power supply, and when there is no other failure, This data propagates every scan clock as Q1, Q2,.... Considering the state of Qn, Qn-1 when this data propagates to Qn, (Qn, Qn-1) = (0 Therefore, the output from the EOR circuit 70 is 1, and the H output is always output from the monitor terminal 80.
[0038]
However, as shown in FIG. 6A, even if there is no multiple failure, the H output is always output from the monitor terminal 80. Therefore, simply referring to the output of the monitor terminal 80 requires If there is no failure, an erroneous determination will be made. However, on the other hand, since Qn-3 changes to 101010 ..., the output of the monitor terminal 82 changes to HLHLHL ... so that the output of the monitor terminal 80 differs from the output of the monitor terminal 82. The above is an erroneous determination.
[0039]
As described above, according to the third embodiment, a scan having a plurality of EOR circuits each having an output terminal of a flip-flop that is an odd number of stages apart from each other and having a plurality of monitor terminals wired to the output of the EOR circuit is provided. A chain, wherein the EOR circuit receives, as inputs, an output terminal of a flip-flop which is input to the other EOR circuit and which is odd-numbered apart from each other, and an output of an odd-numbered flip-flop which is different from the odd-numbered stage. In the case where multiple failures occur, that is, Qn is short-circuited to GND and Qn-1 is short-circuited to the power supply, the output of the first monitor terminal incorrectly determines that there is no failure. By referring to the output of the monitor terminal in combination, there is an effect that the probability of erroneous determination can be reduced.
[0040]
(Embodiment 4)
FIG. 7 shows a circuit configuration of a semiconductor device according to the fourth embodiment of the present invention, and FIG. 8 is a timing chart of the semiconductor device according to the fourth embodiment of the present invention.
In FIG. 7, reference numeral 21 denotes a first scan chain, and reference numeral 22 denotes a second scan chain. The configurations of 21 and 22 are the same as those in the first embodiment.
[0041]
As shown in FIG. 8, rectangular data of 101010... Is input from the input terminal 31 and the input terminal 32 for each scan clock, as in the first embodiment, and the monitor terminal 80 and the monitor terminal If both of the 83s are always H output, it can be determined that there is no failure in either scan chain.
[0042]
As described above, according to the fourth embodiment, the scan chain including the EOR circuit having the input terminals of the flip-flops separated by an odd number of stages and the monitor terminal wired to the output of the EOR circuit is provided. Since a plurality of scan chains are connected to an oscilloscope or the like to display an output, if there is no failure on a plurality of scan chains, the output of each monitor terminal always becomes H output, and if there is a failure, The output can always be L, and even when a plurality of scan chains are provided, an expected value for determining whether or not the output signal from the output terminal is correct is generated, and the determination is performed. This eliminates the necessity of a complicated device, and it is possible to easily determine the presence or absence of a failure on each scan chain.
[0043]
Although the above description has been given of a semiconductor device having two scan chains, the present invention can be generalized and applied to an integer number of scan chains.
[0044]
(Embodiment 5)
FIG. 9 shows a circuit configuration of a semiconductor device according to a fifth embodiment of the present invention.
As shown in FIG. 9, the configuration is different from that of the first embodiment in that a flip-flop 110 is provided between the output of the EOR circuit 70 and the monitor terminal 80.
[0045]
When there is no failure on the scan chain, rectangular data of 101010... Is input from the input terminal 31 for each scan clock as in the first embodiment, and Qn, Qn when this data propagates to Qn. Considering the state of -1, there are two cases, (Qn, Qn-1) = (0, 1) and (1, 0). However, a realistic circuit generally has a time delay in many cases. For example, there may be a time Ts required for an output change of each flip-flop on the scan chain and a time difference Td between output changes of adjacent flip-flops. FIG. 10 shows an example having the former, and FIG. 11 shows an example having both the former and the latter. In any case, a time occurs that momentarily becomes 0 (this is referred to as a mustache). If the generation of such a beard is output to the monitor terminal 80 as it is, stable determination cannot be made. Therefore, the flip-flop 110 is wired between the EOR circuit 70 and the monitor terminal 80, and a clock is applied to the flip-flop 110 so that the flip-flop 110 latches a portion other than the beard of the output from the EOR circuit 70. Thus, it is possible to prevent the mustache of the output from the EOR circuit 70 from propagating to the monitor terminal 80 and obtain a smoothed waveform.
[0046]
As described above, according to the fifth embodiment, the output of the EOR circuit is input to the monitor terminal via the flip-flop. Therefore, a clock is applied to the flip-flop, and the flip-flop receives the output from the EOR circuit. By latching the portion other than the whiskers of the output, it is possible to prevent the occurrence of whiskers in the output of the EOR circuit that occurs when the circuit has a time delay, to smooth the output from the monitor terminal, and to perform a more stable determination. There is an effect that it can be performed.
[0047]
【The invention's effect】
As can be seen from the above description, according to the present invention, an inexpensive and simple burn-in inspection device can be provided in a semiconductor device that performs burn-in using a scan chain.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a semiconductor device according to a first embodiment of the present invention;
FIG. 2 is a timing chart of the semiconductor device according to the first embodiment of the present invention;
FIG. 3 is a configuration diagram of a semiconductor device according to a second embodiment of the present invention;
FIG. 4 is a timing chart of the semiconductor device according to the second embodiment of the present invention;
FIG. 5 is a configuration diagram of a semiconductor device according to a third embodiment of the present invention.
FIG. 6 is a timing chart of the semiconductor device according to the third embodiment of the present invention, showing an example when there is no failure (a) and a case where there is a failure (b).
FIG. 7 is a configuration diagram of a semiconductor device according to a fourth embodiment of the present invention.
FIG. 8 is a timing chart of a semiconductor device according to a fourth embodiment of the present invention.
FIG. 9 is a configuration diagram of a semiconductor device according to a fifth embodiment of the present invention.
FIG. 10 is a timing chart of a semiconductor device according to a fifth embodiment of the present invention.
FIG. 11 is a timing chart of a semiconductor device according to a fifth embodiment of the present invention.
FIG. 12 is a configuration diagram of a first conventional semiconductor device.
FIG. 13 is a configuration diagram of a second conventional semiconductor device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Semiconductor device main body 2 Burn-in target circuit 21 First scan chain 22 Second scan chain 31 First input terminal 32 Second input terminal 41 First output terminal 42 Second output terminal 5 Scan clock terminal 60 61, 110 Flip-flops 70, 71, 72, 73, 74 EOR circuits 80, 81, 82, 83 Monitor terminals 91, 92, 93, 94 AND circuit 100 Selector circuit

Claims (5)

A scan chain having an input terminal and an output terminal, wherein rectangular data equal to the cycle of a scan clock is input from the input terminal;
An EOR circuit having as input the output terminals of two flip-flops separated by an odd number of stages on the scan chain;
A monitor terminal wired to the output of the EOR circuit;
A semiconductor device, comprising: A scan chain having an input terminal and an output terminal, wherein rectangular data having a cycle of an integer multiple of 2 or more of a scan clock is input from the input terminal;
Two AND circuits each having the two inputs of the outputs of two flip-flops separated by a different odd number of stages on the scan chain,
Two EOR circuits each receiving the outputs of the two AND circuits,
A selector circuit having the two EOR circuits as inputs,
A monitor terminal wired to the output of the selector circuit,
A semiconductor device, comprising: The semiconductor device according to claim 1,
A scan chain having a plurality of EOR circuits each having an output terminal of two flip-flops separated by an odd number of stages on the scan chain, and a plurality of monitor terminals wired to the output of the EOR circuit;
The EOR circuit has an output terminal of two flip-flops separated by an odd number of stages on the scan chain and an output terminal of two flip-flops separated by an odd number of stages different from the number of odd stages on the scan chain. Do
A semiconductor device characterized by the above-mentioned. The semiconductor device according to claim 1,
It has an input terminal and an output terminal,
A plurality of scan chains each including an EOR circuit having input terminals of two flip-flops separated by an odd number of stages on the scan chain, and a monitor terminal wired to an output of the EOR circuit;
A semiconductor device characterized by the above-mentioned. The semiconductor device according to claim 1,
A flip-flop whose output is the input of the EOR circuit and whose output is wired to the monitor terminal;
A semiconductor device characterized by the above-mentioned.

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