JPH02251777A - Burn-in test device - Google Patents

Abstract

PURPOSE:To enable execution of a test of high precision by a simple test circuit board and a signal generator by a method wherein an output signal of an internal logic circuit to be tested and an input signal at the time of an actual operation are taken in an input buffer selectively. CONSTITUTION:Input buffers 5 to 7, an internal logic circuit 14 and output terminals 11 to 13 thereof and a basic test signal input terminal 15 are provided. A switching signal is inputted to a switching terminal 4 to put the buffers 5 to 7 in a test mode, and a test signal is impressed on the terminal 15 from the signal generator. Then the circuit 14 starts to operate, a logic output signal thereof is outputted to the terminals 11 to 13 and also inputted in feedback to the buffers 5 to 7, the signal thus inputted is given as a new test signal to the circuit 14, and thus a test is continued. On the occasion, input terminals 8 to 10 are made open to maintain a potential of a set level and thereby execution of a test of the circuit 14 is enabled. According to this constitution, it is possible to simplify a wiring of a test circuit board, to lessen the number of test signals and to execute a test of excellent precision.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to testing of semiconductor integrated circuit devices, and more specifically to a burn-in test device that performs a burn-in test of internal logic circuits in a semiconductor integrated circuit device. It is related to.

[Conventional technology]

FIG. 4 is a block connection diagram showing a conventional burn-in test device. In the figure, 1 is a semiconductor integrated circuit device, 2 is a
3 is a test board for a burn-in test on which the semiconductor integrated circuit device 1 is mounted, and 3 is a signal generator for inputting a test signal to the semiconductor integrated circuit device 1.

Next, the operation will be explained. Generally, burn-in tests are performed to eliminate initial defects in semiconductor integrated circuit devices. Furthermore, among these burn-in tests, a dynamic burn-in test in which a test is performed while a signal is applied is the most effective.

First, a test signal is generated by the signal generator 3 and applied to the semiconductor integrated circuit device 1 via the wiring on the test board 2. With the test signal being applied to the semiconductor integrated circuit device 1 in this manner, the semiconductor integrated circuit device 1 is placed under a burn-in test environment, and a test is performed for a predetermined period of time.

This burn-in test causes the semiconductor integrated circuit device 1 that was about to develop an initial failure to become defective, and a subsequent 7-anxy test (to check whether the functions of the semiconductor integrated circuit device 1 are operating correctly) is performed. (test) K, it is removed as defective.

Therefore, in such a burn-in test, the more the internal circuit of the semiconductor integrated circuit device 1 operates, the more
It can be said that it is a highly accurate test since it is easy to identify initial defects.

[Problem to be solved by the invention]

Since the conventional burn-in test equipment is configured as described above, in order to operate the internal circuit of the semiconductor integrated circuit device 1 as fully as possible to perform a highly accurate test, it is necessary to input test signals to all input terminals. Moreover, it is necessary to make the test signal a random signal rather than a periodic signal, and the test board 2
There are problems such as the above wiring is complicated and an expensive signal generator that can generate various test signals is required. In addition, as a conventional burn-in test device, the MIL standard (MI
There is a similar description in L-8TD-883C Method 1015.4 (Regulations).

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a burn-in test device that can perform a burn-in test with high accuracy using a simple test board and a signal generator.

[Means to solve the problem]

The burn-in test device according to the present invention selectively inputs the output signal of the internal logic circuit to be tested and the input signal during actual operation into the input buffer (KJI), and inputs the input signal into the input buffer (KJI) at the time of the test. Input a switching signal to set the above input buffer to test mode.
The output signal of the internal logic circuit to which the test signal is input is selected and fed back to the internal logic circuit, and the input terminal is held at a set potential.

[Effect]

In the input buffer of the present invention, the operation mode is switched according to a switching signal between test operation and actual operation, and in particular,
During a test operation, the output signal of the internal logic circuit is fed back to the internal logic circuit as a new input signal for testing, thereby causing a new logic output signal to be output.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 1 is a semiconductor integrated circuit device, 2 is a test board, and 3 is a signal generator, which are similar to those shown in FIG. Reference numeral 4 denotes a switching terminal for inputting a switching signal for switching and selecting test operation and actual operation.

FIG. 2 is a block connection diagram showing details of the semiconductor integrated circuit device 1, in which 5 to 7 are input buffers, 8 to 1 are input buffers, and 8 to 1 are input buffers.
0 is an input terminal for input signals during actual operation, 11 to 13 are output terminals of the internal logic circuit 14 to be tested, and 15 is a test signal input terminal for inputting basic test signals from the signal generator 3. , the input roses 775 to 7 are input to the internal logic circuit 1 in place of the input signals of the input terminals during testing.
Input the output of step 4 as feedback.

Next, the operation will be explained.

First, a switching signal is input to the switching terminal 4 to set each input buffer 5 - 7 to the test mode, and then a test signal is applied from the signal generator 3 to the test signal input terminal 15 . As a result, the internal logic circuit 14 of the semiconductor integrated circuit device 1 starts operating based on this test signal, and logic output signals of this internal logic circuit 14 are obtained at the output terminals 11-13. - On the other hand, this logic output signal is input from input buffer 5 to T.
The signal is fed back to the internal logic circuit 14 as a new test signal, and the test is continued. Here, from each of the above output terminals 11 to 13 to input buffers 5 to 7
The pattern of test signals returned to the internal logic circuit 14
Although it depends on the configuration of the semiconductor integrated circuit device 1, the periodically changing test signals given from the signal generator 3 can be of various kinds, and can activate the operation of the semiconductor integrated circuit device 1.

Also, at this time, input terminals 8 to 10 are left open,
By maintaining the potential at the set level, it is possible to perform a pin-in test of the internal logic circuit 14 using the test signal.

In the above embodiment, a test operation circuit is not added to the internal logic circuit 14, but as shown in FIG. In some cases, a control terminal may be provided for level sensing. Here, reference numerals 16 to 18 are edge-sensing latch elements which become level-sensing during test operation using a switching terminal 4 for switching between test operation and actual operation. According to this embodiment, % latch elements 16-1
8 is set to test operation by inputting a switching signal to the switching terminal 4, and the signal at the clock terminal of the latch elements 16 to 18 is set to the 1H level (or 1L" level). ) Even if it is fixed, there will be no through between the input and output of the latch elements 16 to 18, and the operation of the internal logic circuit 14A at the subsequent stage will not be stopped.

〔Effect of the invention〕

As described above, according to the present invention, by returning a signal from the output terminal of the internal logic circuit to be tested to the input buffer during the test mode, the test signal is generated based on the basic test signal from the signal generator. Since the configuration is such that it can be input into the internal logic circuit, the wiring on the test board can be simplified, and the signal generator that provides the test signal from the outside can also be used to generate the test signal. This has the advantage of requiring fewer signals and allowing highly accurate burn-in testing.

[Brief explanation of drawings]

FIG. 1 is a block connection diagram showing a burn-in test device according to an embodiment of the invention, FIG. 2 is a block connection diagram showing details of a semiconductor integrated circuit device according to the invention, and FIG. 3 is a block connection diagram showing details of a semiconductor integrated circuit device according to the invention. A block connection diagram showing details of the circuit device. FIG. 4 is a block connection diagram showing a conventional burn-in test device. 1 is a semiconductor integrated circuit device, 4 is a switching terminal, 5°6.7
is an input buffer, 8.9.10 is an input terminal, and 14 is an internal logic circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] An internal logic circuit that is provided in a semiconductor integrated circuit device as a test target and that receives a test signal from the outside and outputs a predetermined pattern of output signals, an output signal of this internal logic circuit, and an input signal during actual operation. an input buffer that selects the output signal and outputs it to the internal logic circuit, a switching terminal for inputting a switching signal that selects the output signal of the input buffer and puts it into test mode when testing the internal logic circuit; A burn-in test device comprising: an input terminal for the input signal during actual operation, which is held at a set potential during testing of a logic circuit.