CN111693846A - Chip testing system and method - Google Patents
Chip testing system and method Download PDFInfo
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- CN111693846A CN111693846A CN201911422265.XA CN201911422265A CN111693846A CN 111693846 A CN111693846 A CN 111693846A CN 201911422265 A CN201911422265 A CN 201911422265A CN 111693846 A CN111693846 A CN 111693846A
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- 238000012360 testing method Methods 0.000 title claims abstract description 169
- 238000000034 method Methods 0.000 title claims abstract description 13
- 238000005457 optimization Methods 0.000 claims description 6
- 230000002708 enhancing effect Effects 0.000 claims description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 238000009966 trimming Methods 0.000 description 2
- 108091026890 Coding region Proteins 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/2806—Apparatus therefor, e.g. test stations, drivers, analysers, conveyors
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/281—Specific types of tests or tests for a specific type of fault, e.g. thermal mapping, shorts testing
- G01R31/2815—Functional tests, e.g. boundary scans, using the normal I/O contacts
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The invention provides a chip testing system and a chip testing method. The first chip carrying platform is electrically connected with the first circuit board, the reference platform and the first chip testing platform have functions of writing parameters into the chip for testing, when the reference platform or the first chip testing platform tests the chip, the chip is arranged on the first chip carrying platform, and the first circuit board is electrically connected with the reference platform or the first chip testing platform. The method comprises the steps that a machine table is referred to test a standard chip to obtain an optimized parameter of the standard chip, the standard chip is tested on a first chip testing machine table to obtain a first testing result based on the optimized parameter, and if the first testing result exceeds a preset specification, the first chip testing machine table is debugged; if the first test result does not exceed the preset specification, the first chip tester finishes the calibration of the tester.
Description
Technical Field
The present invention relates to a chip testing system and method, and more particularly, to a chip testing system and method for mass production of chips, and more particularly, to reducing the difference between testing machines.
Background
Before the chips are shipped, each chip must be tested by a testing machine, for example, trimming the resistance of the devices on the chip to obtain the optimum frequency, or enhancing the stability of the chip. Generally, the testers are calibrated by the manufacturer to meet the specifications guaranteed at first, but even if each tester meets the specifications, there are still differences between different testers. In addition, the difference of the testing environment causes the variation of the chip testing, for example, when the chip is tested, the chip carrier is used to set the chip and the circuit board is used to electrically connect the testing machine and the chip carrier.
In the conventional chip testing method, the standard chip (gold chip) is used to calibrate different test machines to reduce the machine difference, wherein various characteristics of the standard chip are in accordance with the shipment standard, and a tester tests the same standard chip with different test machines before testing the chip to be tested to calibrate each machine, however, different parameters are written on different test machines by the standard chip along with different machines, which results in that the machine calibration process cannot optimally reduce the machine difference.
Disclosure of Invention
In view of the above-mentioned problems of the prior art, an object of the present invention is to provide a chip testing system, which includes a first circuit board, a first chip carrier, a reference stage, a first chip testing stage, and a standard chip (gold chip). The first chip carrier is electrically connected to the first circuit board, and the reference machine and the first chip tester both have a function of writing parameters (e.g., trim resistor) into the chip for testing, wherein when the reference machine or the first chip tester tests the chip, the chip is disposed on the first chip carrier, and the first circuit board is electrically connected to the reference machine or the first chip tester. The method comprises the steps that a machine table is referred to test a standard chip to obtain an optimized parameter of the standard chip, the standard chip is tested on a first chip testing machine table based on the optimized parameter to obtain a first test result, and if the first test result exceeds a preset specification, the first chip testing machine table is dispatched; if the first test result does not exceed the preset specification, the first chip tester finishes the calibration of the tester.
Preferably, the optimization parameters may be written into an encoded region of the standard chip by the reference station, and the encoded region is read-only (read-only) for the first chip testing station.
Preferably, the optimized parameters can be stored in the remote server, the portable access device or the computer through the reference machine, and input into the first chip testing machine through the remote server, the portable access device or the computer, so as to test the standard chip on the first chip testing machine.
Preferably, the optimized parameters may be inputted into the first chip testing machine through a computer so as to test the standard chip on the first chip testing machine.
Preferably, the optimization parameters may relate to resistance values of components on the standard chip or codes for enhancing stability of the standard chip.
Another objective of the present invention is to provide a chip testing method, which comprises a calibration stage of a tester and a chip testing stage. The calibration stage of the testing machine is to calibrate the first chip testing machine having the function of writing parameters into the chip for testing, so that the first chip testing machine conforms to the preset specification relative to the reference machine having the function of writing parameters into the chip for testing, and the calibration stage of the testing machine comprises: arranging a standard chip (gold chip) on a first chip carrier, wherein the first chip carrier is electrically connected with a first circuit board, and the first circuit board is electrically connected with a reference machine table; testing the standard chip to obtain the optimized parameters of the standard chip; the first chip carrying platform, the standard chip arranged on the first chip carrying platform and the first circuit board electrically connected with the first chip carrying platform are electrically connected with the first chip testing machine platform; testing the standard chip on the first chip testing machine based on the optimized parameters to obtain a first testing result, and if the first testing result exceeds a preset specification, debugging the first chip testing machine; if the first test result does not exceed the preset specification, the first chip tester finishes the calibration stage of the tester. The chip test stage tests the chip to be tested, and the chip test stage comprises the following steps: arranging a chip to be tested on a first chip carrying platform, wherein the first chip carrying platform is electrically connected with a first circuit board, and the first circuit board is electrically connected with a first chip testing machine platform which finishes the calibration stage of the testing machine platform; and testing the chip to be tested on the first chip testing machine.
Preferably, the optimized parameters can be written into the code area of the standard chip by the reference tool, and the code area is read only by the first chip testing tool.
Preferably, the optimized parameters can be stored in the remote server, the portable access device or the computer through the reference machine, and input into the first chip testing machine through the remote server, the portable access device or the computer, so as to test the standard chip on the first chip testing machine.
Preferably, the optimized parameters may be inputted into the first chip testing machine through a computer so as to test the standard chip on the first chip testing machine.
Preferably, the optimization parameters may relate to resistance values of components on the standard chip or codes for enhancing stability of the standard chip.
The chip testing system and method as described above mainly differ from the prior art in that: when different chip test machines test standard chips, the same set of optimized parameters are used, the same chip carrying platform and the same circuit board are used to reduce test variation, and the obtained test result can more truly present the difference among the machines so as to provide more complete information for a corrector in the calibration stage of the test machines, not only correct all the machines to meet the specification, but also reduce the difference among the machines and further promote the consistency among different tested chips.
Drawings
FIG. 1 is a block diagram of a chip testing system according to an embodiment of the invention.
FIG. 2 is a flow chart showing a chip testing method according to an embodiment of the invention.
Reference numerals:
100: standard chip
101: reference machine
102: first chip testing machine
1021: first circuit board
1022: first chip carrying platform
S210 to S214, S220 to S222: step (ii) of
Detailed Description
In order to make the present invention easy to understand the technical features, contents and advantages of the present invention and the effects achieved thereby, the present invention will be described in detail with reference to the drawings and the embodiments, wherein the drawings are used for illustration and the auxiliary description only, and not necessarily for the actual proportion and the precise configuration after the implementation of the present invention, and therefore, the appended drawings should not be read and the claims of the present invention should not be limited to the proportion and the configuration relationship.
Referring to fig. 1, a block diagram of a chip testing system according to an embodiment of the invention is shown. As shown in fig. 1, the chip test system includes: the apparatus includes a standard chip 100, a reference stage 101, a first chip testing stage 102, a first circuit board 1021, and a first chip carrier 1022. The standard chip (gold chip)100 is a chip conforming to the shipment specification, and the reference stage 101 and the first chip testing stage 102 are substantially identical in function, and can write parameters for testing at least one identical chip, wherein the write parameters refer to adjusting adjustable characteristics of elements on the chip, such as trimming resistors (trim resistors) and other optimized settings, so as to enhance the stability of the chip; first chip carrier 1022 is used for loading chips; the first circuit board 1021 is used for electrically connecting the chip and the chip testing machine during chip testing.
Referring to fig. 2, a flow chart of a chip testing method according to an embodiment of the invention is shown. The chip testing method of the present invention mainly comprises two steps (S210-S220), namely the calibration stage of the testing machine of step S210 and the chip testing stage of step S220, and the detailed description is as follows:
step S210: the first chip tester 102 is calibrated in the calibration stage of the tester, so that the first chip tester 102 and the reference machine 101 not only conform to the specifications of the machines, but also the difference between the two machines is reduced. As mentioned above, each tester is calibrated by the equipment manufacturer to meet the initially guaranteed specification, however, even if each tester meets the specification, there is a difference between different testers, so it is necessary to minimize the difference between the equipments, according to this embodiment, the step S210 can be further described by the following steps (S211 to S214):
step S211: the standard chip 100 is disposed on a first chip carrier 1022, the first chip carrier 1022 is electrically connected to a first circuit board 1021, and the first circuit board 1021 is electrically connected to the reference stage 101. The connection is as shown in fig. 1 (solid line in fig. 1).
Step S212: the standard chip 100 is tested to obtain the optimized parameters of the standard chip 100, and the optimized parameters are written into the coding region of the standard chip 100 through the reference machine 101. In this step, the reference machine 101 tests the standard chip 100, adjusts the adjustable characteristics of the devices on the standard chip 100 according to the test result, and sets various characteristic setting values corresponding to the optimized test result (hereinafter referred to as the standard test result) of the standard chip 100 as the optimized parameters of the standard chip 100.
Step S213: the standard chip 100, the first chip carrier 1022 and the first circuit board 1021 are electrically connected to the first chip tester 102 instead. The connection is as shown in fig. 1 (dashed line in fig. 1).
Step S214: based on the optimized parameters, the standard chip 100 is tested on the first chip tester 102 to obtain a first test result. In this step, the optimized parameters of the standard chip 100 are the optimized parameters obtained in step S212 and remain unchanged, wherein the optimized parameters may be encoded regions (not shown) of the standard chip 100, which are read-only (read-only) for the first chip testing machine 102, written by the reference machine 101 after step S212 is performed; alternatively, according to an embodiment of the present invention, the optimized parameters may be stored in the remote server, the portable access device or the computer by the reference machine 101 after the step S212 is executed, and any one of the above devices inputs the optimized parameters into the first chip tester 102; alternatively, according to another embodiment of the present invention, the optimization parameter may be input into the first chip testing machine 102 by a tester before performing step S214. Based on the optimized parameters, the first chip tester 102 directly tests the standard chip 100 to obtain a first test result, the first test result is compared with the standard test result, if the difference between the first test result and the standard test result meets the preset specification, the first chip tester 102 completes the tester calibration stage, that is, the stage difference between the first chip tester 102 and the reference stage 101 is optimally reduced, and in the following stage of testing the chip to be tested, because the difference between the first chip tester 102 and the reference stage 101 is reduced, the first chip tester 102 and the reference stage 101 can simultaneously perform chip testing to improve the yield. If the difference between the first test result and the standard test result does not meet the predetermined specification, it means that the first chip tester 102 must be further debugged until the first chip tester 102 completes the calibration stage of the tester.
The difference between the present invention and the prior art is mainly as follows: when testing standard chips on different chip test machines (a reference machine and a first chip test machine), the invention is based on the same optimized parameters and the same set of chip carrier and circuit board, instead of testing the standard chips on the first chip test machine with another set of optimized parameters of the standard chips as in the prior art.
When the first chip tester 102 completes the calibration in the calibration stage of the tester, the chip tester can enter the chip testing stage to test the chip to be tested (step S220), and step S220 can be further described by the following steps (S221 to S222):
step S221: the chip to be tested is disposed on the first chip carrier 1022, the first chip carrier 1022 is electrically connected to the first circuit board 1021, and the first circuit board 1021 is electrically connected to the first chip tester 102 completing the calibration stage of the tester.
Step S222: the chip to be tested is tested on the first chip tester 102.
When a large number of test chips are needed, the chip testing method can be repeated on more test machine tables, and the difference among the multiple chip test machine tables is reduced.
The chip testing system and the method disclosed by the invention are used for correcting different chip testing machines based on the same set of optimized parameters of the standard chip and correcting the same set of circuit board and chip carrier to reduce measurement variation.
The foregoing is by way of example only, and not limiting. It is intended that all equivalent modifications or variations without departing from the spirit and scope of the present invention shall be included in the scope of the appended claims.
Claims (10)
1. A chip test system, comprising:
a first circuit board;
a first chip carrying platform electrically connected with the first circuit board;
the system comprises a reference machine and a first chip testing machine, wherein the reference machine and the first chip testing machine both have the function of writing parameters into a chip for testing, when the reference machine or the first chip testing machine tests the chip, the chip is arranged on a first chip carrying platform, and a first circuit board is electrically connected with the reference machine or the first chip testing machine; and
the reference machine station tests the standard chip to obtain an optimized parameter of the standard chip, tests the standard chip on the first chip testing machine station to obtain a first testing result based on the optimized parameter, and if the first testing result exceeds a preset specification, the first chip testing machine station is debugged; if the first test result does not exceed the preset specification, the first chip tester is represented to complete the calibration of the tester.
2. The system of claim 1, wherein the optimized parameter is written to an encoded region of the standard chip by the reference tool, and the encoded region is read-only to the first chip tester tool.
3. The chip testing system of claim 1, wherein the optimized parameters are stored in a remote server, a portable access device or a computer through the reference machine, and are input into the first chip testing machine through the remote server, the portable access device or the computer to test the standard chip on the first chip testing machine.
4. The system of claim 1, wherein the optimized parameters are inputted into the first chip tester via a computer for testing the standard chip on the first chip tester.
5. The chip test system according to any one of claims 2 to 4, wherein the optimization parameter is related to a resistance value of a component on the standard chip or a code for enhancing stability of the standard chip.
6. A method for testing a chip, comprising:
a calibration stage of the testing machine, which calibrates a first chip testing machine having a function of writing parameters into a chip for testing, so that the first chip testing machine conforms to a predetermined specification with respect to a reference machine having a function of writing parameters into a chip for testing, the calibration stage of the testing machine comprising:
arranging a standard chip on a first chip carrying platform, wherein the first chip carrying platform is electrically connected with a first circuit board, and the first circuit board is electrically connected with the reference machine platform;
testing the standard chip to obtain an optimized parameter of the standard chip;
the first chip carrying platform, the standard chip arranged on the first chip carrying platform and the first circuit board electrically connected with the first chip carrying platform are electrically connected with the first chip testing machine platform; and
testing the standard chip on the first chip testing machine based on the optimized parameter to obtain a first test result, and if the first test result exceeds a preset specification, debugging the first chip testing machine; if the first test result does not exceed the preset specification, the first chip tester is represented to finish the tester calibration stage; and
a chip testing stage for testing a chip to be tested, comprising:
arranging the chip to be tested on the first chip carrying platform, electrically connecting the first chip carrying platform with the first circuit board, and electrically connecting the first circuit board with the first chip testing machine platform for completing the calibration stage of the testing machine platform; and
and testing the chip to be tested on the first chip testing machine.
7. The method as claimed in claim 6, wherein the optimized parameter is written into an encoded region of the standard chip by the reference tool, and the encoded region is read-only for the first chip tester.
8. The method as claimed in claim 6, wherein the optimized parameter is stored in a remote server, a portable access device or a computer through the reference machine, and is input into the first chip tester through the remote server, the portable access device or the computer to test the standard chip on the first chip tester.
9. The method as claimed in claim 6, wherein the optimized parameters are inputted into the first chip tester via a computer for testing the standard chip on the first chip tester.
10. The chip testing method according to any one of claims 7 to 9, wherein the optimization parameter relates to a resistance value of a device on the standard chip or a code for enhancing stability of the standard chip.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW108108252 | 2019-03-12 | ||
| TW108108252A TWI693410B (en) | 2019-03-12 | 2019-03-12 | Chip test system and method |
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| CN111693846A true CN111693846A (en) | 2020-09-22 |
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| CN201911422265.XA Pending CN111693846A (en) | 2019-03-12 | 2019-12-31 | Chip testing system and method |
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| TW (1) | TWI693410B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022100139A1 (en) * | 2020-11-10 | 2022-05-19 | 长鑫存储技术有限公司 | Detection method and detection apparatus for wafer testing machines |
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Also Published As
| Publication number | Publication date |
|---|---|
| TWI693410B (en) | 2020-05-11 |
| TW202033968A (en) | 2020-09-16 |
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