CN113138330A - Method and system for preventing chip from entering test mode by mistake - Google Patents
Method and system for preventing chip from entering test mode by mistake Download PDFInfo
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- CN113138330A CN113138330A CN202011605697.7A CN202011605697A CN113138330A CN 113138330 A CN113138330 A CN 113138330A CN 202011605697 A CN202011605697 A CN 202011605697A CN 113138330 A CN113138330 A CN 113138330A
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- 238000012360 testing method Methods 0.000 title claims abstract description 86
- 238000000034 method Methods 0.000 title claims abstract description 23
- 230000008676 import Effects 0.000 claims abstract description 9
- 238000005070 sampling Methods 0.000 claims description 11
- 230000008030 elimination Effects 0.000 claims description 10
- 238000003379 elimination reaction Methods 0.000 claims description 10
- 230000011664 signaling Effects 0.000 claims description 5
- 230000009286 beneficial effect Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 1
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- 238000004377 microelectronic Methods 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/2856—Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
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Abstract
The invention relates to the field of chip testing, in particular to a method and a system for preventing a chip from entering a test mode by mistake. The method comprises the following steps: step S1, presetting an import code pattern corresponding to the test mode; step S2, acquiring a first signal received by the first pin; and step S3, processing the first signal, judging whether the processed first signal belongs to the imported code pattern, and controlling the chip to enter a test mode according to the judgment result. The technical scheme of the invention has the beneficial effects that: the method and the system for preventing the chip from entering the test mode by mistake can accurately and quickly control the chip to enter the test mode, and avoid the problem that the normal work of the chip is influenced because the chip is tested by mistake operation of a user.
Description
Technical Field
The invention relates to the field of chip testing, in particular to a method and a system for preventing a chip from entering a test mode by mistake.
Background
An IC (Integrated Circuit), also called an Integrated Circuit, is a micro electronic device or component, which is manufactured by interconnecting transistors, resistors, capacitors, inductors and other elements and wirings required in a Circuit through a certain process on one or more semiconductor wafers or dielectric substrates, and then packaged in a package to form a micro structure with the required Circuit function. The operation mode of the chip can be generally divided into a working mode and a testing mode, wherein the working mode is a normal operation mode of the chip, and for a general user, the chip usually works in the working mode; the Test mode is a mode in which a chip supplier tests on an ATE (Automatic Test Equipment) machine after producing a chip, and in this mode, different stimuli can be applied to each pin of the chip to Test whether a problem occurs in a chip production or packaging link, so as to implement an operational Test of an internal circuit of the chip.
These two modes are mutually exclusive, and when the chip is in the test mode, the predetermined function in the working mode cannot be executed, so that the user usually does not want the chip to enter the test mode by mistake. However, in the prior art, since the mode setting interface of the chip is complex, the chip often enters the test mode due to misoperation of a user or intentional factors, so that the chip cannot work normally, and even a safety problem occurs.
Disclosure of Invention
In view of the above problems in the prior art, a method and system for preventing a chip from entering a test mode by mistake are provided.
The method for preventing the chip from entering the test mode by mistake comprises the following steps that the chip comprises a first pin for receiving a first signal;
the method comprises the following steps:
step S1, presetting an import code pattern corresponding to the test mode;
step S2, acquiring a first signal received by the first pin;
and step S3, processing the first signal, judging whether the processed first signal belongs to the imported code pattern, and controlling the chip to enter a test mode according to the judgment result.
Preferably, the first pin is a reset pin, and the reset pin is used for receiving a first signal;
the step S3 includes:
step S31, performing jitter elimination processing on the first signal to generate a corresponding second signal, and generating a third signal according to the first signal and the second signal;
step S32, determining whether the corresponding first signal belongs to the imported code pattern according to the second signal and the third signal, and controlling the chip to enter a test mode according to the determination result.
Preferably, the chip further comprises a clock pin, and the clock pin is used for receiving a clock signal;
the step S31 includes:
step S311, acquiring the clock signal, and sampling the first signal according to the clock signal;
step S312, generating the third signal according to the first signal and the second signal after the sampling processing.
Preferably, the first signal includes a lead-in portion corresponding to the lead-in code pattern and a configuration portion corresponding to a functional configuration; the method further comprises the following steps:
and the chip is configured according to the configuration part in the test mode.
A system for preventing a chip from entering a test mode by mistake comprises a first pin for receiving a first signal;
the system comprises:
the preset module is used for presetting the lead-in code pattern corresponding to the test mode;
and the control module is connected with the preset module and used for acquiring and processing the first signal received by the first pin, judging whether the processed first signal belongs to the import code pattern or not, and controlling the chip to enter a test mode according to a judgment result.
Preferably, the first pin is a reset pin, and the reset pin is used for receiving a first signal;
the control module further comprises:
the jitter elimination unit is used for carrying out jitter elimination processing on the first signal to generate a corresponding second signal;
the processing unit is connected with the jitter eliminating unit and used for acquiring the first signal and the second signal and generating a corresponding third signal;
and the control unit is connected with the processing unit and used for judging whether the corresponding first signal belongs to the import code pattern or not according to the second signal and the third signal and controlling the chip to enter a test mode according to a judgment result.
Preferably, the chip further comprises a clock pin, and the clock pin is used for receiving a clock signal;
the processing unit includes:
the first processing component is used for acquiring the clock signal and sampling the first signal according to the clock signal;
and the second processing part is connected with the first processing part and is used for generating the third signal according to the first signal and the second signal after sampling processing.
Preferably, the first signal includes a lead-in portion corresponding to the lead-in code pattern and a configuration portion corresponding to a functional configuration;
the configuration module includes:
and the chip configures the chip according to the configuration part in the test mode.
The technical scheme of the invention has the beneficial effects that: the method and the system for preventing the chip from entering the test mode by mistake can accurately and quickly control the chip to enter the test mode, and avoid the problem that the normal work of the chip is influenced because the chip is tested by mistake operation of a user.
Drawings
FIG. 1(a) is a schematic diagram illustrating a control chip entering an operating mode when pulling up to DVDD in the prior art;
FIG. 1(b) is a schematic diagram illustrating a prior art control chip entering a test mode by pulling down to ground;
FIG. 2 is a flowchart illustrating a method for preventing a chip from entering a test mode by mistake according to a preferred embodiment of the present application;
FIG. 3 is a flowchart illustrating the step S3 according to the preferred embodiment of the present application;
FIG. 4 is a flowchart illustrating the step S31 according to the preferred embodiment of the present application;
FIG. 5 is a schematic diagram of a system for preventing a chip from entering a test mode by mistake according to a preferred embodiment of the present application;
FIG. 6 is a schematic diagram of a control module according to a preferred embodiment of the present application;
FIG. 7 is a schematic diagram of a processing unit according to a preferred embodiment of the present application;
fig. 8 is a schematic diagram of a first signal, a second signal, and a third signal according to a preferred embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.
The invention is further described with reference to the following drawings and specific examples, which are not intended to be limiting.
In the prior art, the operation mode of the chip is usually controlled to be a normal operation mode or a test mode by a power-on mode, as shown in fig. 1(a) - (b), different pull-up and pull-down modes are adopted for PIN _ LED, and the operation mode of the chip is controlled, specifically, as shown in fig. 1(a), when the PIN _ LED is pulled up to DVDD, the chip is controlled to enter the operation mode, and as shown in fig. 1(b), when the PIN _ LED is pulled down to ground, the chip is controlled to enter the test mode. However, whether the control chip enters the working mode or the test mode, the user is required to pull up and down some pins fixedly, and if the customer does not make a wrong board level circuit, the user will mistakenly enter the test mode, which results in that the chip at this time cannot work.
In practical applications, it is only necessary to enter the test mode on the ATE machine, and the ATE machine can input stimuli to the pins of the chip. Therefore, the invention provides a method and a system for preventing a chip from entering a test mode by mistake.
The chip comprises a first pin for receiving signals;
as shown in fig. 2, the method includes:
step S1, presetting an import code pattern corresponding to the test mode;
step S2, acquiring a first signal received by a first pin;
step S3, processing the first signal, determining whether the processed first signal belongs to the imported code pattern, and controlling the chip to enter the test mode according to the determination result.
Specifically, the invention can preset a lead-in code pattern for controlling the chip to enter the test mode, and can control the chip to enter the test mode when a signal received by the first pin of the chip belongs to the preset lead-in code pattern after being processed.
In a preferred embodiment of the present invention, the first pin is a reset pin, and the reset pin is configured to receive a first signal;
as shown in fig. 3, step S3 includes:
step S31, performing jitter elimination processing on the first signal to generate a corresponding second signal, and generating a third signal according to the first signal and the second signal;
and step S32, judging whether the corresponding first signal belongs to the imported code pattern according to the second signal and the third signal, and controlling the chip to enter a test mode according to the judgment result.
Specifically, considering that the pins on the chip are limited, the test mode needs as many pins as possible to add a scan chain, so as to reduce the test time and cost, and meanwhile, the pins cannot generate an incoming waveform in the working mode, and here, the reset pin can be used as the first pin, and accordingly, in order to realize the function multiplexing of the reset pin, namely, the reset function is realized, the chip can be controlled to enter the test mode, and a third signal is generated according to the first signal received by the reset pin and the second signal after the jitter elimination processing, so as to judge whether the first signal received by the chip at the moment correspondingly belongs to an incoming code pattern, and the chip is controlled to perform the test mode.
In a preferred embodiment of the present invention, the chip further includes a clock pin, and the clock pin is configured to receive a clock signal;
as shown in fig. 4, step S31 includes:
step S311, acquiring a clock signal, and sampling the first signal according to the clock signal;
in step S312, a third signal is generated according to the sampled first signal and second signal.
In particular, the clock signal may sample a signal received by the reset pin.
In a preferred embodiment of the invention, the first signal comprises a lead-in portion corresponding to the lead-in pattern and a configuration portion corresponding to the functional configuration; the method further comprises the following steps:
and the chip is configured according to the configuration part in the test mode.
Specifically, the first signal further includes a configuration portion corresponding to the functional configuration, and after the reset pin receives the first signal, the chip may be configured according to the configuration portion, that is, after the test pattern is imported into the code pattern, more data bits may be defined to indicate different configurations in the test pattern, such as whether to compress the test pattern (test pattern), whether to enable the internal PLL, and the like. This saves more pins and thus more scan chains can be added.
The system for preventing the chip from entering the test mode by mistake comprises a first pin for receiving a first signal;
as shown in fig. 5, the system includes:
a presetting module 1, which is used for presetting a lead-in code pattern corresponding to a test mode;
and the control module 2 is connected with the presetting unit 1 and is used for acquiring and processing the first signal received by the first pin, judging whether the processed first signal belongs to the import code pattern or not, and controlling the chip to enter a test mode according to a judgment result.
In a preferred embodiment of the present invention, the first pin is a reset pin, and the reset pin is configured to receive a first signal;
as shown in fig. 6, the control module 2 further includes:
a jitter elimination unit 21, configured to perform jitter elimination processing on the first signal to generate a corresponding second signal;
the processing unit 22 is connected with the jitter eliminating unit 21 and is used for acquiring the first signal and the second signal and generating a corresponding third signal;
and the control unit 23 is connected to the processing unit 22 and configured to determine whether the corresponding first signal belongs to the imported code pattern according to the second signal and the third signal, and control the chip to enter the test mode according to the determination result.
In a preferred embodiment of the present invention, the chip further includes a clock pin, and the clock pin is configured to receive a clock signal;
as shown in fig. 7, the processing unit 22 includes:
a first processing unit 221, configured to acquire a clock signal and perform sampling processing on a first signal according to the clock signal;
the second processing unit 222 is connected to the first processing unit 221, and configured to generate a third signal according to the first signal and the second signal after the sampling processing.
In a preferred embodiment of the invention, the first signal comprises a lead-in portion corresponding to the lead-in pattern and a configuration portion corresponding to the functional configuration;
the configuration module includes:
and the chip is configured in the test mode according to the configuration part.
Example (b):
the embodiment is an embodiment of a specific application of a system for preventing a chip from entering a test mode by mistake, wherein the active level is 0 level.
The preset module presets a lead-in pattern corresponding to the test pattern, and a data structure of the lead-in pattern may include 18 bytes of data, wherein bytes 0 to 15 may correspond to a lead-in part, may be "01011001 _ 01010100", and bytes 16 to 17 may correspond to a configuration part in a signal, as shown in table 1 below:
TABLE 1
A Reset pin of the chip receives a first signal Reset _ n, a clock pin receives a clock signal test _ clock, an anti-jitter unit in the control module carries out anti-jitter processing on the first signal Reset _ n to generate a second signal Internal _ Reset _ n, and the control unit generates a third signal En _ test _ mode, Compress _ En and Bypass _ pll according to the first signal Reset _ n, the clock signal test _ clock and the second signal Internal _ Reset _ n;
as shown in fig. 8, it is determined that the first signal received by the reset pin belongs to the preset lead-in code pattern, the lead-in portion En _ test _ mode in the third signal changes from "0" to "1", the chip at this time enters the test mode, and then the corresponding function configuration and test are performed according to the configuration portions Compress _ En and Bypass _ pll in the received third signal.
And when the first signal Reset _ n of the Reset pin is '0' for a long time, the control chip enters the working mode after exiting the test mode.
The technical scheme of the invention has the beneficial effects that: the method and the system for preventing the chip from entering the test mode by mistake are provided, the signal received by the chip is processed, whether the processed signal belongs to a preset leading-in code pattern or not is judged, the chip is controlled to enter the test mode, the chip can be accurately and quickly controlled to enter the test mode, and the situation that the chip is subjected to the test mode due to misoperation of a user, and further normal work of the chip is influenced is avoided.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.
Claims (8)
1. A method for preventing a chip from entering a test mode by mistake is characterized in that the chip comprises a first pin for receiving a first signal;
the method comprises the following steps:
step S1, presetting an import code pattern corresponding to the test mode;
step S2, acquiring a first signal received by the first pin;
and step S3, processing the first signal, judging whether the processed first signal belongs to the imported code pattern, and controlling the chip to enter a test mode according to the judgment result.
2. The method according to claim 1, wherein the first pin is a reset pin for receiving a first signal;
the step S3 includes:
step S31, performing jitter elimination processing on the first signal to generate a corresponding second signal, and generating a third signal according to the first signal and the second signal;
step S32, determining whether the received first signal belongs to the imported code pattern according to the second signal and the third signal, and controlling the chip to enter a test mode according to the determination result.
3. The method according to claim 2, wherein the chip further comprises a clock pin for receiving a clock signal;
the step S31 includes:
step S311, acquiring the clock signal, and sampling the first signal according to the clock signal;
step S312, generating the third signal according to the first signal and the second signal after the sampling processing.
4. The method for preventing the chip from entering the test mode mistakenly according to claim 1, wherein the first signal comprises a lead-in part corresponding to the lead-in code pattern and a configuration part corresponding to the functional configuration; the method further comprises the following steps:
and the chip is configured according to the configuration part in the test mode.
5. A system for preventing a chip from entering a test mode by mistake is characterized in that the chip comprises a first pin for receiving a first signal;
the system comprises:
the preset module is used for presetting the lead-in code pattern corresponding to the test mode;
and the control module is connected with the preset module and used for acquiring and processing the first signal received by the first pin, judging whether the processed first signal belongs to the import code pattern or not, and controlling the chip to enter a test mode according to a judgment result.
6. The system according to claim 5, wherein the first pin is a reset pin for receiving a first signal;
the control module further comprises:
the jitter elimination unit is used for carrying out jitter elimination processing on the first signal to generate a corresponding second signal;
the processing unit is connected with the jitter eliminating unit and used for acquiring the first signal and the second signal and generating a corresponding third signal;
and the control unit is connected with the processing unit and used for judging whether the corresponding first signal belongs to the import code pattern or not according to the second signal and the third signal and controlling the chip to enter a test mode according to a judgment result.
7. The system for preventing the chip from entering the test mode by mistake of claim 6, wherein the chip further comprises a clock pin, and the clock pin is used for receiving a clock signal;
the processing unit includes:
the first processing component is used for acquiring the clock signal and sampling the first signal according to the clock signal;
and the second processing part is connected with the first processing part and is used for generating the third signal according to the first signal and the second signal after sampling processing.
8. The system for preventing the chip from entering the test mode by mistake according to claim 6, wherein the first signal comprises a lead-in part corresponding to the lead-in code pattern and a configuration part corresponding to the functional configuration;
the configuration module includes:
and the chip is configured in the test mode according to the configuration part.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117434428A (en) * | 2023-12-18 | 2024-01-23 | 杭州晶华微电子股份有限公司 | Chip calibration system, chip calibration mode entering method and chip |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040017219A1 (en) * | 2002-07-23 | 2004-01-29 | Dong-Kwan Han | System on chip (SOC) and method of testing and/or debugging the system on chip |
| US20040111658A1 (en) * | 2002-12-05 | 2004-06-10 | Kenichi Natsume | Scan test circuit with reset control circuit |
| CN101666838A (en) * | 2009-09-15 | 2010-03-10 | 北京天碁科技有限公司 | Chip system and mode control method thereof |
| CN105974299A (en) * | 2016-05-30 | 2016-09-28 | 珠海市微半导体有限公司 | Chip test control circuit and method thereof |
| CN107623517A (en) * | 2017-08-28 | 2018-01-23 | 上海集成电路研发中心有限公司 | A kind of clock and the realization device for resetting control chip mode of operation |
| CN110554298A (en) * | 2019-08-27 | 2019-12-10 | 江苏芯盛智能科技有限公司 | Chip and chip testing method |
| CN111157872A (en) * | 2019-12-25 | 2020-05-15 | 上海亮牛半导体科技有限公司 | Method for multiplexing existing logic pin to enter test mode |
-
2020
- 2020-12-29 CN CN202011605697.7A patent/CN113138330A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040017219A1 (en) * | 2002-07-23 | 2004-01-29 | Dong-Kwan Han | System on chip (SOC) and method of testing and/or debugging the system on chip |
| US20040111658A1 (en) * | 2002-12-05 | 2004-06-10 | Kenichi Natsume | Scan test circuit with reset control circuit |
| CN101666838A (en) * | 2009-09-15 | 2010-03-10 | 北京天碁科技有限公司 | Chip system and mode control method thereof |
| CN105974299A (en) * | 2016-05-30 | 2016-09-28 | 珠海市微半导体有限公司 | Chip test control circuit and method thereof |
| CN107623517A (en) * | 2017-08-28 | 2018-01-23 | 上海集成电路研发中心有限公司 | A kind of clock and the realization device for resetting control chip mode of operation |
| CN110554298A (en) * | 2019-08-27 | 2019-12-10 | 江苏芯盛智能科技有限公司 | Chip and chip testing method |
| CN111157872A (en) * | 2019-12-25 | 2020-05-15 | 上海亮牛半导体科技有限公司 | Method for multiplexing existing logic pin to enter test mode |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117434428A (en) * | 2023-12-18 | 2024-01-23 | 杭州晶华微电子股份有限公司 | Chip calibration system, chip calibration mode entering method and chip |
| CN117434428B (en) * | 2023-12-18 | 2024-03-26 | 杭州晶华微电子股份有限公司 | Chip calibration system, chip calibration mode entering method and chip |
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Address after: Room 201, building 4, No. 78, Keling Road, high tech Zone, Suzhou, Jiangsu 215159 Applicant after: Yutai Microelectronics Co.,Ltd. Address before: Room 201, building 4, No.78, Keling Road, high tech Zone, Suzhou City, Jiangsu Province Applicant before: Suzhou Yutai Microelectronics Co.,Ltd. |
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Application publication date: 20210720 |