JP2007294758A - Semiconductor test device, communication module test device, wafer test device, and wafer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor test device capable of shortening test time, and of testing communication operation even with a universal tester. <P>SOLUTION: In the semiconductor test device, communication operation is tested by making paired semiconductors alternately perform transmission and reception, among the semiconductors of two or more each having a transmitter and a receiver capable of two-way communication with a high frequency signal. The test device includes a transmission setting control unit 1a for transmitting a transmission control signal set by a transmission side in a DUT 2 where one semiconductor is disposed, and a reception setting control unit 1b for transmitting a reception control signal set by a reception side in a DUT 3 where the other semiconductor is disposed. Further, the device includes, in the DUT 2, a data transmitter 1c for transmitting transmission data; a data receiver 1d for receiving reception data from the DUT 3; and a data comparison/judgement part 1e for comparing the foregoing transmission data and the foregoing reception data, and judging, from a comparison result, the quality of communication operation of each semiconductor. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor test apparatus, a communication module test apparatus, and a wafer test apparatus that test a semiconductor having a communication function, a communication module, and a wafer.

  Conventionally, a wide variety of semiconductors have been designed and manufactured and mounted on various devices. For example, a mobile phone or the like is equipped with a semiconductor having a transmission / reception communication function, and direct conversion digital modulation / demodulation communication is performed on the semiconductor.

  However, although the semiconductor has a communication function designed by a designer and manufactured based on the design, the manufactured semiconductor does not necessarily have a communication function as designed. Therefore, a test process for testing whether or not the semiconductor manufacturing process has a designed communication function is provided. Semiconductors that have passed the test are shipped with guaranteed communication functions.

  Here, a test process for testing a communication function of a conventional semiconductor will be described. Note that the present invention is not limited to semiconductors, and may be applied to, for example, a communication module including a semiconductor having a communication function.

  In the test process, various types of testers are used. For example, there are the following types.

  An analog tester is a tester that performs tests on amplifiers and transistors. An RF tester (analog tester) is a tester in which a signal control function is enhanced in an analog tester for a communication semiconductor and a broadcast semiconductor. However, the function of the DC / function is weak and it is not possible to perform contact check of all semiconductor products.

  The logic tester is a tester for testing a logic circuit whose clock frequency is not high.

  An SOC tester (SOC: System On Chip) is a tester having an RF signal source having a function function of a clock of several hundred MHz, and a high-performance LSI such as a system-on-chip having an RF signal transmission / reception circuit or a CPU. It is an expensive tester that performs a test on a high-performance semiconductor having a communication function.

  For example, see FIG. 15 for the operation of testing the transmission / reception communication function of a semiconductor having the function of performing conventional frequency conversion and performing bidirectional communication at high frequency, for example, the conventional direct conversion digital modulation / demodulation communication. However, the following description will be made with the explanation of the configuration.

  FIG. 15 is a block diagram showing a configuration of a test apparatus 200 for testing a conventional communication function of the semiconductor.

  As shown in FIG. 15, the test apparatus 200 includes an analog tester 210 and a DUT 220. The analog tester 210 is a tester whose functions are extended to the analog tester and the RF tester so that digital modulation and demodulation can be performed. The modulator 211, the logic 212, and the spectrum analyzer 213 show the functional parts extended to the analog tester 210. The DUT 220 is a device under test, in which a semiconductor to be tested is arranged.

  When a reception test is performed, the analog tester 210 generates test data, the generated test data is digitally modulated by the modulator 211, frequency-converted to a high frequency (RF) frequency, and output to the DUT 220 as an input signal.

  Then, the control signal transmitted from the analog tester 210 to the DUT 220 instructs the DUT 220 to demodulate the input signal from the analog tester 210, and demodulates the input signal. Thereafter, the demodulated data is transmitted to the logic 212 of the analog tester 210.

  The analog tester 210 compares the test data output to the DUT 220 with the data input from the DUT 220 using the function function of the logic 212, and determines that communication has been performed normally if they match.

  When performing a transmission test, the analog tester 210 outputs data input to the logic 212 of the analog tester 210 during the reception test to the DUT 220 as an input signal.

  Then, the control signal transmitted from the analog tester 210 to the DUT 220 instructs the DUT 220 to modulate the input signal from the analog tester 210, modulates the input signal, and converts the frequency to an RF frequency. Thereafter, the RF signal is transmitted to the spectrum analyzer 213 of the analog tester 210.

  The analog tester 210 measures the RF signal using the function of the spectrum analyzer 213.

  As described above, the test apparatus 200 tests the transmission / reception communication function for one test target semiconductor.

  However, conventionally, when a semiconductor transmission / reception communication operation is tested with a tester, a dedicated analog tester corresponding to the communication test has to be prepared.

  When testing a semiconductor transmission / reception communication operation with a tester, an analog tester is used. Since an analog tester has an RF tester or the like, it can transmit and receive RF, but a general digital signal (DC signal). And function functions are often weak and cannot be handled. Therefore, since contact check or the like cannot be performed on all terminals, all terminals cannot be confirmed unless a test using a logic tester is performed in order to detect an assembly failure.

  Even if it can be handled, it is often insufficient for control and measurement when testing the communication function. Therefore, the analog tester needs to be separately modified and expanded.

  Further, in many cases where semiconductor communication operations are tested with an analog tester, it is necessary to prepare a separate facility for outputting a digital modulation signal.

  Also, even if there is a dedicated RF tester for analog testing that can output a digital modulation signal, the logic cannot be tested at the same time, so first test the DC characteristics with the logic tester, then pass the RF tester to check the AC characteristics. It is necessary to go through two processes of testing. Therefore, there is a problem that the test time increases.

  In addition, if an expensive SOC tester is used, it is possible to test the transmission / reception communication operation of a semiconductor in one process. For example, a high-performance semiconductor that is about 10 times the price of a communication semiconductor is tested. In this case, although the cost is reasonable, the target semiconductor having a function capable of bidirectional communication tests an item having a relatively long test time such as confirmation of coincidence of transmitted and received data. Therefore, when an expensive SOC tester is used, there is a problem that it is not profitable in terms of cost.

  The present invention has been made in view of the above-described conventional problems, and an object of the present invention is to provide a semiconductor test apparatus that can shorten a test time and can test a communication operation with a general-purpose tester.

  In order to solve the above-described problem, a semiconductor test apparatus according to the present invention is configured to transmit and receive a pair of semiconductors alternately in pairs among two or more semiconductors having a transmitter and a receiver capable of bidirectional communication with a high-frequency signal. A semiconductor test apparatus for testing a communication operation, wherein a transmission setting control means for transmitting a transmission control signal to be set on one transmission side to one of the semiconductors, and a reception control signal to be set on a reception side on the other semiconductor. Receiving setting control means for transmitting data, data transmitting means for transmitting transmission data to said one semiconductor, data receiving means for receiving received data from said other semiconductor, said transmission data and said receiving data A data comparison / determination unit is provided for determining whether the semiconductor communication operation is good or bad based on the comparison result.

  In addition, in order to solve the above-described problem, a semiconductor test method for a semiconductor test apparatus according to the present invention includes a pair of two or more semiconductors each having a transmitter and a receiver capable of bidirectional communication with a high-frequency signal. A semiconductor test method of a semiconductor test apparatus for testing a communication operation by alternately transmitting and receiving, the step of transmitting a transmission control signal to be set on the transmission side to one of the semiconductors, and the reception to the other semiconductor A step of transmitting a reception control signal to be set on the side, a step of transmitting transmission data to the one semiconductor, a step of receiving reception data from the other semiconductor, and the transmission data and the reception data. And comparing the result of the comparison to determine whether the semiconductor communication operation is good or not.

  According to the above configuration, the semiconductor test apparatus of the present invention transmits a control signal set on the transmission side to one semiconductor, transmits a control signal set on the reception side to the other semiconductor, and transmits to the transmission side. Transmission data for converting into a high frequency signal is transmitted to one of the set semiconductors. Then, the semiconductors perform high-frequency signal communication, demodulate the high-frequency signal received by the other semiconductor set on the receiving side, and transmit the demodulated data to the semiconductor test apparatus as received data.

  Thereafter, the semiconductor test apparatus of the present invention receives the received data from the semiconductor, compares the transmitted data and the received data, confirms whether the data matches or not from the comparison result, and determines whether the semiconductor communication operation is good. Therefore, a dedicated high-frequency tester for testing a high-frequency signal is not necessary.

  In other words, a tester having basic functions that can transmit and receive data, control semiconductor operations, and check DC characteristics and a wide range of logic functions may be used. Therefore, it is possible to use a general-purpose tester that is not dedicated and that can be tested with a widely used facility.

  In general, data generated on the tester side generates a high-frequency signal for confirming communication operation by a semiconductor. Therefore, it is not necessary to create a high-frequency signal for confirming the communication operation by the tester before the test, so that the time required for the creation can be reduced. Therefore, the test time can be used effectively, and the test time per unit can be shortened.

  As described above, in the semiconductor test apparatus of the present invention, the test time can be shortened and the communication operation can be tested even with a general-purpose tester.

  The semiconductor test apparatus includes a switching unit that selects one of the plurality of semiconductors as a semiconductor to be set on the receiving side, and connects the selected semiconductor to the semiconductor set on the transmitting side. It is preferable that the switching unit includes switching control means for controlling the switching unit by selecting one semiconductor to be set on the receiving side from a plurality of semiconductors and transmitting a switching signal for switching connection.

  According to the above configuration, the switching unit transmitted from the switching control means causes the switching unit to connect to the semiconductor set on the transmission side as the semiconductor that sets one of the plurality of semiconductors on the reception side. It becomes possible to perform a test while combining each semiconductor.

  In addition, since it is possible to perform a test while combining each semiconductor, it is possible to check whether the transmission operation and the reception operation of each semiconductor are normal by checking the transmission operation and the reception operation of each semiconductor. It becomes possible to confirm whether or not.

  Furthermore, as the number of semiconductors increases, the problem that the data comparison / determination means determines a non-defective product as a defective product can be improved.

  The semiconductor test apparatus preferably includes a handler that automatically supplies the semiconductor to the semiconductor test apparatus at the same time after assembly is completed, and automatically classifies and stores the semiconductor based on the test result.

  According to the above configuration, the semiconductor is automatically arranged at the same time after completion of assembly in the semiconductor test apparatus by the handler, and is automatically classified and stored based on the test result. This eliminates the need for classification and storage operations and reduces the time required for the above operations, thereby reducing the overall test time.

  The semiconductor test apparatus preferably includes an attenuator for attenuating the high-frequency signal in a communication path from a semiconductor set on the transmission side to a semiconductor set on the reception side.

  According to the above configuration, the signal level of the high frequency signal input from the transmission unit to the reception unit can be adjusted by the attenuator, so that the minimum input level of the high frequency signal received by the reception unit is confirmed. Is possible.

  The semiconductor test apparatus preferably includes an amplifier that amplifies the high-frequency signal in a communication path from a semiconductor set on the transmission side to a semiconductor set on the reception side.

  According to the above configuration, the signal level of the high-frequency signal input to the receiving unit can be adjusted by the amplifier, so that the maximum input level of the high-frequency signal received by the receiving unit can be confirmed. .

  In order to solve the above problems, the communication module test apparatus of the present invention alternately transmits and receives the communication modules in pairs among two or more communication modules having a transmission unit and a reception unit capable of bidirectional communication with a high-frequency signal. A communication module test apparatus for testing a communication operation by transmitting a transmission control signal for setting a transmission control signal to one of the communication modules and a reception side to the other communication module. A reception setting control means for transmitting a reception control signal to be set, a data transmission means for transmitting transmission data to the one communication module, a data reception means for receiving reception data from the other communication module, and the above The transmission data is compared with the received data, and the communication result of the communication module is determined based on the comparison result. It is characterized in that it comprises a determining data comparison determination unit.

Moreover, in order to solve the above-mentioned problem, the communication module test method for the communication module test apparatus according to the present invention is the communication module of the two or more communication modules having a transmitter and a receiver capable of bidirectional communication with a high-frequency signal. A communication module test method of a communication module test apparatus for testing communication operation by alternately transmitting and receiving modules in pairs, the step of transmitting a transmission control signal to be set on the transmission side to one of the communication modules,
Transmitting a reception control signal to be set on the reception side to the other communication module; transmitting transmission data to the one communication module; receiving reception data from the other communication module; And comparing the transmission data and the reception data, and determining the quality of the communication operation of the communication module from the comparison result.

  According to the above configuration, the communication module test apparatus of the present invention transmits a control signal set on the transmission side to one communication module, transmits a control signal set on the reception side to the other communication module, Transmission data for converting into a high frequency signal is transmitted to one communication module set on the transmission side. Then, the communication modules perform high-frequency signal communication, demodulate the high-frequency signal received by the other communication module set on the receiving side, and transmit the demodulated data to the communication module test apparatus as received data.

  After that, the communication module test apparatus of the present invention receives the received data from the communication module, compares the transmitted data and the received data, confirms whether the data matches or not from the comparison result, and the communication operation of the communication module is good. Therefore, a high-frequency dedicated tester for testing a high-frequency signal becomes unnecessary.

  In other words, a tester having basic functions that can transmit and receive data, control the operation of the communication module, and check the operation of DC characteristics and a wide range of logic functions may be used. Therefore, it is possible to use a general-purpose tester that is not dedicated and that can be tested with a widely used facility.

  Also, normally, data generated on the tester side generates a high-frequency signal for confirming communication operation by a communication module. Therefore, it is not necessary to create a high-frequency signal for confirming the communication operation by the tester before the test, so that the time required for the creation can be reduced. Therefore, the test time can be used effectively, and the test time per unit can be shortened.

  As described above, in the communication module test apparatus of the present invention, the test time can be shortened, and the communication operation can be tested with a general-purpose tester.

  In addition, since it is possible to test communication before being mounted on an actual machine, it is possible to detect defective products before shipping and ship non-defective products.

  In order to solve the above problems, a wafer test apparatus according to the present invention includes a pair of two or more dies formed on a wafer having a transmitter and a receiver capable of bidirectional communication with a high-frequency signal. A wafer test apparatus for testing communication operations by alternately transmitting and receiving, wherein a transmission setting control means for transmitting a transmission control signal to be set on the transmitting side is transmitted to one of the dies, and a receiving side is connected to the other die. A reception setting control means for transmitting a reception control signal to be set, a data transmission means for transmitting transmission data to the one die, a data receiving means for receiving reception data from the other die, and the transmission data And a data comparison / determination unit that determines whether the communication operation of the die is good or not based on the comparison result.

  Further, in order to solve the above problems, a wafer test method for a wafer test apparatus according to the present invention includes two or more dies formed on a wafer having a transmitter and a receiver capable of bidirectional communication with a high-frequency signal. A wafer test method of a wafer test apparatus for testing a communication operation by alternately transmitting and receiving the dies in pairs, the step of transmitting a transmission control signal to be set on the transmission side to one of the dies, and the other Transmitting a reception control signal to be set on the receiving side to the die, transmitting transmission data to the one die, receiving reception data from the other die, and the transmission data And a step of comparing the received data and determining the quality of the communication operation of the die from the comparison result.

  According to the above configuration, the wafer test apparatus of the present invention transmits a control signal set on the transmission side to one die, transmits a control signal set on the reception side to the other die, and sends it to the transmission side. Transmission data to be converted into a high frequency signal is transmitted to one of the set dies. Then, the dies perform high frequency signal communication, the high frequency signal received by the other die set on the receiving side is demodulated, and the demodulated data is transmitted as reception data to the wafer test apparatus.

  Thereafter, the wafer test apparatus of the present invention receives the received data from the die, compares the transmitted data with the received data, confirms whether the data matches or not from the comparison result, and determines whether the communication operation of the die is good. Therefore, a dedicated high-frequency tester for testing a high-frequency signal is not necessary.

  In other words, a tester having basic functions that can transmit and receive data, control the operation of a die, and check the operation of DC characteristics and a wide range of logic functions may be used. Therefore, it is possible to use a general-purpose tester that is not dedicated and that can be tested with a widely used facility.

  Also, data generated on the tester side usually generates a high-frequency signal for communication operation confirmation by a die. Therefore, it is not necessary to create a high-frequency signal for confirming the communication operation by the tester before the test, so that the time required for the creation can be reduced. Therefore, the test time can be used effectively, and the test time per unit can be shortened.

  As described above, in the wafer test apparatus of the present invention, the test time can be shortened and the communication operation can be tested even with a general-purpose tester.

  In addition, since the test is performed in the wafer state, it is possible to detect a defective product at the initial stage of the manufacturing process. In particular, when a semiconductor chip having a function capable of two-way communication is barely mounted, a test can be performed only in a wafer state, so that a test tester can perform a high-frequency signal communication test while performing a wafer state test. It leads to reduction of defects and is very effective.

  In the wafer test apparatus, one of the plurality of dies is selected as a die to be set on the receiving side, and the switching unit that connects the selected die to the die set on the transmitting side, It is preferable to provide switching control means for controlling the switching unit by selecting a die to be set on the receiving side from a plurality of dies and transmitting a switching signal for switching the connection.

  According to the above configuration, the switching unit transmitted from the switching control means causes the switching unit to connect to the die set on the transmitting side as a die that sets one of the plurality of dies on the receiving side. It becomes possible to test while combining each die.

  In addition, since it is possible to perform a test while combining each die, whether the communication is normal for each of the transmission operation and the reception operation by checking the transmission operation and the reception operation of each die. It becomes possible to confirm whether or not.

  Further, as the number of dies is increased, the problem that the data comparison / determination means determines that a non-defective product is a defective product can be improved.

  Further, the wafer test apparatus includes a probe card used for connecting to a die for testing communication operation on the wafer and causing the die to input and output signals necessary for testing the communication operation. It is preferable.

  According to the above configuration, the probe card is connected to the die for inputting / outputting the input / output signal, so that the input / output signal can be easily input / output from the test target die.

  The wafer test apparatus preferably includes an attenuator for attenuating the high-frequency signal in a communication path from a die set on the transmitting side to a die set on the receiving side.

  According to the above configuration, the signal level of the high frequency signal input from the transmission unit to the reception unit can be adjusted by the attenuator, so that the minimum input level of the high frequency signal received by the reception unit is confirmed. Is possible.

  The wafer test apparatus preferably includes an amplifier that amplifies the high-frequency signal in a communication path from a die set on the transmitting side to a die set on the receiving side.

  According to the above configuration, the signal level of the high-frequency signal input to the receiving unit can be adjusted by the amplifier, so that the maximum input level of the high-frequency signal received by the receiving unit can be confirmed. .

  The wafer test apparatus preferably includes a shielded cable that communicates the high-frequency signal, connects the receiving unit directly from the transmitting unit of the die, and contacts and fixes the probe card.

  According to the above configuration, since the shielded cable is fixed in contact with the probe card, it is stable and the receiving unit is directly connected from the transmitting unit of the die, so that leakage of high-frequency signals can be suppressed.

  In order to solve the above-described problem, the wafer of the present invention includes wiring for connecting the transmitting unit of one die to the receiving unit of the other die on a scribe region other than the die of the wafer. It is characterized by.

  According to the above configuration, since the wiring is provided on the scribe region that is an area other than the die of the wafer, there is no need for a special configuration associated with the wiring, and it is the same as mounting the chip component on the wafer. In addition, it is possible to simultaneously mount the wafer on any number of locations according to the number of dies.

  Further, the wafer preferably includes a switch for switching a path from the transmitting unit of the one die to the receiving unit of the other die on the scribe region.

  According to the above configuration, the switch switches the path from the transmission unit of one die to the reception unit of the other die, so that the combination of the transmission unit and the reception unit of each die can be changed. .

  Also, since the switch is provided on the scribe area, there is no need for a special configuration accompanying the provision of the switch. Similarly to mounting chip parts on the wafer, the wafer can be placed at any number of locations according to the number of dies. It can be mounted on the top simultaneously.

  In the wafer, it is preferable that a pad for inputting / outputting a signal is provided on the switch on the scribe region.

  According to the above configuration, since the switch is provided with the pad for inputting / outputting a signal, it is possible to input / output a signal to / from the switch with a simple configuration including the pad.

  The wafer preferably includes die switching control means for controlling the path by transmitting a switching signal instructing switching to the switch.

  According to the above configuration, the switch switches the path from the transmission unit of one die to the reception unit of the other die by the switching signal transmitted from the die switching control unit, so that it is possible to combine the dies. It becomes.

  As described above, the semiconductor test apparatus of the present invention has a transmission setting control means for transmitting a transmission control signal to be set on the transmission side to one of the semiconductors, and a reception control signal to be set on the reception side on the other semiconductor. Receiving setting control means for transmitting data, data transmitting means for transmitting transmission data to said one semiconductor, data receiving means for receiving received data from said other semiconductor, said transmission data and said receiving data Since the data comparison and determination means for determining whether the semiconductor communication operation is good or not based on the result of the comparison and the comparison is provided, the test time can be shortened and the communication operation can be tested even with a general-purpose tester. .

[Embodiment 1]
An embodiment of the present invention will be described with reference to FIGS.

  FIG. 1 is a block diagram showing a configuration of a semiconductor test apparatus 10 of the present embodiment. As shown in FIG. 1, the semiconductor test apparatus 10 according to the present embodiment includes a logic tester 1, a DUT 2, and a DUT 3, and tests whether the transmission / reception communication operations of the DUT 2 and the DUT 3 are normal. It is a device.

  Further, in the semiconductor test apparatus 10, the signal level input to the receiving side DUT is managed, and all the wires are provided so that the sensitivity of the signal level can be confirmed. Then, data transmission / reception is performed via the wiring.

  The logic tester 1 is not a dedicated tester that designates a measurement target, but a logic tester that performs a test on a logic circuit target having a high clock frequency of 20 to 30 MHz. Regardless of the application, it is an old version of a tester that is generally inexpensive and is designed to check the operation of DC characteristics and a wide range of logic functions with a clock that exceeds the signal transmission speed.

  For example, there are Advantest's T33 ** series and Yokogawa's T1000 class tester as an old version of the tester. These testers have a clock frequency of several tens of MHz and are general-purpose LSI testers of one or two generations before.

  In the latest LSI tester, for example, the clock frequency is 100 to 300 MHz, and the value of the clock frequency of the logic tester 1 is different by one digit. However, in general, the old version of the tester has been depreciated, and the latest high-performance high-speed clock LSI may not be tested. It is preferable to use the tester effectively.

  2, the logic tester 1 includes a transmission setting control unit 1a as a transmission setting control unit, a reception setting control unit 1b as a reception setting control unit, a data transmission unit 1c as a data transmission unit, and a data reception. A data receiving unit 1d as means, a data comparison / determination unit 1e as data comparison / determination unit, and a switching control unit 1f as switching control unit are provided.

  For example, the transmission setting control unit 1a transmits to the DUT 2 a control signal that modulates the transmission data received from the data transmission unit and transmits the modulated high-frequency signal from the transmission unit of the DUT 2 to the reception unit of the DUT 3. That is, it controls that the DUT is set on the transmission side.

  For example, the reception setting control unit 1b causes the DUT 3 to receive a high-frequency signal transmitted from the transmission unit of the DUT 2, demodulates and decodes the received high-frequency signal, and transmits the demodulated data to the data reception unit as reception data. Control signal to be transmitted. That is, it controls that the DUT is set on the receiving side.

  The data transmission unit 1c creates digital data and transmits the created digital data to the transmission side DUT set by the transmission setting control unit 1a. The data receiving unit 1d receives digital data from the receiving side DUT set by the reception setting control unit 1b.

  The data comparison / determination unit 1e compares the transmission data and the reception data using the DC / function function, checks whether the data matches the comparison result, and determines whether the communication operation is good or bad. The switching control unit 1f transmits and controls a switching signal instructing switching to a switch described later.

  The logic tester 1 has a control port that can control the transmission and reception of digital data and the operation of the DUT, and can generate random data for checking the bit error rate.

  DUT2 and DUT3 are devices under test. In this embodiment, a semiconductor to be tested is arranged in each. The semiconductor includes a transmitter and a receiver, and is a direct conversion digital modulation / demodulation type communication having a function of performing frequency conversion and bidirectional communication with a high-frequency signal (RF signal). However, in a semiconductor, a control circuit for achieving the above functions is provided in advance.

  Next, the operation of the semiconductor test apparatus 10 of the present embodiment will be described with reference to FIG. Here, for example, it is assumed that DUT2 is set as the transmission side and DUT3 is set as the reception side.

  First, in the logic tester 1, the transmission setting control unit 1a transmits a control signal to be set on the transmission side to the DUT 2. Next, the reception setting control unit 1b transmits a control signal to be set on the reception side to the DUT 3.

  The control signal set on the transmission side includes a control signal that modulates transmission data received from the data transmission unit 1c of the logic tester 1 and transmits the modulated high-frequency signal from the transmission unit of the DUT 2 to the reception unit of the DUT 3. In addition, the control signal set on the receiving side receives a high-frequency signal transmitted from the transmission unit of the DUT 2, demodulates the received high-frequency signal, and receives data of the logic tester 1 using the demodulated data as received data A control signal to be transmitted to the unit 1d is included. As described above, whether the DUT 2 and the DUT 3 are the transmission side and the reception side is set by the two control signals.

  Next, the data transmission unit 1c creates transmission data as digital data to be transmitted to the DUT 2, and transmits the created transmission data to the DUT 2 (TX).

  The DUT 2 converts the input transmission data into an RF signal according to the control signal transmitted from the transmission setting control unit 1a, and transmits the converted RF signal to the DUT 3 (RF signal).

  The DUT 3 demodulates the input RF signal into digital data according to the control signal transmitted from the reception setting control unit 1b, and uses the demodulated digital data as reception data received by the data reception unit 1d. (RX).

  Note that direct conversion communication is performed between DUT 2 and DUT 3. However, FSK or ASK communication may be performed.

  Thereafter, in the logic tester 1, the data comparison / determination unit 1e uses the DC / function function to compare the transmission data transmitted to the DUT 2 with the reception data received from the DUT 3, and confirms the data match based on the comparison result. If it is determined that the communication is successful. Specifically, it is determined that communication between TX of DUT2 and RX of DUT3, that is, communication when DUT2 is on the transmission side and when DUT3 is on the reception side is Pass. Pass indicates that the communication is good.

  Similarly, when the DUT 2 is set to the receiving side and the DUT 3 is set to the transmitting side, the data comparison / determination unit 1e uses the DC / function function to receive data received from the DUT 2 and transmission data transmitted to the DUT 3. If the data match is confirmed from the comparison result, it is determined that the communication between the DUT 2 on the receiving side and the DUT 3 on the transmitting side is Pass.

  On the other hand, if the data comparison / determination unit 1e confirms that the data do not match, it determines that the communication has failed, and determines that communication between DUT2 and DUT3 is Fail. Fail indicates that there is a communication failure.

  As described above, the communication operation of DUT2 and DUT3 is tested by transmitting and receiving DUT2 and DUT3 alternately.

  As described above, in the semiconductor test apparatus 10 of the present embodiment, the transmission setting control unit 1a transmits the control signal set on the transmission side to the DUT 2, and the reception setting control unit 1b transmits the control signal set on the reception side. The data is transmitted to the DUT 3, and the data transmission unit 1c transmits the transmission data for converting the RF signal into the DUT 2 set on the transmission side. Then, the DUTs perform RF signal communication, the DUT 3 set on the receiving side demodulates the received RF signal, the demodulated data is transmitted as received data to the data receiving unit 1d, and the data receiving unit 1d receives the received data. Receive.

  After that, the data comparison / determination unit 1e uses the DC / function function to compare the transmission data and the reception data, confirms whether the data matches or not from the comparison result, and determines whether the communication operation of the DUT is good. This eliminates the need for a dedicated RF tester for testing the RF signal.

  In other words, the logic tester 1 can perform basic operations such as transmission and reception of digital data, semiconductor operation control, and DC characteristics and a wide range of logic function operations as in the above-described means 1a to 1f. It only needs to have a function. Therefore, it is possible to use a general-purpose logic tester that is not dedicated and that can be tested with a widely used facility.

  In general, a digital signal waveform created on the tester side generates an RF signal for confirming communication operation by the DUT. Therefore, it is not necessary to create a high-frequency signal for confirming communication operation by the logic tester 1 before the test, so that the time required for the creation can be reduced. Therefore, the test time can be used effectively, and the test time per unit can be shortened.

  As described above, in the semiconductor test apparatus 10 of the present embodiment, the test time can be shortened, and the general-purpose logic tester 1 can test the transmission / reception communication operation.

  Further, since the logic tester 1 is not an expensive dedicated tester developed for a specific application but an inexpensive old version of the tester, the equipment cost for the tester can be reduced. Therefore, it is possible to reduce the test cost and to effectively use the existing tester, so that it is possible to construct a very useful test environment.

  Further, if a test is performed within a frequency range in which the semiconductor test apparatus 10 can communicate, it is possible to confirm a frequency band in which the semiconductor communicates. Furthermore, if a test is performed within a frequency range in which the semiconductor test apparatus 10 can communicate, the frequency band of the semiconductor to be communicated can be confirmed.

  Further, in the semiconductor test apparatus 10 of the present embodiment, the semiconductor to be tested is placed in the DUT 2 and DUT 3 by a handler (not shown). The handler is an apparatus that automatically supplies the completed semiconductors simultaneously to the DUT 2 and DUT 3 and automatically classifies and stores the completed semiconductors based on the test results.

  Therefore, in the semiconductor test apparatus 10, since the semiconductors are automatically arranged at the same time by the handler and automatically classified and stored based on the test result, the operation of arranging and taking out the semiconductors is not necessary. Since the time required for the operation is shortened, the entire test time can be shortened.

  As shown in FIG. 3, an attenuator or amplifier 21 may be provided between the DUTs that perform RF signal communication. FIG. 3 is a block diagram showing a configuration of the semiconductor test apparatus 20 of the present embodiment.

  The semiconductor test apparatus 20 of the present embodiment includes an attenuator or amplifier 21 that attenuates or amplifies the RF signal in the communication path from the DUT 2 to the DUT 3 in addition to the configuration of the semiconductor test apparatus 10 shown in FIG. ing.

  Therefore, since the signal level of the RF signal input to the receiving side DUT can be adjusted by the attenuator or the amplifier 21, the minimum input level or the maximum input level of the RF signal received by the receiving side DUT is confirmed. It becomes possible.

  Also, as shown in FIG. 4, a switch 31 and a switch 32 as a switching unit may be provided between the DUTs that perform RF signal communication. FIG. 4 is a block diagram showing a configuration of the semiconductor test apparatus 30 of the present embodiment.

  The semiconductor test apparatus 30 of the present embodiment includes a switch 31 and a switch 32 in addition to the configuration of the semiconductor test apparatus 20 shown in FIG.

  The switch 31 and the switch 32 are controlled to switch the attenuator or the amplifier 21 between when the DUT is not inserted and when the attenuator or the amplifier 21 is not switched according to the switching signal instructing the switching transmitted from the switching control unit 1f of the logic tester 1. It is a switch to be done.

  Therefore, the minimum input level or the maximum input level of the RF signal received by the receiving side DUT is confirmed while comparing the case where the attenuator or amplifier 21 is inserted into the communication path from the DUT 2 to the DUT 3 with the case where the attenuator or amplifier 21 is not included. It becomes possible.

  As described above, in the semiconductor test apparatuses 10 to 30 according to the first embodiment, a test is performed using two DUT pairs. However, even if only one of the two DUT pairs is a non-defective product, when the test is performed by this method, both of the pairs are determined to be defective. Therefore, a method for improving this problem by increasing the number of DUTs and performing a test by combining the DUTs will be described in the second embodiment.

[Embodiment 2]
The following will describe another embodiment of the present invention with reference to FIGS. Configurations other than those described in the present embodiment are the same as those in the first embodiment. For convenience of explanation, members having the same functions as those shown in the drawings of Embodiment 1 are given the same reference numerals, and descriptions thereof are omitted.

  FIG. 5 is a block diagram showing a configuration for switching the semiconductor test apparatus 40 of the present embodiment. The semiconductor test apparatus 40 according to the present embodiment tests four DUTs, and includes a logic tester 1, DUTs 41 to DUT 44, and a switch 45 as a switching unit as shown in FIG.

  DUT 41 to DUT 44 are devices under test. In the present embodiment, a semiconductor is arranged for each. The switch 45 is a switch that is controlled to switch the combination of the transmission side and the reception side of the DUTs 41 to 44 by a switching signal instructing switching that is transmitted from the switching control unit 1 f of the logic tester 1.

  Next, the operation of the semiconductor test apparatus 40 of the present embodiment will be described with reference to FIGS. FIG. 6 is a flowchart showing a combination example of the transmission side and the reception side of DUT 41 to DUT 44 in the semiconductor test apparatus 40 of the present embodiment.

  First, the transmission setting control unit 1a of the logic tester 1 transmits a control signal to the DUT 41, and sets the DUT 41 to the transmission side (step S1).

  Next, the reception setting control unit 1b transmits a control signal to the DUT 42 to DUT 44 to set the DUT 42 to DUT 44 to the reception side. The switching control unit 1f transmits a switching signal instructing the switching to the switch 45, and controls the switch 45, so that the data comparison determination unit 1e transmits the data transmission unit 1c while the switch 45 sequentially switches the receiving side. The transmission data transmitted to the reception side is compared with the reception data received by the data reception unit 1d on the reception side, and it is confirmed from the comparison result whether or not the communication is normal (step S2).

  After confirming step S2, the transmission setting control unit 1a transmits a control signal to the DUT 42, and sets the DUT 42 to the transmission side (step S3).

  Next, the reception setting control unit 1b transmits a control signal to the DUT 41 and the DUTs 43 and 44 to set the DUT 41 and the DUTs 43 and 44 to the reception side. The switching control unit 1f transmits a switching signal instructing the switching to the switch 45, and controls the switch 45, so that the data comparison determination unit 1e transmits the data transmission unit 1c while the switch 45 sequentially switches the receiving side. The transmission data transmitted to the reception side is compared with the reception data received by the data reception unit 1d on the reception side, and it is confirmed from the comparison result whether or not the communication is normal (step S4).

  Similarly, in order, the transmission setting control unit 1a sets the DUT 43 to the transmission side (step S5), the reception setting control unit 1b sets the DUTs 41 and 42 and the DUT 44 to the reception side, and the data comparison determination unit 1e It is confirmed whether or not the communication is normal (step S6).

  Further, the transmission setting control unit 1a sets the DUT 44 to the transmission side (step S7), the reception setting control unit 1b sets the DUTs 41 to 43 to the reception side, and the data comparison determination unit 1e determines whether the communication is normal. (Step S8).

  After step S8 in which all four DUTs are set on the transmission side and communication is confirmed, in the logic tester 1, the data comparison / determination unit 1e determines that each DUT is in accordance with each result (steps S2, S4, S6, S8). Determine the quality of communication. The above results are organized as shown in FIG. FIG. 7 shows a table in which the results in the flowchart shown in FIG. 6 are organized.

  For example, in step S1 and step S2 of FIG. 6, in step S1, DUT 41 is set on the transmission side, and in step S2, DUT 42 to DUT 44 are set on the reception side, and it is confirmed whether or not communication is normal.

  If the reception of the DUT 42 is confirmed normally, Pass is entered in the column where DUT 41_TX and DUT 42_RX cross in the table shown in FIG. 7, and Fail is entered in the case of communication failure. In order, the communication test result of step S2 is entered in the column of the row of DUT 41_TX.

  In this manner, the table is filled in order according to the flowchart of FIG. 6, and if at least one Pass is confirmed in one row in the table, it is determined that TX of DUT * is Pass (determination 1). . Further, if at least one Pass is confirmed in one row in the table, it is determined that RX of DUT * is Pass (determination 2). Finally, if both DUT * _TX and DUT * _RX are Pass, it is determined that DUT * is a non-defective product that satisfies the transmission / reception communication operation (determination 3).

  Therefore, in the semiconductor test apparatus 40 of the present embodiment, the switch 45 is set as a DUT that causes the receiving side to set one of the plurality of DUTs according to the switching signal transmitted from the switching control unit 1f of the logic tester 1. Since the connection is made to the DUT set on the transmission side, it is possible to perform a test while combining each DUT pair.

  In addition, since it is possible to perform a test while combining each DUT, whether the communication is normal for each of the transmission operation and the reception operation by performing the test while confirming the transmission operation and the reception operation of each DUT. It becomes possible to confirm whether or not.

  In the present embodiment, the case where four DUTs are tested has been described. However, the present invention is not limited to this, and the number of DUTs can be increased within the limit of the number of test pins of the logic tester 1. In this case, as the DUT is increased, the problem that the data comparison determination unit 1e determines that a non-defective product is a defective product can be improved.

  Here, the semiconductor is not used as such but as a component. In particular, a semiconductor having a communication function is configured as a communication module together with a plurality of components. The communication module has a size of about 1 mm square and a height of several mm, for example, and is mounted on a real machine having a communication function.

  Therefore, even in a communication module composed of a semiconductor having a communication function, for example, if the communication module is arranged in the DUT 2 and the DUT 3 shown in FIG. 1, the communication operation of the communication module is tested in the same manner as in the case of arranging the semiconductor. It is possible.

  Therefore, it is possible to test communication before mounting on an actual machine, detect defective products before shipping, and ship non-defective products.

  In addition, as with semiconductors, communication modules are automatically arranged at the same time by a handler, and automatically classified and stored based on test results, so there is no need to place or remove communication modules and store them in a classified manner. Since the time required for the above operation is shortened, the entire test time can be shortened.

[Embodiment 3]
The following will describe another embodiment of the present invention with reference to FIGS. Configurations other than those described in the present embodiment are the same as those in the first embodiment and the second embodiment. For convenience of explanation, members having the same functions as those shown in the drawings of Embodiment 1 and Embodiment 2 are given the same reference numerals, and explanation thereof is omitted.

  In the first embodiment and the second embodiment, the communication test of the assembled semiconductor and communication module has been described. In the present embodiment, a communication test in a wafer state will be described.

  FIG. 8 is a schematic diagram showing the configuration of the wafer test apparatus 50 of the present embodiment. A wafer test apparatus 50 according to the present embodiment includes a logic tester 1 (not shown) and performs a test on a die formed on the wafer 51. In the present embodiment, the wafer test apparatus 50 shown in FIG. As shown, testing is performed on two dies, die 52 and die 53. The wafer test apparatus 50 according to the present embodiment includes a probe card 54 and a shield cable 55.

  The probe card 54 is connected to the logic tester 1 and is connected to the bonding pads of the die 52 and the die 53 to input / output the potential and signals necessary for the communication test output from the logic tester 1. It is a test jig used for performing a test. The probe card 54 has, for example, a structure in which a probe (test probe) is attached to a printed wiring board. Electrical connection is made by pressing the bonding pads of the die 52 and the die 53 after positioning them with respect to the probe card.

  The shielded cable 55 is a cable for communicating an RF signal, and is appropriately connected to a place to be tested on the probe card.

  In the wafer test apparatus 50 of the present embodiment, potentials and signals necessary for the communication test are output from the logic tester 1 through the probe card 54 to the die 52 and the die 53, and the RF signal is communicated by the shield cable 55. As with the assembled semiconductor and communication module, it is possible to determine whether the communication operation is good or bad.

  Therefore, since the wafer is in a state before the semiconductor is manufactured, the wafer test apparatus 50 according to the present embodiment can detect defective products at the initial stage of the manufacturing process. In particular, when a semiconductor chip having a function capable of bidirectional communication is barely mounted, the test can be performed only in the wafer state. Therefore, the logic tester 1 can perform the RF signal communication test while performing the wafer state test. This leads to a reduction in module defects and is extremely effective.

  Further, as shown in FIG. 9, an attenuator or amplifier 61 may be provided in a shielded cable 55 that performs communication of RF signals. FIG. 9 is a schematic diagram showing the configuration of the wafer test apparatus 60 of the present embodiment.

  In addition to the configuration of wafer test apparatus 50 shown in FIG. 8, wafer test apparatus 60 of the present embodiment attenuates or amplifies an RF signal during a communication path from die 52 to die 53. It has.

  Therefore, since the signal level of the RF signal input to the receiving die can be adjusted by the attenuator or the amplifier 61, the minimum input level or the maximum input level of the RF signal received by the receiving die is confirmed. It becomes possible to do.

  Further, when RF signal leakage occurs and affects the test, as shown in FIGS. 10 and 11, the transmitting side die and the receiving side die may be directly connected by a shield type contact pin.

  FIG. 10 is a schematic diagram showing the configuration of the wafer test apparatus 70 of the present embodiment. FIG. 11 is a side view of the wafer test apparatus 70.

  The wafer test apparatus 70 of the present embodiment includes a shield type contact pin 71 and a contact pin support 72 that supports the shield type contact pin 71 in addition to the configuration of the wafer test apparatus 50 shown in FIG. .

  The shield-type contact pin 71 has a structure in which a PAD is attached to the pin tip. For example, there is a semi-rigid type wafer probe pin. The contact pin support 71 is connected to the probe card 53 and kept at the GND level.

  As shown in FIGS. 10 and 11, the shield-type contact pin 71 is fixed to the contact pin support 72 by soldering. Therefore, the contact pin 71 is stably fixed.

  Therefore, in wafer test apparatus 70 of the present embodiment, since the transmitting side die and the receiving side die are directly connected, it is possible to suppress leakage of the RF signal.

  In addition, as shown in FIG. 12, a wiring 82 may be formed in a scribe area 81 on the wafer 51. FIG. 12 is a schematic diagram showing the configuration of the wafer test apparatus 80 of the present embodiment.

  In addition to the configuration of wafer test apparatus 50 shown in FIG. 8, wafer test apparatus 80 of the present embodiment includes wiring 82 that performs RF signal communication with scribe area 81 on wafer 51. The scribe area 81 is an area other than the die on the wafer 51, and becomes a margin for cutting when the die is cut.

  Therefore, since the wiring 82 is formed in the scribe region 81 on the wafer 51, a special configuration associated with the provision of the wiring 82 is not necessary, and in the same way as mounting a chip part on the wafer 51, It is possible to simultaneously mount the wafer 51 on any number of locations according to the number.

  In addition, since the wiring 82 directly connects the transmission side die and the reception side die, it is possible to suppress leakage of the RF signal. The tested wiring 82 is cut and separated when the die is cut.

  As described above, in the semiconductor test apparatuses 50 to 80 according to the third embodiment, the test is performed using two die pairs. However, even if only one of the two die pairs is a non-defective product, both of the pairs are determined to be defective when tested by this method.

  Therefore, a method for improving this problem by increasing the number of dies and performing a test by combining dies will be described in the following fourth embodiment.

[Embodiment 4]
The following will describe another embodiment of the present invention with reference to FIG. 13 and FIG. The configuration other than that described in the present embodiment is the same as that of the third embodiment. For convenience of explanation, members having the same functions as those shown in the drawings of Embodiment 3 are given the same reference numerals, and descriptions thereof are omitted.

  FIG. 13 is a schematic diagram showing the configuration of the wafer 51 when the wafer test apparatus 90 according to the present embodiment is switched. The wafer test apparatus 90 according to the present embodiment tests four dies, and as shown in FIG. 13, dies 91 to 94 formed on the wafer 51, a switch 95 as a switching unit, and PADs 95 to 98 for controlling the switch are provided, and other configurations not shown are the same as those of the wafer test apparatus 50 of the third embodiment shown in FIG.

  The switch 95 is a switch that is controlled to switch the combination of the transmission side and the reception side of the die 91 to the die 94 by a switching signal instructing switching transmitted from the switching control unit 1f of the logic tester 1. The region 81 is provided.

  The switch control PADs 95 to 98 are PADs for causing the switch 95 to input and output a switching signal instructing switching transmitted from the switching control unit 1 f of the logic tester 1, and are provided in the scribe area 81.

  In wafer test apparatus 90 of the present embodiment, switching control unit 1 f of logic tester 1 transmits a switching signal for instructing switching to switch 45 to switch control PADs 95 to 98, and switch control PAD 95 to 98 switches the switch. A switching signal is input to 95 and the switch 95 is switched in accordance with the control signal, whereby the combinations of the transmitting side and the receiving side of the dies 91 to 94 are switched.

  Further, as shown in FIG. 14, the combination of the transmission side and the reception side of the dies 91 to 94 may be performed by control by transmitting a switching signal instructing switching from the dies 91 to 94.

  FIG. 14 is a schematic diagram showing the configuration of the wafer 51 when the wafer test apparatus 100 according to the present embodiment is switched. In wafer test apparatus 100 of the present embodiment, the die transmits the switching signal α to switch 95, whereby the combination of the transmitting side and the receiving side of die 91 to die 94 is switched.

  Therefore, in wafer test apparatus 90 and wafer test apparatus 100 of the present embodiment, switch 95 receives one of a plurality of dies by a switching signal transmitted from switching control unit 1f of logic tester 1 or from the die. Since the die set on the side is connected to the die set on the transmission side, it is possible to perform a test while combining pairs of each die.

  In addition, since it is possible to perform a test while combining each die, whether the communication is normal for each of the transmission operation and the reception operation by checking the transmission operation and the reception operation of each die. It becomes possible to confirm whether or not.

  In the present embodiment, the case where four dies are tested has been described. However, the present invention is not limited to this, and the number of dies can be increased within the limit of the number of test pins of the logic tester 1. In this case, as the number of dies increases, the problem that the logic tester 1 determines that a non-defective product is a defective product can be improved.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the claims, and the technical means disclosed in different embodiments can be appropriately combined. Such embodiments are also included in the technical scope of the present invention.

  The present invention can be suitably used when a communication operation is tested in a manufacturing process for a product having a communication function.

It is a block diagram which shows one Embodiment of the semiconductor test apparatus in this invention. It is a block diagram which shows the structure of the logic tester in the said semiconductor test device. It is a block diagram which shows other embodiment of the semiconductor test apparatus in this invention. It is a block diagram which shows other embodiment of the semiconductor test apparatus in this invention. It is a block diagram which shows other embodiment of the semiconductor test apparatus in this invention. It is a flowchart which shows the example of a combination of the test of the said semiconductor test apparatus. It is a figure which shows the example of a test determination procedure of the said semiconductor test apparatus. It is a block diagram which shows one Embodiment of the wafer test apparatus in this invention. It is a block diagram which shows other embodiment of the wafer test apparatus in this invention. It is a block diagram which shows other embodiment of the wafer test apparatus in this invention. It is a side view of the wafer test apparatus. It is a block diagram which shows other embodiment of the wafer test apparatus in this invention. It is a block diagram which shows other embodiment of the wafer test apparatus in this invention. It is a block diagram which shows other embodiment of the wafer test apparatus in this invention. It is a block diagram which shows the conventional test apparatus.

Explanation of symbols

1 Logic Tester 1a Transmission Setting Control Unit (Transmission Setting Control Unit)
1b Reception setting control unit (reception setting control means)
1c Data transmission part (data transmission means)
1d Data receiving unit (data receiving means)
1e Data comparison determination unit (data comparison determination means)
1f Switching control unit (switching control means)
2,3 DUT (semiconductor)
DESCRIPTION OF SYMBOLS 10 Semiconductor test apparatus 20 Semiconductor test apparatus 21 Attenuator or amplifier 30 Semiconductor test apparatus 31, 32 Switch (switching part)
40 Semiconductor Test Equipment 41-44 DUT (Semiconductor)
45 switch (switching part)
DESCRIPTION OF SYMBOLS 50 Wafer test apparatus 51,52 Die 53 Probe card 54 Shielded cable 60 Wafer test apparatus 61 Attenuator or amplifier 70 Wafer test apparatus 71 Contact pin 72 Contact pin support 80 Wafer test apparatus 81 Wiring 90 Wafer test apparatus 91-94 Die 95 Switch (Switching part)
96-97 PAD
100 Wafer test equipment

Claims (19)

Of two or more semiconductors having a transmitter and a receiver capable of bidirectional communication with a high-frequency signal, a semiconductor test apparatus that tests communication operations by alternately transmitting and receiving the semiconductor in pairs,
Transmission setting control means for transmitting a transmission control signal to be set on the transmission side to one of the semiconductors,
A reception setting control means for transmitting a reception control signal to be set on the receiving side to the other semiconductor;
Data transmission means for transmitting transmission data to the one semiconductor;
Data receiving means for receiving received data from the other semiconductor;
A semiconductor test apparatus comprising: a data comparison / determination unit that compares the transmission data with the reception data and determines the quality of the communication operation of the semiconductor based on the comparison result. A switching unit that selects one of the plurality of semiconductors as a semiconductor to be set on the receiving side and connects the selected semiconductor to the semiconductor set on the transmitting side;
The switching unit includes switching control means for controlling the switching unit by selecting one semiconductor to be set on the receiving side from a plurality of semiconductors and transmitting a switching signal for switching connection. The semiconductor test apparatus according to claim 1.   The semiconductor test apparatus according to claim 1, further comprising a handler that automatically supplies the semiconductor simultaneously after assembly is completed, and automatically classifies and stores the semiconductor based on a test result.   3. The semiconductor test according to claim 1, further comprising an attenuator for attenuating the high-frequency signal in a communication path from the semiconductor set on the transmitting side to the semiconductor set on the receiving side. apparatus.   3. The semiconductor test apparatus according to claim 1, further comprising an amplifier that amplifies the high-frequency signal in a communication path from the semiconductor set on the transmission side to the semiconductor set on the reception side. . A semiconductor test method of a semiconductor test apparatus for testing a communication operation by alternately transmitting and receiving the above semiconductors in pairs among two or more semiconductors having a transmitter and a receiver capable of bidirectional communication with a high-frequency signal. ,
One of the semiconductors, transmitting a transmission control signal to be set on the transmission side;
Transmitting the reception control signal to be set on the receiving side to the other semiconductor;
Transmitting transmission data to the one of the semiconductors;
Receiving received data from the other semiconductor;
A step of comparing the transmission data with the reception data, and determining the quality of the semiconductor communication operation based on the comparison result. Among two or more communication modules having a transmission unit and a reception unit capable of bidirectional communication with a high-frequency signal, a communication module test device that tests a communication operation by alternately transmitting and receiving the communication module in pairs,
Transmission setting control means for transmitting a transmission control signal to be set on the transmission side to one of the communication modules,
A reception setting control means for transmitting a reception control signal to be set on the receiving side to the other communication module;
Data transmission means for transmitting transmission data to the one communication module;
Data receiving means for receiving received data from the other communication module;
A communication module test apparatus comprising: a data comparison / determination unit that compares the transmission data with the reception data and determines the quality of the communication operation of the communication module based on the comparison result. Communication module test of a communication module test apparatus that tests communication operation by transmitting and receiving the communication modules alternately in pairs among two or more communication modules having a transmitter and a receiver capable of bidirectional communication with a high-frequency signal A method,
Transmitting a transmission control signal to be set on the transmission side to one of the communication modules;
Transmitting the reception control signal to be set on the receiving side to the other communication module;
Transmitting transmission data to the one communication module;
Receiving received data from the other communication module;
Comparing the transmission data with the reception data, and determining whether the communication operation of the communication module is good or not based on the comparison result. A wafer test apparatus for testing communication operations by alternately transmitting and receiving the above-mentioned dies in pairs among two or more dies formed on a wafer having a transmitter and a receiver capable of bidirectional communication with a high-frequency signal. There,
Transmission setting control means for transmitting a transmission control signal to be set on the transmitting side to one of the dies,
A reception setting control means for transmitting a reception control signal to be set on the receiving side to the other die;
A data transmission means for transmitting transmission data to the one die;
Data receiving means for receiving received data from the other die;
A wafer test apparatus comprising: a data comparison / determination unit that compares the transmission data with the reception data and determines whether the communication operation of the die is good or not based on the comparison result.   Select one of the above dies as a die to be set on the receiving side, and connect the selected die to the die set on the transmitting side. 10. The wafer test apparatus according to claim 9, further comprising switching control means for controlling the switching unit by selecting one die to be set to be transmitted and transmitting a switching signal for switching connection.   10. A probe card used for connecting to a die for testing a communication operation on the wafer and causing the die to input and output signals necessary for testing the communication operation. The wafer test apparatus described in 1.   12. The wafer test according to claim 10, further comprising an attenuator for attenuating the high-frequency signal in a communication path from a die set on the transmitting side to a die set on the receiving side. apparatus.   12. The wafer test apparatus according to claim 10, further comprising an amplifier that amplifies the high-frequency signal in a communication path from a die set on the transmitting side to a die set on the receiving side. .   The wafer test apparatus according to claim 11, further comprising a shielded cable that directly connects a receiving unit to a receiving unit of the die that performs communication of the high-frequency signal and that is fixed in contact with the probe card. . Of two or more dies formed on a wafer having a transmitter and a receiver capable of bidirectional communication with a high-frequency signal, a wafer test apparatus for testing a communication operation by alternately transmitting and receiving the dies in pairs A wafer test method comprising:
Transmitting a transmission control signal to be set on the transmitting side to one of the dies;
Transmitting the reception control signal to be set on the receiving side to the other die, and
Transmitting transmission data to the one die, and
Receiving received data from the other die;
Comparing the transmitted data with the received data, and determining whether the communication operation of the die is good or not based on the comparison result.   A wafer comprising: a scribe region which is a region other than a die of a wafer; and a wiring for connecting a transmitting unit of one die to a receiving unit of the other die.   The wafer according to claim 16, further comprising a switch for switching a path from the transmitting unit of the one die to the receiving unit of the other die on the scribe region.   The wafer according to claim 17, further comprising a pad for inputting and outputting signals to the switch on the scribe region.   18. The wafer according to claim 17, further comprising die switching control means for controlling the path by transmitting a switching signal instructing switching to the switch.

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